The device receiving information from a channel

 

(57) Abstract:

The invention relates to telecommunications systems and can be used in systems for receiving digital data broadcasting systems. The technical result of the invention is to improve the noise immunity and increased functionality of the device due to the possibility of joint operation of multiplexed channels asynchronously accept packages. For this purpose, the device comprises a data selector, the selector start of the service, the allocation of data characters, a selector, a channel number, a shift register, a buffer register, the correction pattern of the numbers of channels and packages, the control circuit record, the count numbers of the packages, the trigger bit half block diagram of the detection of the halves of the block, the character count package data elements And the counter unit, the adder, the buffer memory data blocks, the decoder error-correcting code, the buffer memory data. 4 Il.

The invention relates to telecommunications systems, and in particular to systems data broadcast by radio and television channels and mainly can be used in systems with the introduction of data for the duration of the vertical quenching pulse telemig during human quenching interval of the television signal [1] , contains the allocation of the digital data inserted into the video signal; means for detecting errors in data transmitted during the period of the line scan; a buffer memory for temporary storage of these data; correcting errors in the data.

The known device allows to correct multiple bit errors in the received data packets by using the majority-decodable code.

The disadvantage of this device is not sufficiently high noise immunity due to the impossibility of error correction type inserts or deposition packages.

A device for receiving data from a channel playback information storage tape [2], containing the power play, a buffer memory, a method of forming the recording address, a method of forming the address reading circuit detecting a synchronization code blocks, the scheme determine the address of the code synchronization circuit detection/error correction scheme definition identifies the data block, the address arithmetic circuit, the detection circuit address identifies the data sector, the scheme of reading data of the preamble.

The known device allows you to fix the sector, and reliably determine the beginning of the sector.

The disadvantages of the device include:

1) not enough high noise immunity due to the impossibility of error correction type inserts or precipitation data blocks in the composition of the sectors;

2) the device may not operate in multiplexed channels with asynchronous appearance packages.

The closest to the technical nature of the claimed solution is selected as a prototype device of the optical recording and reproducing data [3] processing data from channel playback from an optical storage media. The device prototype contains a demodulator, the schema definition of the beginning of the package, a series-parallel Converter, a register-latch the batch number, the scheme of detecting and correcting errors in the numbers of packets, the control circuit of the write/read buffer memory for data blocks, the scheme of detecting and correcting errors in the data blocks, the buffer memory data. In addition, the device prototype contains modulation scheme, the multiplexer address, the ROM for the organization interleave symbols of the code words of the data block diagram of the playback clock buffer elements with Tr the Le package number package restores room in case of distortions of his errors, uses this number as part of the address for recording the contents of the packet in the buffer memory for data blocks. Then, the block data collected in this buffer memory is processed by a circuit for detection and correction of errors and shall be transmitted in the buffer memory for the data.

Using recorded at the beginning of the package of markers of the beginning of the package allows you to limit the propagation of errors caused by insertions or deposition bit outside the current package. The application is written in the beginning of the batch numbers for placing the packet in the buffer memory limits the propagation of errors caused by insertions or deposition packet data block. The detection scheme and error correction on the basis of powerful error-correcting block codes type of reed - Solomon codes with interleaving ensures high reliability of the playback information playback channels optical drives.

The device prototype is designed to work with demultiplexing channels with simultaneous appearance packages. In such channels, the packet data block appear sequentially at fixed time intervals MBA is the inability to deal with multiplexed channels with asynchronous appearance package, providing for the organization of multiple virtual channels in a single broadcast, in which each successive packet data block can appear in an arbitrary time interval.

An object of the invention is to expand the functional capabilities of the device to provide robust building block information of the asynchronously received packets, transmitted by the multiplexed information channels.

The technical problem is solved due to the fact that in the known device containing the data selector, the selector start of the service, the allocation of data characters, a shift register, a buffer register, the correction pattern of the numbers of channels and packages, the control circuit record, the count numbers of the packages, the character count package data buffer memory data blocks, the decoder error-correcting code, the buffer memory data, and the input of the data selector connected to the bus of the information signal, the output serial data of the data selector is connected to the input serial data of the shift register, the output clock frequency data of the data selector is connected to the synchronization input of the shift register and with the first the data buffer register and the first input of the selector start of the service, the second inputs of the selector start of the package connected to the bus code to the beginning of the packet, the output selector the beginning of the package is connected to the second input of the differential allocation of data characters, the output of the circuit selection data symbols are connected to the input write buffer register and a second input of the control circuit record, the fourth input of which is connected to the bus clock frequency symbol processing on the packet data, the outputs of buffer register connected m-bit data bus to the inputs of the correction patterns of the numbers of channels and packages and inputs the data of buffer memory data blocks, the first input of the control circuit record connected with the output characteristic of the decoding error correction circuits numbers of channels and packages, the first outputs of the correction patterns of the numbers of channels and packages are connected to the n-bit bus of service with the input data number counter of packets, the third output of the control circuit record connected with a counter input number counter of packets with a first reset input of the counter of the symbols of the data packet, the fourth circuit output control record is connected to the input of the record number counter of packets and the second reset input of the counter of the symbols of the data packet, the fifth circuit output control record is connected to the counting input of the counter symbol is the address of the buffer memory data blocks, the outputs of the character counter data package connected n1 - bit address bus of the symbol data packet with a third address inputs ,data blocks, the data outputs of decoder error-correcting code are connected by a data bus to the input data buffer memory data, address inputs which are connected to the address bus with the second outputs of the address decoder error correcting code according to the invention introduced the selector channel number, the trigger bit half block detection circuit halves of the block, the first element And the counter unit and the adder, the input selector channel number connected to the m1-bit bus channel number with the fourth outputs of the correction patterns of the numbers of channels and packages the second inputs of the selector channel number connected to the m1-bit bus code channel number, the output selector channel number connected to the third input of the control circuit record, the second circuit output correction numbers of channels and packages connected to the first input of the differential detection of half blocks and input data trigger bit half block, the first circuit output control record is connected to the synchronization input of the trigger bit half block, the second output of the control circuit record connected with the second input of the differential detection halves of the blocks, the th is connected to the first circuit output detection halves of the block, the second output of which is connected to the counting input of the counter unit, the output of the first element And is connected to the carry-in input of the adder, the data inputs of the counter unit is connected to an n2 - bit bus start address of the data blocks in the buffer memory block data entry entry counter unit connected to the bus "Download", the outputs of the counter unit connected to the n2 - bit bus with the first data inputs of the adder, the second input data which is connected to an n2 - bit bus logic zero, the outputs of the adder are connected to the n2 - bit address bus unit with the second input of the address buffer memory data blocks, moreover, the detection scheme halves of the unit contains an inverter, the second and third elements, the first, second, third and fourth elements AND IS NOT counter the first half of the block counter of the second half of the block, the first and second decoders and the trigger half block, the first input of the differential detection of the halves of the block is the input of the inverter and the first input of the third element And the second input of the differential detection of the halves of the block is the second input of the second and third elements And the output of the inverter connected to the first input of the second element, And the output of the second element And connected to the first input of the second e what about the element AND IS NOT and to the first input of the fourth element AND-NOT the output of the first element AND IS NOT connected to the input of the decrement counter the first half of the block, the input of the increment which is connected to the output of the second element AND IS NOT, the output of the third element AND IS NOT connected to the input of the decrement counter the second half of the block, the input of the increment which is connected to the output of the fourth element AND-NOT outputs of the counter of the first half of the unit is connected to the k - bit bus to the inputs of the first decoder, the outputs of the counter of the second half of the unit is connected to the k - bit bus to the inputs of the second decoder, the first inverted output of the first decoder connected to the first input of the first element AND IS NOT, the second output of the first decoder connected to the input set S trigger half block, the third inverted output of the first decoder is connected to a second input of the second element AND the first inverted output of the second decoder connected to the first input of the third element AND the second output of the second decoder is connected to the reset input R of the trigger half block, the third inverted output of the second decoder is connected to a second input of the fourth element AND-NOT inverted output of the trigger half of the block is the first output of the circuit detection halves of the block, direct trigger half of the block is, that stated, the device characterized by the presence of new elements: selector channel number 4, the trigger bit half block 10, schema discovery halves of the block 11 (11-23), the first item And 25, the counter unit 26 and the adder 27 with corresponding connections, and is not known from the prior art. Thus the invention conforms to the criterion "Novelty".

Analysis of the known technical solutions in the study and related fields allows us to conclude that the introduced functional blocks known. However, their introduction into a well-known device with the above links gives it new properties. The interaction of the introduced functional blocks allows use of the device receiving information from a channel in the multiplexed channels with asynchronous packet transmission. The introduction of the selector channel number 4 allows one broadcast channel to organize multiple virtual channels. Entered the detection scheme of the halves of the block 11 provides reliable fixation of the completion Assembly of block data from the asynchronously received from a channel packages. This scheme together with the adder 27 controls the addressing of the received packets in the buffer memory data blocks and provides room the purpose of the channel for professionals in this and related areas of technology is not obvious from the prior art. Thus the invention meets the criterion of "Inventive step".

The invention meets the criterion of "Industrial applicability" because it can be applied in various technical fields, for example in telecommunications systems, such as distribution systems computer information through television channels [4, 5].

The essence of the invention lies in the fact that the functioning of the device receiving information from a channel in the multiplexed channels with asynchronous packet transmission and to ensure error-correcting ability of the Assembly of blocks of data from these packets in the buffer memory data blocks used detection circuit halves of the block of data. The schema discovery halves of the data block based on the use of rooms packages. The location of the packet in the buffer memory of the data blocks is determined by the value of the batch number, the contents of the counter unit and the detection scheme of the halves of the block. Each of the received packets based on the value of the high order bit of the batch number refers to one of the two halves of the block of data. The detection scheme of the halves of the block of data in counting the number of received packets for each of the two halves of the block decides after receiving the previous half of the block. The completion of the reception of the second half of the block indicates the end of packet reception of a current block, and the detection scheme halves of the block increments the counter unit. Thus, the decision boundaries of the blocks is made with high reliability on the basis of the analysis of many rooms packages. Drop or insert individual packages do not lead to incorrect identification of the boundaries of data blocks and further spread of errors. Data in a separate loose and distorted packets can be recovered using error-correcting reed-Solomon codes.

In Fig. 1 shows a functional diagram of the device receiving information from a channel, and Fig. 2 is a functional circuit diagram of the detection of the halves of the block 11 of Fig. 3 is a timing chart of the circuit operation detection halves of the block 11 of Fig. 4 - one of the options of the format of the data block.

In the device description and the drawings, the following symbols are used:

RxD - serial data from the data selector 1 from the received information signal;

CLK1 is a clock signal serial data RxD received data selector 1;

CLK2 is a clock frequency synchro is Archi bit batch number;

NC - m1 - bit channel number;

ONE symptom of the error when decoding a channel number or a service;

D - input data item;

C - sync-item;

W - input recording resolution element;

-1 - log decrement counter;

+1 - log increase in the value of the counter;

R1, R2 inputs reset the character counter data package 24;

R is the reset input of trigger half block (TPB) 23;

S - input setup trigger half block (TPB) 23;

Q is a direct output of the flip-flop state;

Strbp signal recording bit older batch number NP(n-1) (bit half unit) trigger-bit half block 10;

Strcpy signal, the gate change counters 19, 20 half blocks SCPB and SCPB discovery schema half of block 11;

+CCNP signal, increasing the count of rooms packages CCNP 9 per unit;

Admission NP - signal, allowing the recording of the number of the received packet in the count rooms packages CCNP 9;

m - bit symbols of the data packet;

m1 - bit channel number;

n - bit number package number counter packets CCNP 9 and address of the packet in the data block;

n1 - bit address of the symbol data packet in the packet and the counter is 28, counter block number SCNB 26 and adder SM 27;

N=n+n1+n2 - bit full address of the buffer memory data blocks 28;

k - bit counters 19, 20 half block SCPB and SCPB, k=n-1;

+SCPB, +SCPB signals increasing values of the counters 19, 20 half block SCPB and SCPB per unit;

-SCPB, -SCPB signals decreasing values of the counters 19, 20 half block SCPB and SCPB per unit;

NG - the lower bound is the value of the counters 19, 20 half block SCPB and SCPB, which blocked their reduction;

VG is the upper bound is the value of the counters 19, 20 half block SCPB and SCPB, which blocked their increase;

THEN, the threshold is the value of the counters 19, 20 half block SCPB and SCPB, at which the decision about what reliably detected half of the data block and, therefore, the previous half of the data block is completely filled bags;

PB - the sign of the transition circuit detection halves of the block 11 in the first state, receiving a single value, when the number of received packets of the first half data block is greater than or equal to the value of the PORES.

PB-the sign of the transition circuit detection halves of the block 11 in the second state, receiving a single mn is ignal the installation of the sign PB;

UPB - setting signal characteristic PB;

TS is the symbol clock synchronization service;

BS - symbol-byte synchronization code to the beginning of service;

Ci,jthe symbol for Xjthe i - th code word reed-Solomon code;

RS - reed-Solomon code.

The pickup device information (Fig. 1) from the channel contains the data selector 1 selector the beginning of the package 2, the allocation of data characters 3, the selector channel number 4, the shift register 5, the buffer register 6, the correction pattern of the numbers of channels and packages 7, the control circuit record 8, the counter numbers of packages (SCNP) 9, the trigger bit half block (TBPB) 10, a detection circuit halves of the block (APB) 11 (11-23), the character counter data package (SCCDP) 24, the first item And 25, the counter block number (SCNB) 26, the adder (SM) 27, the buffer memory data blocks (BPBD) 28, a decoder error-correcting code (BPC) 29, the buffer data memory 30.

To the input of the data selector 1 (Fig. 1) is passed from the communication channel information signal. The data selector 1 output serial data RxD is connected to the input serial data D of the shift register 5, and the output clock frequency CLK1 data with the synchronization input of the shift register 5 and to the first input of the differential allocation of symbols darwini input selector start of packet 2. On the second inputs of the selector start of packet 2 is fed code to the beginning of the package. The output selector of the beginning of the package 2 is connected to the second input of the differential allocation of data characters 3. The output of the circuit selection data characters 3 is connected to the input of write W buffer register 6 and with a second input of the control circuit record 8. The outputs of buffer register 6 is connected to the m-bit data bus to the inputs of the correction patterns of the numbers of channels and packages 7 and the data inputs D of the buffer memory data blocks 28. The first inputs of the selector channel number 4 is connected to the m1 - bit bus channel number NC with fourth outputs the correction patterns of the numbers of channels and packages 7. On the second inputs of the selector channel number 4 is served m1 - bit channel number. The output selector channel number 4 is connected to the third input of the control circuit record 8, the first input of which is connected to the output characteristic of the decoding errors of the ML schema correction numbers of channels and packages 7. The fourth input of the control circuit record 8 is supplied to a clock frequency symbol processing data package CLK2. The first outputs of the correction patterns of the numbers of channels and packages 7 are connected to the n-bit bus package number NP(n-1:0) input data D number counter package 9, the second output NP(n-1) correction circuits room is a bit half block 10. The first output Strbp control circuit record 8 is connected to the c input synchronization With the trigger bit half block 10, the second output Strcpy control circuit record 8 is connected to the second input of the differential detection halves of the blocks 11, the third output +CCNP control circuit record 8 is connected to the input +1 count numbers of packages 9 and the first reset input R1 of the character counter data package 24, the fourth output Preamp control circuit record 8 is connected to the input of write W number counter packets 9 and the second reset input R2 of the character counter data packet 24, the fifth output +SCCDP control circuit record 8 is connected to the input +1 count characters of the data packet 24. Inverted output trigger bit half block 10 is connected to the first input of the first element And 25, a second input connected to the first output PB schema discovery halves of the block 11, the second output PB which is connected to the input +1 count the number of blocks 26. The output P of the first item And 25 is connected to the carry-in input P of the adder 27. The data inputs D of the decoder 29 are connected by a data bus with data outputs D buffer memory data blocks 28. Data outputs D of the decoder 29 are connected by a data bus with the data inputs D of the buffer data memory 30.

Full address of symbol data packet is emptied address A2 buffer memory data blocks 28 of the counter unit 26 through the adder 27 and define the start address of the current data block in the buffer memory data blocks 28. The starting address of the data block can be set in the counter unit 26 by the signal "Load". The address of the packet in the current block data is n - bit number, the next senior n2 discharges block number, the n - bit packet number is fed to the first address inputs A1 buffer memory data blocks 28 with the output number counter packages 29. Junior n1 bits of the full address is served on the third address inputs A3 buffer memory data blocks 28 of the character counter data packet 24 and determine the address of symbol data in the received packet. Thus, the full address contains N bits, with N=n2+n+n1. On the fourth address inputs A4 serves a full N - bit address from the decoder error-correcting code 29.

The detection scheme of the halves of the block 11 (Fig. 2) contains the inverter 12, the second and third elements 13, 14, first, second, third and fourth elements AND NOT 15, 16, 17, 18, the counter of the first half of the block (SCPB) 19, the counter of the second half of the block (SCPB) 20, the first and second decoders (DC) 21, 22 and the trigger half block (TPB) 23.

The first sign of NP(n-1) circuit detection halves of the block 11 (Fig. 2) is the input of the inverter 12 and the first input of the third element And 14. The second input Strcpy schema discovery halves of the block is the second element, And 13. The output of the second element And 13 is connected by a link +SCPB with the first input of the second element AND-NOT 16 and link-SCPB with a second input of the third element AND-NOT 17. The output of the third element And 14 is connected by a link-SCPB with the second input of the first element AND NOT 15 and communication +SCPB to the first input of the fourth element AND-NOT 18. The output of the first element AND-NOT 15 is connected to the input of -1 counter the first half of the block 19, input +1 which is connected to the output of the second element AND-NOT 16. The output of the third element AND-NOT 17 is connected to the input of -1 counter the second half of the unit 20, input +1 which is connected to the output of the fourth element AND-NOT 18. The output of the meter the first half of the block 19 is connected k - bit bus to the input of the first decoder 21. The output of the counter of the second half of the block 20 is connected k - bit bus with the input of the second decoder 22. The first inverted output NG of the first decoder 21 is connected to the first input of the first element AND NOT 15, the second output of the PORES of the first decoder 21 is connected by a link UPS with the input set S trigger half block 23, the third inverted output VG of the first decoder 21 is connected to a second input of the second element AND-NOT 16. The first inverted output NG second decoder 22 is connected to the first input of the third element AND-NOT 17, the second output THEN the WTO the second decoder 22 is connected to a second input of the fourth element AND-NOT 18. Inverted output of the trigger half block 23 is the first output PB discovery schema half of block 11, direct trigger half block 23 is a second output PB schema discovery halves of the block 11.

The device operates as follows.

The device receiving information from the channel works with blocks of data having the format shown in Fig. 4. The data block consists of 31 package with numbers from 1 to 31. Each package contains two bytes of clock synchronization TS, the symbol-byte synchronization BS code (start of packet); the channel number NC (3 bits); the number NP, (5 bits); forty characters of the data package.

The channel number and number package code protected Hamming (8,4), correcting and detecting one of two erroneous bits. The use of different numbers of channels and different BS types allows you to organize multiple virtual channels in a single television channel. The format for data transmission involves the use for protection against errors in the channel error correcting reed-Solomon codes (RS-codes) defined over the Galois field GF(256). The symbol size for this field is equal to the byte. The data block contains 40 code words, each of which contains 31 characters. On aswego). Columns 6: 45 a.m contain code words RS-code. Deep interleaving symbols of the code words in the data block allows you to effectively fix how long the packet errors in a television line, and the loss of entire packets of data due to distortion of the packet header.

High-correcting ability of the reed-Solomon code can be implemented provided that despite the availability of depositions of some of the packets and the reception of false packets, symbols from packages with unerring headers will be collected in a code word without change, and the boundaries between the code words will be correctly identified. You must implement a robust Assembly of data blocks from the received packets.

Introduction in the device information reception selector channel number 4 allows you to work with multiplexed (virtual) channels, which have different numbers of channels. Additional multiplexing of channels provides a selector start of the package 2, which can be used various codes beginning of the package. Multiplexing channels provides for the organization of multiple virtual channels in a single broadcast channel. The time interval between tsetse asynchronously. In this case, to ensure the Assembly of the block of data it is impossible to use the methods of time synchronization (frame synchronization). The natural solution to this problem is the use of cyclic rooms packages. Immunity Assembly of data blocks to be provided in two stages. In the first phase errors are corrected in the numbers of channels and packages. Correcting errors in the device receiving information from a channel implements a simple combinational logic circuit correction numbers of channels and packages 7. In the second stage uses a detection circuit halves of the block 11, the trigger bit half block 10, the first item And 25, the counter unit 26, an adder 27, and the counter numbers of the packages 9. The interaction of the listed blocks is based on the following principles.

1) Each packet data block belongs to one of the two halves of the block of data. The package refers to the first half of the data block, if the most significant bit of the number of the received packet NP(n-1) equal to zero. Otherwise, the packet belongs to the second half of the block.

2) Adopted without error packet number uniquely identifies the address of the packet to the current data block in the buffer memory data blocks 28. Undetected error in the number s of real numbers will be correctly placed in the buffer memory data blocks 28 and their characters in code words RS code will not be indented.

3) In case of detection of the correction pattern of the numbers of channels and packages 7 fatal errors in the batch number NP(n-1:0) it is assumed that a packet is received, the number greater by one than the number of the previously received packet.

4) On the basis of the separation of packets belonging to one of the two halves of the block of data for schema discovery halves of the block 11 defines two States. In the first condition detection circuit halves of the block 11 moves when the device is receiving information from the channel took a certain number of packets belonging to the first half of the data block. When it is decided that the second half of the previous data block is completely filled with packages. The second condition detection circuit halves of the block 11 moves when the device is receiving information from the channel took a certain number of packets belonging to the second half of the data block. When it is decided that the first half of the current data block is completely filled with packages.

5) If the detection scheme of the halves of the block 11 is in the second state, and the input device receiving information from the channel the packet is coming in the first half of the block, it is assumed that this packet from the first half of the disorder receiving information from the channel the packet is coming in the second half of the data block, the entry is in the scope of the current data block.

6) the Address of the data block in the buffer memory data blocks 28 is incremented whenever a transition schema discovery halves of the block 11 in the first state, which means that the previous data block is completely filled with packages.

The input information signal, taken from the communication channel to the input of the data selector 1 (Fig. 1), which makes the selection of the serial data signal RxD and the clock frequency CLK1 these data. The serial output of the data selector 1 are received on the serial data input D of the shift register 5, in which the front of the clock CLKI pulse supplied from the data selector 1 input synchronization, is a shift in serial data. Thus, the shift register 5 corresponding to the bit performs serial-to-parallel conversion of the received data. Parallel m - bit data outputs of the shift register 5 are received at the data inputs D of the buffer register 6 and the input selector of the beginning of the package 2. The selector start package 2 compares the data on the outputs of the shift register 6 with the specified code to the beginning of the package. Equality means that, ctstate to the input device. Therefore, in the case of a tie, the selector start package 2 generates a signal that triggers the allocation of data characters 3.

The allocation of data characters 3 after starting from the selector start package 2 starts counting the number of received bits symbols data package, using a clock frequency CLK1 serial data RxD from the output of the data selector 1. On the basis of this calculation is the selection of all m-bit data symbols of the packet, i.e., control of series-parallel conversion is performed on the shift register 5. After admission to the shift register 5 of each m-bit symbol data packet selection scheme symbols 3 gives the data strobe write enable input write W buffer register 6, to store the next symbol data package. The same signal each time the selection of the next character data package starts the control circuit record 8.The symbol data packet stored in the buffer register 6, is fed to the inputs of the correction patterns of the numbers of channels and packages 7. After recording in the buffer register 6 symbol data packet corresponding to the channel number, the correction pattern of the numbers of channels and packages 7 decodes, selects and outputs m1 - bit number is the number of channel valid receive bits of the next character data package to the moment of writing this character in the buffer register 6. After recording in the buffer register 6 symbol data packet corresponding to the packet number, the correction pattern of the numbers of channels and packages 7 decodes, selects and outputs the n - bit packet number NP(n-1:0), senior level package number NP(n-1) and the sign of the decoding errors of ML, indicating that the presence or absence of fatal errors in the batch number, valid for receiving bits of the next character data package to the moment of writing this character in the buffer register 6. The channel number NC outputs of the correction patterns of the numbers of channels and packages 7 arrives at the inputs of the selector channel number 4. The selector channel number 4 compares the channel number to which the received packet with the specified source channel number. If they match the selector channel number 4 generates a signal, which is a sign of an incoming packet to the specified in the selector channel number channel 4. This signal is fed to the input of the control circuit record 8.

The first start signal from the circuit selection data characters 3 activates the control machine control circuitry record 8. is that in a certain state. Each state of the machine corresponds to the reception buffer register 6 and the handling of a particular symbol data package.

The first state (the state of the processing channel number) of the control machine control circuitry record 8 after the first run from the scheme of allocation of data characters 3 corresponds to the reception buffer register 6 and the processing of the character data package containing the channel number. In this state, the control circuit record 8 analyzes the signal supplies the received packet to the specified channel from the selector channel numbers 4 and the sign of the error decoding OD generated by the correction pattern of the numbers of channels and packages 7.

The analysis of the control scheme record 8 generates a sign permit recording of data symbols of the packet in the buffer memory data blocks 28. The sign is formed in the status word, which is in the control circuit record 8.

Write the symbols of the data packet received by the unit receiving the information from the channel into the buffer memory data blocks 28 is carried out in two cases:

if the received packet belongs to the set in the selector channel number channel 4 and the correction pattern of the numbers of channels and packages 7 not found solving the error in the channel and formed error signal decoding OD channel number.

In the case of the prohibition of entry of data characters received package management scheme record 8 does not generate any signals that control the addressing and writing the packet into the buffer memory data blocks 28.

Following the state of the control machine control circuitry record 8 (the state of processing of the batch number) after the second start signal from the circuit selection data characters 3 corresponds to the reception buffer register 6 and the processing of the character data package containing the number of the received packet. In this state, the control circuit record 8 analyzes the sign of the error decoding OD correction circuits numbers of channels and packages 7, corresponding to the presence or absence of fatal errors in the batch number. In the case of recording resolution character data of the received packet on the basis of this characteristic generates signals that control the addressing of the received packet in the buffer memory data blocks 28. These include: Strbp, Strcpy, +CCNP, Preamp.

After decoding the batch number NP(n-1:0) schema correction numbers of channels and packages, the most significant bit of the number of the received packet NP(n-1) is stored in the trigger bit half block (TBPB) 10. Recording is performed on a signal Strbp that tosignal Preamp is recorded in the count room packages 9. The count of the numbers of packets 9 is a relative address of an incoming packet in the current data block. The start address of the current data block is contained in the counter unit 26.

In case of detection of the correction pattern of the numbers of channels and packages 7 fatal errors in the batch number NP(n-1:0) it is assumed that a packet is received, the number greater by one than the number of the previously received packet. When this control scheme record 8 in a state of processing of the batch number on the basis of the sign of the error decoding OD generates a control signal +CCNP increasing the content of the counter numbers of the packages 9 per unit.

When the control circuit record to be processed, batch number, based on the state diagram of the detection of the halves of the block 11 and the number of the received packet is calculated address in the buffer memory data blocks 28.

In the first circuit state detection halves of the block 11, the trigger half block 23 is installed in the unit, sign PB on the second output circuit detection halves of the block 11 is equal to one, and the sign PB on the first circuit output detection halves of the block 11 is equal to zero.

In the second circuit state detection halves of the block 11 trigger providerfor the circuit output detection halves of the block 11 is equal to one.

The detection scheme of the halves of the block 11 contains two counters: the counter of the first half of the block 19 and the counter second half of the block 20. These counters count the number of received packets of each half of the received data block. Receipt of a packet belonging to one half of the data block, increments the counter value corresponding to half of the block that contains the number of received packets that half of the data block, and decrements a counter value of the other half of the block.

Management counters halves of the blocks 19, 20 are carried out using the element 12 and the second and third elements And 13, 14. The listed items based on the value of the high bit numbers of the received packet NP(n-1) control signal Strcpy form appropriate control actions-SCPB, +SCPB, -SCPB, +SCPB. The control signal Strcpy is formed by the control circuit record 8 in a state of processing of the batch number in the case of a write-enable packet in the buffer memory data blocks 28.

Control actions-SCPB, +SCPB, -SCPB, +SCPB arrive at the inputs of the first, second, third and fourth elements, AND-HE 15, 16, 17 and 18. These elements together with the decoders 21, 22 implement to block the values NG. The values of VG and NG are the decoders 21, 22. The value of VG is selected depending on the number of packets in the data block, and NG is assumed to be zero.

When the number of received packets belonging to the first half data block certain threshold THEN, the detection circuit halves of the unit 11 enters the first state. The transition to the first state indicates that the second half of the previous block of data taken everything belonging to her, packages, taking into account the possible insertions and deposition packages.

When the number of received packets belonging to the second half of the data block certain threshold THEN, the detection circuit halves of the block 11 moves into its second state. The transition to the second state indicates that in the first half of the current data block taken all belonging to her, packages, taking into account the possible insertions and deposition packages.

The threshold value THEN the number of received packets of the first half data block to counter the first half of the unit 19 sets the decoder 21. When the number of received packets of the first half data block at the output of the counter of the first half of the block 19 values THEN the decoder 21 generates a signal UPB. This signal condition is the condition.

The threshold value THEN the number of received packets of the second half of the data block counter of the second half of the unit 20 sets the decoder 22. When the number of received packets of the second half of the data block at the output of the counter of the first half of the block 20 values THEN the decoder 22 generates a signal UPB. This signal resets the trigger half block 23 to zero. When this detection circuit halves of the block 11 moves into its second state.

If the detection scheme of the halves of the block 11 is in the second state (PB= 0, PB=1), and the input device receiving information from the channel the packet is coming in the first half of the block, it is assumed that this packet from the first half of the next block of data. Using the adder 27 calculates the address in the buffer memory data blocks 28 and writes the data packet in accordance with the calculated address. The address is calculated based on the value of the counter unit 26, which is a basic part of a complete address for the buffer memory data blocks 28 and addresses of the beginning of the data blocks in memory. Using the adder 27 to the value of the counter unit 26, which is fed to the inputs of A first addend adder 27, temporarily added to the unit applied to the input of the and sign PB output circuit detection halves of the blocks 11 and the value of the inverted output trigger bit half-block is equal to one, that corresponds to the reception of the packet belonging to the first half of the next block of data. If the detection scheme of the halves of the block 11 is in the first state (PB=1, PB= 0), and the input device receiving information from the channel the packet is coming in the second half of the data block, the recording is carried out in the scope of the current data block. When this unit on the carry-in input P of the adder 27 to the first item And 25 is not formed, and temporarily increasing the address of the data block by using the adder 27 is not happening.

The address of the data block in the buffer memory data blocks 28 is incremented whenever a transition schema discovery halves of the block 11 in the first state, which means that the previous data block is completely filled with packages, by increasing the value of the counter unit 26 unit signal PB from discovery schema halves of the block 11. The signal PB is formed at the moment of transition schema discovery halves of the block 11 in the first state.

From a condition of processing the batch number control machine control circuitry record 8 on the next start signal from the circuit selection data characters 3 goes into the recording of the received data symbols of the packet in the buffer memory blocks Yes the x packet received. Being able to write character data package management scheme record 8 in the case of the permission record forms for each received symbol data packet control signals and addressing signals recording. The control signal addressing data symbols of the packet is the signal +SCCDP increasing the address of symbol data in the received packet by one. The recording signals of the symbol data packet in memory depend on the choice of buffer memory data blocks 28 and in Fig. 1 is not shown. To generate all control signals of the control circuit record 8 uses a clock frequency CLK2 received at its input. Thus, the recording and processing of data symbols of the packet in the buffer memory data block 28 attached to a clock frequency CLK2, which is selected depending on the frequency of CLKI, time recording and organization of modes of access to the buffer memory data blocks 28.After receiving the last character of the data package management scheme record 8 enters the idle state of the first start signal from the circuit selection data characters 3, which corresponds to the allocation of data symbols with the channel number of the next packet.

After receiving all characters of the data packet selection scheme data characters 3 vozvraschetsya, count the number of received bits symbols data package. After the end of the service device receiving information from the channel returns to initial state waiting to start the next batch.

Correction of errors in blocks of data using RS codes is performed after the complete reception of the write data block in the buffer memory data blocks 28 decoder error-correcting code 29. Decoder error-correcting code 29, reads the data block from the buffer memory data blocks 28 and after correcting errors in it writes the data block in the buffer memory 30.

In Fig. 3 shows timing diagrams of the circuit operation detection halves of the blocks 11. As the unit of time to the timing charts of the selected reception time of one packet. To the timing charts NP corresponds to the number of packet received, SCPB the counter value of the first half of the block, SCPB the counter value of the second half of the block, UPB is setting signal of the first state, i.e., the setting signal trigger half block 23, UPB is setting signal of the second state, i.e., the reset signal trigger half block 23. As a threshold THEN the number of packets selected value of 8, as the upper bound of 12.

In the packages. In this case, the transition into a first state in which the previous data block is completely filled, occurs when you receive a package with the number 7 (the eighth relating to the first half of the data block when the value of the output counter of the first half of the block 19 SCPB equal to 8) on the leading edge of the signal UPB. When the packet of the first half data block counter value of the first half of the block 19 SCPB incremented to a predetermined upper bound VG equal to 12, and is fixed to the arrival of the first packet belonging to the second half of the data block. With the arrival of each packet of the second half of the data block is decrement the counter of the first half data block 19 to zero. When reaching in the process of reducing the value of the counter of the first half data block 19 with a value of 7 is removed, the control signal UPB holding a detection scheme halves of the blocks 11 in the first state.

The transition into the second state in which the first half of the current data block is full, occurs when you receive a package with number 23 (eighth belonging to the second half of the data block when the value of the output counter of the second half of the block 20 With the x counter value of the second half of the block 20 SCPB incremented to a predetermined upper bound VG, equal to 12, and is fixed to the arrival of the first packet belonging to the first half of the data block. With the arrival of each packet of the first half data block is the decrement counter the second half of the data block 20 to zero. When reaching in the process of reducing the value of the counter of the second half of the data block 20 with a value of 7 is removed, the control signal UPB holding a detection scheme halves of the blocks 11 in the second state.

The bottom chart shows the operation of the circuit of the detection halves of the blocks 11 in the presence of precipitation packages. In this case, the transitions between States occur with some delay due to drop packets with numbers 1, 3, 5, 9, 11, 15, 17, 21, 23, 25, 27, 29. The transition into a first state in which the previous data block is completely filled, occurs when you receive a package with the number 12. The transition to the second state occurs when you receive a package with number 22.

Thus, despite the loss of packets, the detection scheme of the halves of the block 11 with high reliability determines the moment of complete filling packages of the previous data block. The delay determination does not exceed the transmission time of one half of the data block. Detection circuit halves blooma information from the channel.

The proposed device can be easily implemented on commercially available elements. Consider an example implementation of a device receiving information from a channel, working with is shown in Fig. 4 the format of the data block. The data selector 1 is implemented on the chip SAA5231 or its domestic analogue CRHA with control circuits. The selector is the beginning of the package 2 is implemented in two chips CSP and chip CLI, the selector channel number 4 - on-a-chip CSP, the shift register 5 - on-chip CMIR, buffer register 6 - on-a-chip CIR, the correction pattern of the numbers of channels and packages 7 - on-a-chip CRRT, the count numbers of the packages 9 - chip CIE, K555TM2 and CLP, the trigger bit half block on the chip K555TM2, the character counter data package 24 - the two chips CIE, the first item And 25 - on-a-chip CLI, counter block number 26 on the chip CIE, the adder 27 in chips KIM and CLP. The allocation of data characters is implemented in two chips CIE, two chips CSP, chip K555TM2, KTV, CAR, CLP, CLE, CLE and CLN. The control circuit of the recording is implemented in two chips K555TM2, chip CIE, KID, KTM, CLA, CLS, CL.

Scheme obne, the decoders 21, 22 on the chip CAP, KLN, CLA and KID, the trigger half block 23 on the chip K555TM2, elements, AND-NOT - on-a-chip CLA, elements, And 13 and 14 on the chip CLI, the item is NOT 12 - on-a-chip KLN.

Decoder error-correcting code 29 can be both hardware and software, for example, if the device information is received from the channel is used at the PC. In the latter case, the buffer memory data blocks 28 and buffer the data memory 30 can represent a different area of the system memory of the PC to which access by the device receiving the information and the decoder error-correcting code 29 is carried out on the system bus of the PC in accordance with the protocols of this system bus.

Alternative software implementation of the decoder is its implementation in the form of a microprocessor system [6] hardware accelerator [7]. At the same time as the memory you can use chips CRRU.

The invention compared with the prototype has the advantage that it can work with multiplexed channels with asynchronous transmission of information packets. When the reception information is error-correcting stavki and drop asynchronously transmitted packets. This prevents the propagation of errors in the data block.

Sources of information:

1. Patent EP 0162612 A2 (EUROPEAN PATENT APPLICATION). MCI H 04 N 7/087. Receiver for a character broadcasting system. / Shibasaki Takeshi (JP) - declared 26.04.85; priority 86826/84 JP from 27.04.84; publ. 27.11.85, bull. 85/48.

2. Patent 5185740 USA. MKI 5 H 04 J 3/06, NCI 370-106. Information transmitting device. / Yoshikazu Kurose, Shinji Aoki, Hideto Suzuki (JP) - declared 23.07.90, N 555769; priority 1-194769 from 26.07.89; publ. 9.02.93.

3. Patent WO 84/03987 (PCT). MCI G 11 7/00, G 11 IN 5/09. Apparatus for recording and reprodusing optical data. Declared / 30.03.84, PCT /JP84/ 00156; publ. 11.10.84.

4. Petrov, C. C., A. Dodonov, the distribution System of the computer information "ALL-ALL" // E simulation. - 1991, N 1.- S. 14-17. brown.

5. VBI: data transmission over the broadcast channels / Petrusevski C. // the Computer press. - 1998 - N 3, S. 98-100.- eng.

6. Egorov S. I. About software - hardware implementation of the decoder reed - Solomon code for error small-sized optical on kapitala / Kursk. polytechn. in-so - Kursk, 1990. 39 S.: ill., table. Bibliogr. 26 titles. - Dept. in INFORMPRIBOR N 4898 - PR 90.

7 . C. 1656689 the USSR, MCI N 03 M 13/00, 13/02. Device coding and computing syndromes of error-correcting codes for correcting errors in the external memory of a computer / S. Rojstva receiving information from a channel, contains the data selector, the selector start of the service, the allocation of data characters, a shift register, a buffer register, the correction pattern of the numbers of channels and packages, the control circuit record, the count numbers of the packages, the character count package data buffer memory data blocks, the error-correcting decoder course, the buffer memory data, and the input of the data selector connected to the bus of the information signal, the output serial data of the data selector is connected to the input serial data of the shift register, the output clock frequency data of the data selector is connected to the synchronization input of the shift register and the first input of the differential allocation of data characters, the outputs of the shift register are connected to m - bit data bus to the input data buffer register and the first input of the selector start of the service, the second inputs of the selector start of the package connected to the bus code to the beginning of the packet, the output selector the beginning of the package is connected to the second input of the differential allocation of data characters, the output of the circuit selection data symbols are connected to the input write buffer register and a second input of the control circuit record, the fourth input of which is connected to the bus clock frequency symbol processing a data packet, outputs b is the input data buffer memory data blocks, the first input of the control circuit record connected with the output characteristic of the decoding error correction circuits numbers of channels and packages, the first outputs of the correction patterns of the numbers of channels and packages are connected to the n - bit bus of service with the input data number counter of packets, the third output of the control circuit record connected with a counter input number counter of packets with a first reset input of the counter of the symbols of the data packet, the fourth circuit output control record is connected to the input of the record number counter of packets and the second reset input of the counter of the symbols of the data packet, the fifth circuit output control record is connected to the counting input of the counter of the symbols of the data packet, the outputs of the counter numbers of the packets n - bit address bus package is connected with the first input address buffer memory data blocks, the outputs of the character counter data package connected n1 - bit address bus of the symbol data packet with a third input of the address buffer memory data blocks, the fourth input address buffer memory data blocks are connected to the N - bit address bus with the first outputs of the address decoder error-correcting code, the data inputs of which are connected by a data bus to the outputs of the data buffer memory blocks Dunn is the R, address inputs which are connected to the address bus with the second outputs of the address decoder error-correcting code, characterized in that the device entered the selector channel number, the trigger bit half of the data block detection circuit halves of the data block, the first element And the counter number of the data block and the adder, the input selector channel number connected to the m1 - bit bus channel number with the fourth outputs of the correction patterns of the numbers of channels and packages, the second inputs of the selector channel number connected to the m1 - bit bus code channel number, the output selector channel number connected to the third input of the control circuit record, the second output of the correction circuits numbers of channels and packages connected to the first input of the differential detection of the halves of the block of data and input data trigger bit half block of data, the first output of the control circuit record connected to the synchronization input of the trigger bit half block of data, the second output of the control circuit record connected with the second input of the differential detection halves of the data block, inverted output trigger bit half data block connected to the first input of the first element And a second input connected to the first circuit output detection halves of the data block, the WTO, with the carry-in input of the adder, inputs counter data block number data is connected to an n2-bit bus start address of the data blocks in the buffer memory block data entry entry counter number of data unit connected to the bus "Download", the outputs of the counter block number data connected n2 - bit bus with the first data inputs of the adder, the second input data which is connected to an n2 - bit bus logic zero, the outputs of the adder are connected to the n2 - bit address bus data block with the second input of the address buffer memory data blocks, and the detection scheme halves the data block contains the inverter, the second and third elements, the first, the second, third and fourth elements AND IS NOT counter the first half of the data block counter of the second half of the data block, the first and second decoders and the trigger half of the data block, the first input of the differential detection halves of the data block is the input of the inverter and the first input of the third element And the second input of the differential detection of the halves of the block of data is the second input of the second and third elements And the output of the inverter connected to the first input of the second element And the output of the second element And is connected to the first input of the second element AND with a second input of the third element AND IS NOT, the third output is the first element AND IS NOT connected to the input of the decrement counter the first half of the data block, input increment which is connected to the output of the second element AND IS NOT, the output of the third element AND IS NOT connected to the input of the decrement counter the second half of the data block, the input of the increment which is connected to the output of the fourth element AND-NOT outputs of the counter of the first half data block connected k - bit bus to the inputs of the first decoder, the outputs of the counter of the second half data block connected k - bit bus to the inputs of the second decoder, the first inverted output of the first decoder connected to the first input of the first element AND IS NOT, the second output of the first decoder connected to the input set S trigger half of the data block, the third inverted output of the first decoder is connected to a second input of the second element AND the first inverted output of the second decoder connected to the first input of the third element AND the second output of the second decoder is connected to the reset input R of the trigger half of the data block, the third inverted output of the second decoder is connected to a second input of the fourth element AND-NOT inverted output of the trigger half of the data block is the first output of the circuit detection halves of the block of data, direct trigger, half of the data block is the second output of the circuit found

 

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