The frequency synthesizer

 

(57) Abstract:

The invention relates to electrical engineering and can be used in transmitting and receiving devices. The objective of the invention is the simplification of the device and improving the accuracy of the output frequency. The frequency synthesizer includes serially connected first register and a multiplier, connected in series reference oscillator and synchronization unit, a first multiplexer, a memory unit, connected in series, a second register, a digital-analog Converter and low pass filter, N second multiplexers, N first adders, N second adders and N third registers. Due to the correction capacity of the adders in each cycle of its operation, the accuracy of the output frequency of the frequency synthesizer even when nonmultiple values of the capacity of the adder and the frequency of the reference signal is determined by the accuracy of the reference oscillator frequency. 2 Il.

The invention relates to electrical engineering and can be used in transmitting and receiving devices. Known frequency synthesizer containing a reference oscillator, a cumulative adder, a delay element, a multiplexer, two adder codes, three frequency register, the multiplier codes, change the false and does not provide sufficient accuracy output frequency.

Known frequency synthesizers, in order to improve accuracy using different circuit designs [2].

Used to improve the accuracy of the circuitry or complex, for instance, decimal adder, where due to the series connection of binary adders reduces the performance of the scheme, or not at all can ensure the accuracy not worse than the accuracy of the reference oscillator.

Known digital frequency synthesizer, comprising a generator of clock pulses, a frequency divider, a block code generation frequency driver control code, two of the drive phase, the multiplier codes, unit totals, pulse distributor, three memory register, the unit's permanent memory, switch, DACS, and a lowpass filter [3].

This synthesizer does not allow to obtain the exact value of the frequency of the output signal.

Known synthesizer signals with a predetermined law of variation of the phase containing two frequency divider, the block of code generation phase and frequency, N-1 combinational adder, N converters code N additional memory registers, delay element, a switch, a memory register, DAC, low pass filter, the block of code generation phase, the synchronizer is ignal.

The objective of the invention is the simplification of the device and improving the accuracy of the output frequency.

To do this, in the frequency synthesizer containing serially connected first register and a multiplier, connected in series reference oscillator and synchronization unit, a first multiplexer, a memory unit, connected in series, a second register, a digital-analog Converter and low pass filter, is entered N of second multiplexers, N first adders, N second adders and N third registers, and the first inputs of the N first adders connected to respective outputs of the multiplier, the second inputs of the N first adders are interconnected with the output of the N-th of the third register, the output of each of the N first adders connected to the first input of the corresponding second adder, the output of the transfer of each of the N first adders connected with the control input of the corresponding second multiplexer, the N outputs of the second multiplexer is connected to the second inputs of the respective second adders, the output of each of which is connected to the third input of the corresponding register, the output of each of the N third registers connected to the respective input of the first multiplexer, the output of the first a mul is and synchronization connected with a clock input N third register, control inputs of the first multiplexer and a clock input of the second register, with the first N inputs of the second multiplexer are connected and are the input signal is "logic 0", the second inputs of the N second multiplexers are interconnected and are input to which is fed the extension code.

The proposed solution meets the criteria of the invention "novelty" because it differs from the prototype by the presence of new functionalities and new relationships between the elements.

In Fig. 1 shows a block electrical diagram of the device of Fig. 2 is a timing diagram of operation of the device.

The synthesizer includes serially connected first register 3(WG1) and the multiplier 2 (INTELLIGENCE), connected in series reference oscillator 1 (OG), block 4 synchronization (BS), the first multiplexer 5 (MH), block 6 memory (BP), the second register 7 (WG 2), d / a Converter 8 (DAC) and the filter 9 low pass (LPF), N second multiplexers 10-1, 10-2,...10-N (MH), N first adders 11-1, 11-2, 11...-N (CM1), N second adders 12-1, 12-2,. . . 12-N (CM2), and N third registers 13-1, 13-2,...13-N (WG3), and the first inputs of the N first adders connected to respective outputs of the multiplier, the output of the adders is connected to the first input of the corresponding second adder, the output of the transfer of each of the N first adders connected with the control input of the corresponding second multiplexer, the N outputs of the second multiplexer is connected with the second inputs of the respective second adders, the output of each of which is connected to the third input of the corresponding register, the output of each of the N third registers connected to the respective input of the first multiplexer, the output of the first multiplexer is connected to the input of the memory block, the output of the memory block is connected to the input of the second register, the outputs of the synchronization unit is connected to clock inputs of the N third registers, control inputs of the first multiplexer and a clock input of the second register, while the first N inputs of the second multiplexer are connected and are the input signal is "logic 0", the second inputs of the N second multiplexers are interconnected and are input to which is fed the extension code.

The device operates as follows.

As you know, in direct digital synthesizers frequency signal of a given frequency by calculating the clock in the time code linearly increasing phase transformation code phase code in the amplitude of the sine wave is considered as the digital synthesizer is

< / BR>
where Faboutthe frequency of the reference signal,

A code frequency,

P - division ratio (determined by the capacity of the adder).

To explain the operation of the device will present a diagram of a device consisting of parallel paths summation - N blocks forming the sum (PLS), each of which consists of the second multiplexer 10-1, 10-2,...10-N and the series-connected first adder 11-1, 11-2,...11-N, the second adder 12-1, 12-2, ...12-N and the third register 13-1, 13-2,...13-n

On the second inputs of the first adders 11-1, 11-2,...11-N for all N PLS code comes from the output of the third register 13-N of the N-th PLS, and the first inputs of the first adders 11-1, 11-2,...11-N for all N PLS multiplier 2 enter codes, multiple code A (A, 2A, 3A,...). In each of facility capacity first adder 11-1, 11-2,...11-N is P - division factor. N-th PLS code from the output of the third register 13-N which goes directly to the second input of the first adders 11-1, 11-2,...11-N for all N PLS, performs the function of accumulating adder, working with step NA.

Summation occurs simultaneously on all PLS, they differ only code coming from the multiplier 2 to the first inputs of the first adders 11-1, 11-2, 11... - N. At the end of the aggregation process is what tscheligi code phase and amount consistent set of current phases of the output signal of the device, and the code stored in the third register 13-N of the N-th PLS, and also the source code for the next cycle summation.

Let us return to the formula (1).

The output frequency of the standard high-stability oscillators, usually a multiple of 1 MHz, the capacitance of the adder is equal to powers of 2.

If natrataste numbers in the numerator and denominator of the real value of the frequency at the output of the device is obtained by dividing these numbers do not accurately corresponds to the desired frequency value, because the result of dividing the number is not an integer.

Imagine the capacity of the accumulating adder as the sum of two numbers - one of them is a multiple of the code of the desired frequency A, and the other adds this number to the value, which is a power of 2:

N = A + D, (2)

where K is an integer,

Dr. incremental code.

To obtain the value of output frequency accuracy of the reference oscillator is proposed to adjust the capacity of the adders.

In each of the N PLS if there is no signal to transfer the output of the first adder 11-1, 11-2,...11-N to the second input of the respective second adder 12-1, 12-2,..,12-N through the corresponding second multiplexer 10-1, 10-2,... 10-N signal "logic 0" and the code output corresponding vtoi any one of the first adders 11-1, 11-2,...11-N, which may occur after the next write code to third registers 13-1, 13-2,...13-N and, consequently, change the code in the second inputs of the first adders 11-1, 11-2,...11-N, the output transfer corresponding to the first adder 11-1, 11-2,...11-N receive the signal, which is driving the respective second multiplexer 10-1, 10-2,...10-N connects to the second input of the respective second adder 12-1, 12-2, 12...-N incremental code D, and to the third input of the corresponding register 13-1, 13-2,...13-N for a new entry arrives code equal to the amount of the balance on the output of each of the crowded first adders 11-1, 11-2,...11-N of the next cycle and incremental code D. Upon completion of the tabulation process the received sum value is written to the corresponding third register 13-1, 13-2,...13-N, the signal transfer output of the transfer of each of the crowded first adders 11-1, 11-2, 11...-N vanishes and the corresponding second multiplexer 10-1, 10-2,...10-N again connects to the second input of the respective second adder 12-1, 12-2, 12...-N signal is "logic 0". Signals overflow of the first adders 11-1, 11-2,... 11-N in each of the FCC are formed independently from each other.

The total required number of concurrently enabled the FCC determined sobstyl are formed on the basis of typical schemes multiplication or using additional adders. So codes 2A, 4A, 8A,... are obtained by a simple shift of the source code And at 1, 2, 3,... discharge, and codes FOR, 5A, 6A,... is obtained by summation of (2A + A), (4A + A), (4A + 2A),... on several additional adders (can be part of a multiplier circuit, not shown).

Unit 4 synchronization, the input of which the signal of the reference oscillator 3 produces the clock signal for writing in the second register 7 and the N third registers 13-1, 13-2,...13-N, and the control signals to the first multiplexer 5, thereby ensuring high accuracy of generated signals (not worse than the accuracy of the reference oscillator). The output signals of block 4 synchronization shown in Fig. 2B - Fig. 2ZH, Fig. 2A - input signals from the reference oscillator 3. The signals shown in Fig. 2B, are used to write the codes in the N third registers 13-1, 13-2,...13-N for all N FCC shifted in time relative to them, and distributed by the number of FCS signals for managing the input of the first multiplexer 5 (Fig. 2G - Fig. 2ZH) shifted relative to the control signals of the first multiplexer 5, the signals are sent to the clock input of the second register 7 (Fig. 2B). In Fig. 2H shows the code values of the samples of a sine function for the case N = 4, prodautsa directly to the memory block 6, executed on programmable permanent memory (ROM), and determine the sample code in the amplitude of the sinusoid of unit 6 to the memory. In ROM recorded the period of the sinusoid, with a number of samples equal to the capacity adder (R-D). The remainder of the ROM is not programmed and is not used. Each code at the output of the first multiplexer 5 corresponds to the exact value of the envelope of the sinusoid.

Code amplitude arrives at the inputs of d / a Converter 8, the output of which is obtained multi-level step voltage, from which by means of the filter 9 of the lower frequencies is allocated to the signal generated by frequency.

Compare the proposed device with the famous.

In the known device [1] is used, the adjustment capacity of the accumulating adder by introducing incremental code, but as a result of further transformations, you receive an error, leading to inaccuracy of the output signal.

Explain said.

Consider the part of the circuit of the known device [1] (the adder 8, the register 9, the multiplier 10, the inverter 11 codes, DAC LPF 12 and 13). Conversion codes generated at the output of the accumulating adder 2, the codes mnogobrojne the tel 10) additional number L, that is because the Converter 11 codes written code values for each of P = 2nvalues of the sine wave, and the output is accumulating adder 2 codes appear, representing the proportion of the period of the sinusoid described by the value (P-B).

The value of L = P/(P-C) (in the description of the known device [1] in this formula is a misprint) is the scale factor, and in General not an integer. But the code on the output of the accumulating adder 2 is an integer, address sampling Converter 11 codes also an integer, so in each case, the result of the multiplication must be rounded to an integer, discarding the fractional part, which will inevitably lead to errors in the choice of the instantaneous values of the amplitude of the output signal, and hence to a deterioration of the spectral characteristics of the output signal, reducing its accuracy.

Explain the above specific example.

For example, it is necessary to develop a frequency synthesizer with a grid spacing of frequency 5 Hz, the reference oscillator frequency of 1.25 MHz, the frequency of the output signal should be not worse than the accuracy of the reference oscillator. The maximum required capacity of the accumulating adder is determined when A = 1, fo. = 5 Hz and bude is left of conditions necessary vosemnadcatiletnij accumulating adder. Incremental code B equal 262144-250000=12144. Now for the known device [1] determine the value of the number L = 262144/(262144-250000)=1,048576. The proposed calculation confirmed the inaccuracy of the procedure of multiplication in the known device [1].

Consider the known device [3] and [4]. Schemes these devices are quite similar - they use two groups of adders - accumulating adder for code generation frequency, combinational adder for forming intermediate times, the code phase.

Nonmultiple in General, the ratio of the frequency of the reference oscillator and tanks adders does not allow to obtain the exact value of the frequency. If to increase the accuracy of the output signal to limit capacity, then it should be done for both groups of adders that in the known devices is not provided.

In addition, proposed in the known device [3] multiplication source frequency n is possible only if the ratio of Foand Faboutis large enough and the result of multiplying remains inherently less capacity is accumulating adder.

The advantage of the proposed device in comparison with the known is that due to the correction capacity of the adders in Kadoma and the frequency of the reference signal is determined by the accuracy of the reference oscillator frequency, and the proposed scheme adders allows you to get maximum performance schema in a simple way.

The frequency synthesizer containing serially connected first register and a multiplier, connected in series reference oscillator and synchronization unit, a first multiplexer, a memory unit, connected in series, a second register, a digital-analog Converter and low pass filter, characterized in that it introduced N second multiplexers, N first adders, N second adders and N third registers, and the first inputs of the N first adders connected to respective outputs of the multiplier, the second inputs of the N first adders are interconnected with the output of the N-th of the third register, the output of each of the N first adders connected to the first input of the corresponding second adder, the output of the transfer of each of the N first adders connected with the control input of the corresponding second multiplexer, the N outputs of the second multiplexer is connected to the second inputs of the respective second adders, the output of each of which is connected to the third input of the corresponding register, the output of each of the N third registers connected to the respective input of the first-mudo second register, the respective outputs of the synchronization unit is connected to clock inputs of the N third registers, control inputs of the first multiplexer and a clock input of the second register, with the first N inputs of the second multiplexer are connected and are the input signal is "logic 0", the second inputs of the second multiplexer are connected and are input to which is fed the extension code.

 

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