The memory device data bus processor

 

(57) Abstract:

The data processing system has a Central processing unit (CPU) connected to a unidirectional bus read and unidirectional bus write address data memory (e.g. cache, NVR or disk) in the form of a cache memory. Bus read and bus write address is generated only in one direction. The technical result is to eliminate loss of time due to the reversal of the signal on the bus. Words read data (SD) and the command and data word (K) is transmitted from the cache memory in the core of the CPU bus read. Command-address (SA) words, words read address (SA), the write address (WA) and write data (ZV) multiplexed time division bus of entry and address for receipt of the core in the cache memory. The system transfers in batch mode, thereby reducing the number of addresses that you want to transfer on the bus and write addresses, freeing up bandwidth on the bus to use the words of write data. 2 S. and 6 C.p. f-crystals, 8 ill.

This invention relates to the field of data processing. Specifically, this invention relates to processing systems danyou, words read data and word data records.

Known data processing systems that include a processor, coupled to the data memory, such as cache memory, which stores the command-data words read data and word data records. Specialists in this field will be clear that the distinction between different data words depends on access, which is currently running with this data word, for example, a data word, which is currently being recorded in the data memory, can be considered the word of write data at this time, and at the same information word, then read from the data memory can be regarded as the word of read data.

The transfer of data words between a data memory and a corresponding processor often is a critical factor in the performance of such a data processing system. To improve the overall performance of the system, significant efforts are made to design the mechanism of transmission of these information words.

Fig. 1-4 of the accompanying drawings illustrates a typical known arrangement (similar to the integrated circuit ARM600 company advanced RISK Machine and the address bus 8, passing between the CPU 2 and memory-the memory 4. The CPU 2 includes a core 10, which responds to a command and a data word supplied thereto via the bus command and data words 12. The core 10 displays the word data records (ZV) shaper 30 to the data bus 6 and the recording address (A3) on the address bus 14 read and write. Address of record (FOR) upon its receipt by the memory cache 4 controls the location at which the word of write data (ZV) is stored in the memory cache 4. Similarly, the data bus 6 and the address bus 14 read and write can be used to read words read data (SD) memory cache 4 in the core 10 of the locations in memory cache of the 4 identified by the read address (SA) on the address bus 14 read and write.

Command and data word selected from the cache memory 4, is transmitted through the data bus 6 in block prefetch 16 (ARM600 has no block prefetch). Block prefetch 16 is designed to facilitate smooth and timely filing of command data words in the core 10, and performs functions such as recognition commands branching. Addresses in the cache memory 4, from which you select the command and data word are determined by the address uborki and the multiplexer 20 to the address bus 8. The multiplexer 20 is used to selectively connect or bus 18 program counter or address bus 14 read and write with address bus 8 depending on the team, not the signal of the flag data (a/D) generated by the core 10.

Alternatively, block prefetch register 16 contains IC counter and takes the value of the program counter back to the core 10 together with the corresponding command. In this case, the block 16 prefetch performs the main volume prefetch and necessary for the formation of the flag address FA. The core 10 provides the possibility of adjusting the size of the block, block prefetch for the effective management of its own pre-emptive sample.

In the cache memory 4 provides a matrix of memory cells 22, which are stored in the command-data words read data and word data records. Address bus B is supplied to the decoder 24 address that is used for selection of a memory cell or row of memory cells of the matrix of memory cells 22, depending on the address word read from address bus 8. Words read data selected from the memory cache 4, serves on the bus 26 read not 28 records data in a matrix 22 of memory cells.

To load data into the cache is not through the core 10 requires a different mechanism. For this mechanism will require its own shapers to make the flag lines appropriate values. Such a mechanism could work, for example, on the unsuccessful appeal to the cache. This mechanism will work, usually with a much slower speed than the core 10, but it is not critical to the performance of the system.

An important consideration in the configuration of this system, as shown in Fig. 1, is that the data bus 6 and the address bus 8 tend to be more the length of the track, and therefore a relatively large suitable container. To overcome this difficulty, put on these tyres words need to actively build on the tires, so as to speed up the period of achieving the correct values of the signal levels of the individual bus lines. For this scheme 30 shaper in the CPU 2 generates the words of write data on the data bus 6. Similarly, the circuit 32 of the imaging unit into the cache 4 forms of words read data on the data bus 6. The advantage here is that at any given moment will act on only one of these two formers for the data bus 6. The signal flag read () I these two formers 30, 32. The driver 34 in the CPU 2 serves to form the address word on the address bus 8.

Fig. 2 depicts the system of Fig. 1 when the sample command and data words. In this mode, the multiplexer 20 switches the value of the IC on the address bus 8 to select the location of the command address of the cache memory 4. Command information word To, access to which is provided in such a way, served in the core 10 through the bus reading 26, the imaging unit 32, the data bus 6, block 16 prefetch and tire 12 teams.

Fig. 3 depicts the operation of the system of Fig. 1 in the transmission of words of read data. In this case, the multiplexer 20 selects the read address SA of the core 10 to feed the address bus 8 to the decoder 24 addresses. The word data is read, the access to which is provided so that goes back to the core 10 through the bus 26 is read, the driver 32 and the data bus 6.

Finally, Fig. 4 depicts the operation of the system of Fig. 1 in the transmission of speech data records. In this case, the address of record A3 comes from the core 10 to the multiplexer 20 to the address bus 8. After one cycle, the core 10 generates the word of the write data SECTION and submits it to the driver 30, the data bus 6 and bus entries 28 in the matrix 22 remember generates the data bus 6. On the contrary, during the transmission of speech data write driver 30, the CPU 2 generates the data bus 6. In order to avoid contradictions between the two formers 30, 32 it is important that they have never begun to form a data bus 6 at the same time. This contradiction may result in damage to the circuit and will unnecessarily consume significant amounts of energy. To protect yourself from these contradictions must be sustained delay period between switching off one of the shapers 30, 32 and the inclusion of another shaper 30 or 32. This requires two separate control signal or the exact bronirovanie in the buffers (i.e., slow turn on and fast turn off).

To improve the overall performance of the systems depicted in Fig. 1-4, it is possible to follow different solutions. One of them is to increase the speed of the clock with which data is transmitted, for example, if the core 10 is used, the frequency "f" of this generator, you can use the speed of the generator is equal to "2f". However, solving problems and keeping appropriate synchronization sufficient delay between the formation of the data bus 6 driver (elevated) synchronization requirements.

Another solution to the problem of improving performance would be simply to increase the width of the tire. Wider tires allow you to send more data over a given period with a given speed clock signals. The disadvantage of this solution is that you need to increase the physical dimensions of the tire. In many cases, the increase in the physical size is a disadvantage from the point of view of manufacture, because you need a larger integrated circuit with a corresponding low output.

The first object of this invention is the integrated circuit that contains:

the cache data memory;

the processor, responsive to read from address command in said data memory command and a data word to read word data reading from address reading in said data memory and to write words write the data in the address entry in said data memory;

unidirectional bus read directly connecting the said data memory and said processor for transmitting mentioned command and data words and those words read data from the specified data memory in said processor; and

unidirectional bus is the catch data records, command-address words read address and said write address with said processor in said data memory;

in which the said data memory operates in the batch mode of access, which address word transmitted in said data memory, determines the starting address for the sequence of actions access to the next address in said data memory.

Unidirectional bus for data flow in one direction or another have the advantage that there is no need to provide the time necessary for the safe changing the direction of the tires on the back. Thus, the bus speed can be increased without creating synchronization problems. In addition, the invention took advantage of the fact that the data address supplied on the address bus, change relatively infrequently compared with the data on the data bus. Thus, multiplexing of data recording on the bus using the data address for the formation of the record bus and address more fully utilizes the available bandwidth.

In accordance with this invention the above-mentioned memory data valid packet access, in which adresi access to the next address in said data memory.

This batch mode of access is particularly suitable for use in this invention of the bus structure, since the word data should be available only when the start sequence is subjected to sample the command and data words or words of data read or to be write words write data. One word data address starts the process of sampling, which then goes successively following each other addresses until the end. So the bus write data and addresses need to carry fewer words data address, resulting freed bandwidth to pass the words of write data.

As mentioned above, it is possible to envisage a scheme shapers for data bus, in order to increase the speed with which reliably get the value of the signal, although the invention has the advantage of more intensive use of bus bandwidth, giving the address data even without these shapers, these shapers are well suited for use in this invention because they remain constantly active on the bus.

In the preferred implementation of the present invention indicated by the receipt of said read data to obtain those words read data, moreover, the specified block prefetch command and the specified circuit receiving said read data is connected in parallel to the specified bus read data.

The existence of a block prefetch speed up the processing of the command. Parallel connection circuit receiving said read data and block prefetch bus allows the reader to apply any command and a data word, or a word of data is read, not guiding them through the multiplexer; and a processor selectively activates either the block prefetch or circuit receiving said read data in accordance with need.

In the preferred implementation of the present invention mentioned data memory contains the receiver address decoder for receiving and decoding the specified command and address words, these words read addresses, and these words address entry, and the schema of the records for the specified words write data, and the signal line flag address passes between the specified processor and the specified receiver address and decoder for actuating the specified receiver address decoder.

Multiplexing data words and address words write data to the address of the data. This convenient flexibility is achieved by signal flag address control appropriate processing in the data memory.

In addition, it is preferable that the above-mentioned processor contains a multiplexer for selecting either the command-address words, or words read address and said write address, or words write data to connect to the said bus write address.

This provides a mechanism for the appropriate data on the data bus, the write address.

The preferred method of operation control data memory is to ensure that the line signal flag reading, passing between the said processor and said cache memory for data signal transmission flag is read; and the signal line flag record is held between the specified processor and the cache data memory for signal transmission flag the account and the signal line of the command flag passes between the specified processor and the memory cache of the data transmission flag team; in this way the said signal flag read signal flag entries and the command signal selects the mode of access to the data memory, and the specified flag of the read case, the data for the specified bus read has higher priority than transfer command and a data word.

Thus, the memory data can be entered in the proper mode for sampling said read data or command data words, or for storing words of data recording. In addition, the average processing speed is increased by the fact that the transmission of the word of read data is a higher priority than the priority of the command and a data word as a command and a data word are usually chosen in advance and is buffered in the system, while the sample of words read data tends to happen randomly as will require a separate decoded commands.

Another object of this invention is a method of data processing in the integrated circuit, which contains the following steps:

storing the command-data words read data words and write data in the data memory;

the mentioned transfer command and data words, and words read data from the specified data memory to the processor through a unidirectional bus read directly connecting the specified data memory and the processor; and

the transfer of these words read data, command and address words is th bus write address, directly connecting the said processor and said data memory;

and in which the specified data memory is running in batch mode access, which address word transmitted in the specified data memory, determines the starting address for the sequence of actions access for the subsequent addresses in the specified data memory.

The invention is illustrated as an example with reference to the accompanying drawings, in which

Fig. 1 to 4 depict a typical known system processor and the data memory;

Fig. 5 depicts a system processor and a data memory containing unidirectional bus in accordance with one implementation of the present invention; and

Fig. 6-8 depict the work of the variant according to Fig. 5 in different modes.

Fig. 5 depicts the CPU 36 core 38, which receives a word of data reading DM command and a data word To form a word write data to ZV. These words are transmitted between the CPU 36 and the cache 40 for unidirectional bus read 42 and unidirectional bus read address 44. Bus read 42 is connected in parallel with the block 46 prefetch scheme and receive data read into the core 38.

Bus 44 account and address is formed by the imaging unit 50 of the CPU 36, and the driver 50 receives its input from the tripartite multiplexer 52. Tripartite multiplexer 52 selects among the values of the SC counter of block 46 prefetch address read AC or address of record A3 with core 38, or data recording SECTION with the core 38. Select the three-way multiplexer 52, the signal is sampled depending on the address signal flag AF generated by the core 38, and signal flag FC generated by the block prefetch 46.

In the cache memory 40, the driver 54 generates a magnitude signal on bus 42 read data. Signals from bus 44 recording and addresses sent to the circuit 58 decoder address (latch 56 addresses controlled by the signal flag address FA), and a scheme to obtain data record.

It is noteworthy that although the above-described variant embodiment of the invention uses a scheme 58 decoder addresses, other options are also possible embodiment on the basis of acatalog cache (i.e., the search characteristic decoding).

Sample or words of read data or command data words of the cache memory 40 is controlled through the signal flag read FS, Nikon 38, shows that the words of write data must be received and stored by the memory cache 40 from bus 44 records and addresses.

In the diagram according to Fig. 5 - in contrast to the schemes of Fig. 1-4 bus 42 reading is unidirectional with the shaper 54 at one end only, and on that bus don't need to change its direction of transmission. Accordingly, you don't need to change direction, making it possible to avoid potential damage and unnecessary power consumption due to contradictions schemes shapers. Address data and write data are multiplexed time division bus 44 recording and addresses of three-way multiplexer 52.

Fig. 6 depicts a system working in mode prefetch commands. In this mode, the value of IC address counter is supplied to the decoder 58 address block 46 prefetch tripartite multiplexer 52, the driver 50, the bus 44 records and addresses, and the latch 56 address. The signal flag address FA is ENABLED and the signal flag FC is ENABLED. This combination of signals controls the three-way multiplexer 52 to select the values of IC address counter of the block 46 prefetch for its application through the driver 50 to the bus 44 recording and Adri selected from addresses, certain bus 44 records and addresses. This command information word is returned to the CPU 36 through the shaper 54, bus 42 reading unit 46 prefetch and bus commands 48.

This system operates in a batch mode in which a value IC of the initial address counter specifies the address from which precede the sequential fetching up until will not be submitted to the following address. The latch 56 address provides input to the circuit 58 of the address decoder; and circuit 58 of the address decoder includes a counter to increment the address during operation in batch mode.

Fig. 7 depicts the effect of reading the data for a system according to Fig. 5. In this case, the words read data sent from the memory cache 40 to the core 38 by the imaging unit 54 and the bus 42 read data. The read address AU is selected tripartite multiplexer 52 in response to the signal flag address FA, claiming on, and the flag FC, approver off. Accordingly, the read address supplied to the cache 40 to the driver 50, the bus 44 records and addresses, the latch 56 address and decoder 58 addresses. ENABLED flag address flag ENABLED read DISABLED flag record due priobretaet preemptive priority over the sampling team. Therefore, if the block prefetch 46 says that the signal flag FC is ENABLED, indicating that it is ready to accept a subsequent command and a data word, and if the core 38 States that the signal flag read FS is ENABLED, the logic in the cache memory 40 perceives reading as having a higher priority and returns via the bus 42 reads the requested word of the read data instead of the data word.

Fig. 8 depicts a system according to Fig. 5-mode memory words of write data in the cache memory 40. In this mode, the flag of the address signal SA alternates between approval on and off depending on the output at this time, the core 38 recording address A3 or words of write data. The signal flag FC is approved as off, and the signal flag address FA controls the three-way multiplexer 52 to select the proper address of record (A3) or word write data, and attaches them to the bus 44 account and address driver 50. Words of write data, the write addresses so effectively multiplexers time division bus 44 records and addresses. Thanks to the transfer of records in the batch mode, the address entry required only at infrequent intervals, such as gr is Cesky would decrease throughput for recording half.

In the cache memory 40, the receiver 56 of the address latch address) responds to the magnitude of the signal flag address FA to collect the address word on bus 44 records and addresses. The signal flag write FZ approved as off and on (in opposition to the flag address FA), indicating the cache 40, you need to remember the words of write data from the bus 44 records and addresses.

1. Integrated circuit that contains the cache data memory, the processor, responsive to the command data word read from the addresses of the commands in the specified memory to read word data reading from address reading in the specified data memory and to write words write the data in the address records in the specified data memory, unidirectional bus read directly connecting the specified data memory with the specified processor to send the specified command and data words, and these words read data from the specified memory data in the specified processor, and a unidirectional bus write address, directly connecting the specified processor and the specified data memory for transferring said write data, word address command, said read address and said address entries from the specified processor in the specified data memory; in which the memory anyedelae the starting address for the sequence of operations for the subsequent addresses in the specified data memory.

2. Integrated circuit under item 1, in which the specified data memory contains the schema driver bus for reading values forming the signal transmitted on the specified bus read data.

3. Integrated circuit under item 1 or 2, in which the specified processor contains a diagram of the driver record bus and addresses values forming the signal transmitted on the specified bus recording and data addresses.

4. Integrated circuit according to any one of the preceding paragraphs in which the specified processor contains the block prefetch commands to obtain the specified command and data words, and a circuit receiving said read data to obtain those words read data, and the specified block prefetch command and the specified circuit receiving said read data is connected in parallel to the specified bus read data.

5. Integrated circuit according to any one of the preceding paragraphs in which the specified data memory contains the receiver address decoder for receiving and decoding the specified command and data words, these words read addresses, and these words address entry, and the schema of the records for the specified words write data, and in which Lin is rivedere in action specified receiver address decoder.

6. Integrated circuit according to any one of the preceding paragraphs in which the specified processor includes a multiplexer processor for selection or command-address words, or words read address and said write address, or words write data to connect to the specified bus records and addresses.

7. Integrated circuit according to any one of the preceding paragraphs, containing the signal line flag reading, passing between the specified processor and the cache data memory for signal transmission flag read signal line flag records passing between the specified processor and the cache data memory for signal transmission flag recording, and the signal line flag commands passing between the specified processor and the cache data memory for signal transmission of the command flag in which the specified signal flag is read, the specified signal flag record and the specified command signal selects the access mode of the specified cache data and the specified flag is read is to ignore the specified signal flag command to transfer a word of data is read at a specified bus read would have a higher priority than the transmission command and a data word.

8. The way obrabotannykh and words of write data in the data memory; transmit the specified command and a data word and for the word of read data from the specified data memory to the processor through a unidirectional bus read directly connecting the specified data memory and the processor, and transmit these words of write data, command and address word, the word of the read address and the word address entry with the specified processor in the specified data memory for unidirectional bus write and address, directly connecting the specified processor and the specified data memory to which the memory data valid packet access, which address word transmitted in the specified data memory, defines the starting address for the sequence of operations for the subsequent addresses in the specified data memory.

 

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