Device for frame synchronization

 

(57) Abstract:

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital transmission systems with a temporary seal. The technical result - increased robustness. Due to the introduction of the second and third schemes match, second and third analyzers coincidence of timing, the first, second and third elements are NOT, first and second elements And the first and second elements OR element OR NOT the device supports matching errors demodulator and subsequent incorrect staffaroni and, therefore, normal operation of the device at high noise level. 2 Il.

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital transmission systems with a temporary seal.

A device for frame synchronization [1], containing the detector clock cycle, the analyzer matches the clock input of the device, the block selection clock frequency pulse distributor, the output of the device, the trigger, the first, second and third elements And the element OR register.

This device coenia in cyclic synchronism is not enough when the cycle length is several times greater than the length of the register and a high level of interference.

The closest to the technical nature of the claimed invention is selected as a prototype system frame synchronization [2], containing the detector clock cycle, consisting of a shift register circuit and the coincidence analyzer coincidence of timing, solver, unit selection clock frequency generating equipment (pulse generator).

The disadvantage of this device is the low noise at high noise level, resulting in large loss of information.

The aim of the invention is to increase the noise immunity.

This goal is achieved by the fact that in the device for frame synchronization, containing the shift register, the input of which is the input of the circuit matches the output of which is connected to the analyzer matches the timing analyzer matches the clock input T connected to the output of the "T" of the pulse generator, and the output is the output of the device, the crucial device whose output is the second output device, the block selection clock frequency, the input of which is connected to the input device and the output connected to the input of the pulse generator, generac is which and third analyzers coincidence of timing, the second and third analyzers match clock inputs T of which is connected to the output of the "T" of the pulse generator, the first, second and third elements are NOT, the inputs of which are connected respectively with the second, first and third analyzers coincidence of timing, the first item, the inputs of which are connected with the first analyzer coincidence of timing, second, and third elements are NOT, and the output and is connected to the input "+1" of the pulse generator, the second And gate, the inputs of which are connected with the third analyzer coincidence of timing, the first, second elements are NOT, and the output connected to the input of the second element OR the first element OR the input of which is connected to the analyzers coincidence of timing, and the output from the deciding device and the element OR NOT, the second element OR, the inputs of which are connected with the element OR NOT and the second element, And an output connected to the input "-1" pulse generator, the element OR NOT, the inputs of which are connected with the first element OR the deciding device, and the output of the second OR element.

In digital transmission systems with a temporary seal at a high level of interference most often errors occur in the demodulator: logical "0" is logical "1" and Vice versa. Pino is determined, him, or in his absence falsely determined that he is. As a result, in the digital stream of the lower level of the hierarchy is either added a non-existent data bits, or removes an existing one. Therefore, the frame synchronization pulse is shifted left or right by one bit. The usual device for frame synchronization, in this case, out of synchronism, then re-searches for the clock and input in synchronism, resulting in lost a lot of information signals. The proposed device for frame synchronization in this situation is not out of synchronism and, therefore, does not lose this information.

The novelty of technical solutions is available in the inventive device of new circuit elements: the second and third schema matching, second and third analyzer coincidence of timing, the first, second and third element, the first and second element And the first and second element, OR the element OR NOT.

Thus the invention conforms to the criterion "novelty".

Analysis of the known technical solutions in the study and related fields allows us to conclude that the introduced functional nodes know the Wu new properties. Introduced functional units interact in such a way that allow to maintain synchronism when errors demodulator and subsequent incorrect staffaroni and, therefore, normal operation of the device for frame synchronization at a high level of interference.

Thus, the invention meets the criterion of "Inventive step", as it is for the expert is not obvious from the prior art.

The invention can be used in digital transmission systems with a temporary seal.

Thus, the invention meets the criterion of "Industrial applicability".

In Fig. 1 shows a block electrical diagram of an apparatus for frame synchronization, Fig. 2 shows a block circuit diagram of the pulse generator.

The device (Fig. 1) contains a shift register RS 1, schema matching CC2 2, CC1 3, SS3 4, the block selection clock frequency WH 5, analyzers coincidence of timing A2 6 A1 7, A3-8, the pulse generator GI 9, item OR 10 items 11, 12, 13, solver RU 14, elements 15, 16, the element OR NOT 17, item, OR 18, and the input of the shift register PC 1 is connected to the input of the output register is 4 - from category 3 to n, the outputs of the circuits match connected respectively with analyzers coincidence of timing A2 6 A1 7, A3-8, the output of the analyzer A2 6 is connected with items AND 15, OR 10 and NOT 11, the output of the analyzer A1 7 is connected with elements NOT 12 OR 10 and the first output device, the output of the analyzer A3 8 is connected with the elements AND 16, OR 10 and NOT 13, the output element 11 is connected to the element And 16, the output element 12 is connected with items And 15 and 15, the output element 13 is connected to the element And 15, the output element And 15 connected to the input "+1" of the pulse generator GI 9, the output element And 16 connected to the element OR 18, the output of the OR element 10 is connected with the element OR NOT 17 and a deciding unit RU 14, the output of a casting device RU 14 is connected with the second output device and the input of the element OR NOT 17, the output of the element OR NOT 17 is connected to the element OR 18, the output of the OR element 18 is connected to the input "-1" pulse generator GI 9, the input unit selection clock frequency WH 5 is connected to the input device, an output connected to the input "PM" of the pulse generator GI 9, the output of the pulse generator GI 9 "t" is connected with the inputs of the "t" analyzers A2 6 A1 7, A3-8.

The pulse generator (Fig. 2) contains a counter Midrange 19, the decoder DS 20, the decoder DS 21, the decoder DS 22, ale is tori DS 20, DS 21 and DS 22, the output of the decoder DS 20 is connected to the input element And 23, the output of the decoder DS 21 is connected to the input element And 24, the output of the decoder DS 22 is connected to the input element And 25, the input of the pulser "+1" is connected to whooami element 28 and 25, the input of the pulse generator "-1" is connected with the inputs of the element 27 and 23, the outputs of the elements are NOT 27 NOT 28 are connected to inputs of the element And 24, the outputs of the And elements 23, 24, 25 are connected to the inputs of the OR element 26, the output of the OR element 26 is connected to the input "Reset" the counter Midrange 19.

The device operates as follows.

In the search mode clock schema matching CC2 2, CC1 3 and SS3 4 not detecting synchronously, generates a logical "0". Accordingly analyzers match A2 6 A1 7 and A3 8 and output "0". Item OR 10 produces the output "0" which is supplied to the element OR NOT 17 and solver RU 14, which is not in a state of synchronism. As a result, the element OR NOT 17 outputs a logical "1" which, passing through the elements OR 18, is fed to the input "-1" pulse generator GI 9, causing a delay of one period of the clock frequency. This process will povtoryatsa up until one matches will not detect synchronously, Hema match SS3 4, which is connected to the shift register from bit 3 to n, and, therefore, checks the signal earlier than CC2 2 and CC1 3.

As a result, when detecting synchronously analyzer A3 8 will output a logical "1", which will arrive on the item OR 10, then RU 14 and the element OR NOT 17. Solver RU 14 starts counting the number of cycles during which fixed synchronism, i.e., the decision to enter into synchronism is made based on the analysis of not one but several cycles. Element And 16 will output "1" as the output analyzer A3 8 logical "1" and the outputs A1 6 A2 7 logical "0". Consequently, the element OR 18 and further to the input "-1" KI-9 will be a logical "1", which will delay GI 9 for another cycle. This delay will lead to the fact that on the next cycle synchronization will be recorded by the analyzer A1 7, because the schema matching CC1 3 is connected to the shift register from category 2 to n-1. The device is normal sync mode.

During this mode, the outputs of the elements 15, 16, OR NOT 17 OR 18 is a logical "0". Therefore, if singlecompany was correctly found, at each cycle at the outputs of these elements are "0" and the generator impul described above - by adding or deleting information bits at the wrong staffaroni. This singlecompany shifted left or right by one bit. As a result, when the pulse generator generates another signal analyzers A2 6 A1 7 and A3 8, singlecompany is not detected by the analyzer A1 7 and the analyzer A2 6 - if there has been a shift to the right, or the analyzer A3 8 - if there has been a shift to the left.

If there has been a shift to the right, then a logical "1" from the analyzer A2 6 and, respectively, a logical "0" with analyzers A1 7 and A3 8 will provide a logical "1" at the output of the OR element 15, which enter the input "+1" KI-9, will increase by one clock cycle number of clock cycles of the generator prior to the issuance of the next pulse analyzers A1 7, A2-6 and A3-8. As a result of this correction the next pulse generator GI 9 again coincides with the detection of synchronously scheme matches CC1 3 and, thus, will be restored to normal operation of the device without loss of synchronism.

If there has been a shift to the left, then a logical "1" analyzer A3 8 and, respectively, a logical "0" with analyzers A2 6 A1 and 7 will provide a logical "1" at the output of the OR element 16, which, having entered the entrance "-1" KI-9, will be delayed for one clock cycle number of clock cycles generators is Torah KI-9 coincides with the detection of synchronously scheme matches CC1 3 and will continue normal operation of the device.

The pulse generator GI 9 operates as follows.

The decoder DS 21 is configured to cycle length N and when the CQ counter 19 has reached the end of the cycle, the decoder DS 21 generates at its output the signal to reset the counter. When the device is already in a state of synchronism, the inputs "+1" and "-1" of the pulse generator is "0", the items are NOT 27, 28 and 24, 23, 25 are such that the reset input of the counter Midrange 19 receives a reset signal from the decoder DS 21.

When searching for a clock input "-1" pulse generator is "1", through which items are NOT 27, 28 and 23, 24, 25 allows the reset of the counter decoder DS 20 that is configured to length N-1. Thus, the distance between the pulses from the KI-9 and synchronously is reduced by one step, as long as the device does not detect synchronously and the signal "1" will be removed from input "-1" pulse generator.

When applying to the input "+1" pulse generator "1" when it is necessary to increment the number of clock cycles of the generator prior to the issuance of the next pulse analyzers coincidence of timing A2 6 A1 7 and A3 8, items are NOT 27, 28 and 23, 24, 25 allow the reset of the counter decoder DS 22 that is configured to length N+1. Thus, the distance between and is recombinatio and the signal "1" will be removed from input "+1" of the pulse generator.

Device for frame synchronization in comparison with the prototype provides increased robustness of digital transmission systems with a temporary seal, as it provides reliable operation for frame synchronization, without loss of synchronism, with the most common impediments encountered.

Sources of information

1. RF patent N 2019046, CL H 04 L 7/08.

2. Gitlin M. C., Leo A. Y. Theoretical foundations of multi-channel communication. M.: Radio and communication, 1985, S. 159 - 166, Fig. 84.

Device for frame synchronization, containing the shift register, the input of which is the input of the circuit matches the output of which is connected to the analyzer matches the timing analyzer matches the clock input T connected to the output of the "T" of the pulse generator, and the output is the output of the device, the crucial device whose output is the second output device, the block selection clock frequency, an input connected to the input device and the output connected to the input of the pulse generator, the pulse generator, characterized in that the introduced second and third schema matching, United respectively with the second and third analyzers coincidence of timing, the second and the first, the second and third elements are NOT, the inputs of which are connected respectively with the second, first and third analyzers coincidence of timing, the first item, the inputs of which are connected with the first analyzer coincidence of timing, second, and third elements are NOT, and the output connected to the input of "+1" of the pulse generator, the second And gate, the inputs of which are connected with the third analyzer coincidence of timing, the first, second elements do NOT, and the output connected to the input of the second element OR the first element OR the input of which is connected to the analyzers coincidence of timing, and the output from the deciding device and the element OR NOT, the second element OR, the inputs of which are connected with the element OR NOT and the second element, And an output connected to the input "-1" pulse generator, the element OR NOT, the inputs of which are connected with the first element OR the deciding device, and the output from the second element OR.

 

Same patents:

The invention relates to techniques for telecommunication and can be used in the transmission channels for digital conversion of signals, working both in time and frequency domain

The invention relates to digital communication systems and can be used in communication networks, in particular in apparatus for the formation and separation of digital streams

The invention relates to the field of telecommunications and computer technology and can be used in data exchange systems to ensure synchronization of the asynchronous pulse reading and writing information

The invention relates to techniques for electrical connection, in particular to a device for frame synchronization, and may find application in digital switching systems

The invention relates to electrical engineering and can be used in systems of high-precision synchronization of spatially-separated time scales

FIELD: digital communications.

SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.

EFFECT: higher reliability, higher effectiveness, higher interference resistance.

1 cl, 3 dwg

FIELD: communications.

SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.

EFFECT: higher trustworthiness.

1 dwg

FIELD: digital communications;

SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.

EFFECT: enlarged functional capabilities.

1 cl, 2 dwg

FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.

SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.

EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.

1 dwg

FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.

EFFECT: increased interference resistance of device for cyclic synchronization.

4 dwg

FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.

SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.

EFFECT: expanded functional capabilities of device for cyclic synchronization.

2 cl, 3 dwg

FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.

SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.

EFFECT: increased interference resistance of cyclic synchronization.

2 cl

FIELD: data processing in broadband radio communications and radio navigation.

SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.

EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.

2 cl, 9 dwg

FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.

SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.

EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.

1 cl, 9 dwg

Up!