Generator read address interleaved

 

(57) Abstract:

The invention relates to a generator read address interleaved to read data recorded in the memory is interleaved, for use in a mobile communication terminal type D. The technical result is to create a simple generator read address when the alternation. The technical result is achieved due to the fact that the generator read address interleaved includes a counter with base 18 for counting input clock pulses modulo 18 for forming the address bits of the column counter with base 32, working from the signal transfer from the counter with base 18, for counting input clock pulses modulo 32 for the formation of the counted value and the multiplexer to change the position of the output bits of the counter with base 32 in accordance with the selection signals data speeds for variable generation address bits row. 2 c. and 8 C. p. F.-ly, 11 tab., 3 table.

The present invention relates to an interleaver for use in a mobile station PCS (Personal communication services) type (CDMA multiple access, code-division multiplexing), and more specifically to the generation who, stored interleaved.

The level of technology.

In accordance with the Standard SP-3384 for CDMA PCS mobile station is determined that CDMA PCS mobile station must perform the interleaving to prevent impulse errors or reverse channel. Interleaving (interleaving) is achieved using a serial write data transfer in the memory in the sequence, and then the serial data is read from memory, if possible.

Known interleaver (Fig. 1) for receiving the interleave includes a counter 10, the memory type ROM (permanent memory) 12, an adder 14, the generator 16 reference address and memory type RAM (RAM memory) 18. The counter 10 counts the clock pulses of the system and supplies the counted value in the ROM 12 in which to store the read address when the rotation corresponding to the calculated value. After receiving the counted value ROM 12 generates a read address with the rotation corresponding to the calculated value. The generator 16 reference address generates a reference address for reading and writing data from/to RAM 18 during rotation. The adder 14 adds the read address when the alternation issued from the ROM 12, the reference address is issued from the generator which provides the recorded data into it. The RAM 18 with striping writes data supplied from the outside, and reads the data recorded in it, in accordance with the read address when the alternation issued from the adder 14.

As can be seen from the preceding description, known interleaver necessarily includes expensive ROM memory in which to store the read address interleaved, thus increasing the manufacturing cost of the interleaver.

Meanwhile, in accordance with the above Standard SP-3384 interleaver has a variable data rate. In other words, the Standard SP-3384 determines the data rate of 9600 bps and 14400 bit/s, the data rate of 4800 bps and 7200 bps, the data rate of 2400 bit/s and 3600 bit/s and the data rate of 1200 bps and 1800 bps. The interleaver shall perform differently interleaving with respect to the corresponding velocity data. Accordingly, the CDMA system with variable data rate should include a ROM in which to store the read address with the alternation for the corresponding velocity data in order to perform interleaving. When the data rate is variable, as indicated above, the ROM has increased to record data, so that the ROM has increased the dres read alternation according to each speed data leading to increased cost. In particular, if the mobile station type CDMA PCS, operating in the Standard SP-3384, ROM will increase in value, causing problems with the increase in the cost.

The essence of the invention.

The present invention is to create a simple generator read address when the alternation, consisting of counters and logic gates.

According to the aspect of the present invention, the generator of the read address with the alternation includes a counter with base 18 for counting the input clock signals on the module 18 for forming bits of the column address counter with base 32, working on a carryout from the counter with base 18, for counting the input clock signals modulo 32 for forming the bit line address and the multiplexer to change the position of the output bits of the counter with base 32 in accordance with the selection signals data speeds for AC formation of the address bits of the string.

A brief description of the drawings.

The above and other objectives, features and advantages of the present invention will become more clear in the light of the subsequent detailed description nailo is availa able scientific C with the prior art,

Fig. 2 is a diagram depicting the organization of data when writing data in the memory is interleaved with data bit rate of 9600 bps and 14400 bps,

Fig. 3 is a chart depicting the organization of data when writing data in the memory is interleaved with data bit rate of 4800 bps and 7200 bps,

Fig. 4 is a chart depicting the organization of data when writing data in the memory is interleaved with data bit rate of 2400 bit/s and 3600 bps,

Fig. 5 is a chart depicting the organization of data when writing data in the memory is interleaved with data speeds of 1200 bps and 1800 bps,

Fig. 6 is a chart depicting the sequence of rows read to read data recorded in the memory interleaving, in accordance with the relevant velocity data,

Fig. 7 is a diagram of the generator of the read address in alternation to form the read address when the alternation to read data when data speeds of 9600 bps and 14400 bps according to a variant implementation of the present invention,

Fig. 8 is a diagram of the generator of the read address in alternation to form the read address when the alternation to read data when the data rate of 4800 bps and 7200 bps according to a variant implementation of the resa read alternation to read data when the data bit rate of 2400 bit/s and 3600 bps according to a variant implementation of the present invention,

Fig.10 is a diagram of the generator of the read address in alternation to form the read address when the alternation to read data when data speeds of 1200 bps and 1800 bps according to a variant implementation of the present invention,

Fig. 11 diagram generator read address at alternating interleaved to form the read address when the alternation to read data at a variable data rate according to another variant implementation of the present invention.

A detailed description of the preferred variant embodiment of the invention.

Below will be described in detail the preferred implementation of the present invention with reference to the accompanying drawings in which the same numeric designations correspond to the same elements. Further, it should be clear that many details, such as detailed elements of the circuits shown only as an example for a better understanding of the present invention, and the present invention can be implemented without these details. In addition, it should be noted that detailed descriptions of relevant prior art can be deliberately omitted if cciu in-memory data striping, such as RAM (random access), when data is recorded at a rate of 9600 bps and 14400 bit/s in accordance with the standard SP-3384 for CDMA PSC mobile stations. As the number of the data being written is the same as the number of addresses, numbers, shown in Fig.2, are the same with the memory addresses interleaved. In other words, the number "1" represents the first data and the address of the first row and the first column and the number "2" represents the second data and the address of the second row and the first column. Similarly, the number "3" represents the third data and the address in the third row and the first column. Other numbers represent the corresponding data and addresses, as described above. It should be noted that this address organization equally applicable to other data speeds.

Data is written sequentially (Fig.2) in the order of addresses at speeds of 9600 bps and 14400 bps, and the recorded data is read in accordance with the read address with the alternation in time alternation. Fig. 6 illustrates the sequence of read address lines, the address read at the interchange. As shown, a sequence of reads of rows in data speed 9600 bps written all 18 columns of certain rows consistently read.

That is, in accordance with Fig.2 the sequence of read data with data speeds of 9600 bps and 14400 bit/s is 1, 33, 65, 97, 129,. .. 545, 2, 34,... and 576. Fig. 7 illustrates the generator read address when the alternation to form the read address when the alternation in accordance with the above sequence read data. Generator read address when the alternation includes a first counter 18CNT1 with the base 18 (vosemnadcatiletnij) and the first counter 32CNT1 with the base 32.

Read address with the alternation presents five address bits c9, c8, c7, c6 and c5 columns and five address bits c4, c3, c2, c1 and c0 of the string respectively. As shown in table 1 (see table at the end of the description), 32 line presents the address bits row c4, c3, c2, c1 and c0. It should be noted that the rows can be equally represented by address bits row c4, c3, c2, c1 and c0 at other speeds data.

Next, as shown in table 2 (see tab. at the end of the description), 18 columns presents the address bits column c9, c8, c7, c6 and c5. It should be noted that the column can be identical to the submitted address bits column c9, c8, c7, c6 and c5 at other speeds data.

Fig. 7 illustrates the address generator read interleaved to form an address read at the alternation in the sequence of read address striping for data speeds of 9600 bps and 14400 bps.

During operation, the first counter 18CNT1 with base 18 counts the input clock signals for the formation of the counted value (i.e., address bits column c9, c8, c7, c6 and c5, in which the address bits column c5 is the youngest significant bit (LSB), and the address bits column c9 is a senior significant bit (MSB). In this case, the counted value is the address of the column and increases from 00000 corresponding to the first column, up to 10001 corresponding to the eighteenth column.

The first counter 18CNT1 with base 18 forms a transfer on the exit of the transfer, when the counted value is changed from 10001 to 00000. The output signal of the transfer from the first counter 18CNT1 with the base 18 is fed to an enable output of the first counter 32CNT1 with the base 32. After receiving the output of the signal transfer from the first secondary market is the substance of the counted value of the address bit line c4, c3, c2, c1 and c0, in which the address bit line C0 is the youngest significant bit (LSB), and the address bit line C4 is a senior significant bit (MSB). In this case, the counted value is a string address and sequentially increases from 00000 corresponding to the first line, to 11111 corresponding to the thirty-second line.

As described above, the first counter 18CNT1 with base 18 counts the signals from 00000 to 10001 to generate column addresses 1, 33, 65, 129, 161, ... and 545, as shown in Fig.2. The first counter 18CNT1 with base 18 forms a transfer, when the counted value is changed from 10001 to 00000. Then, after receiving the output of the signal transfer from the first counter 18CNT1 with the base 18 of the first counter 32CNT1 with base 32 counts the dot clock for the formation of the counted value equal to 00001. At this point, the first counter 18CNT1 with base 18 again counts the signals from 00000 to 10001 to generate column addresses 2, 34, 66, 98, 130,. .. and 546. Similarly, generator read address with the alternation shown in Fig.7, generates a read address 576 interlaced.

Fig. 3 depicts the organization of data, when data is written to the memory is interleaved with STI interleaved are the same, as in the case of 9600 bps and 14400 bps, data bit rate of 4800 bps and 7200 bps in two times slower than the data rate of 9600 bps and 14400 bps. Accordingly, the data that should be recorded in the memory interleaving with a speed of 4800 bps and 7200 bit/s, recorded on two consecutive addresses. Therefore, the same data appears twice in relation to all data, as shown in Fig. 3. However, the data are interspersed through the address of the device during the rotation.

The data recorded on the two addresses are read according to the read address in the sequence, and the sequence of rows read address read at the interleaving shown in Fig.6. Namely, Fig.6 illustrates the sequence of address lines of the address read at the interchange. As shown, a sequence of reads of rows in the data rate of 4800 bps and 7200 bps is 1, 3, 2, 4, 5,... and 32.

That is, the sequence read data bit rate of 4800 bps and 7200 bps is 1, 33, 65, 129, 545, 2, 34,... and 576. Note that the column order is the same as in the case of a data rate of 9600 bps and 14400 bps, but the sequence of the rows is changed. Address bits c4110,... and 11111.

In General, the counter toggles the least significant bit (e.g., bit c0) between 0 and 1 and switches to the next bit in accordance with the youngest significant bit (i.e. bit c1), when the least significant bit c0 is switched from 1 to 0. However, when the data rate of 4800 bps and 7200 bps address bit line c1 switches first, and then switched sequentially row address bits c0, c2, c3 and c4. Therefore, the generator read address with interleaving for data speeds of 4800 bps and 7200 bps can be implemented by changing the output signal of the read address with interleaving for data speeds of 9600 bps and 14400 bps. Namely, the output bits c0 and c1 generator read address with interleaving for data speeds of 9600 bps and 14400 bps change each other for the implementation of the generator read address with interleaving for data speeds of 4800 bps and 7200 bps.

Fig. 8 illustrates the generator read address with interleaving for data speeds of 4800 bps and 7200 bps. Generator read address interleaved generates a read address interleaved sequence of read address interleaved. Generator read address interleaved includes in base 2) counters 2CNT1 and 2CNT2. The second counter 18CNT2 with base 18 forms a column address bits c9, c8, c7, c6 and c5 and the signal transfer in the same manner as shown in Fig.7 the first counter 18CNT1 with the base 18 of the generator read address interleaved to 9600 bps and 14400 bps. The output signal of the transfer from the second counter 18CNT2 with the base 18 is fed to an enable output of the first binary counter 2CNT1, which receives the clock signal on its clock input. Thus, whenever the output signal of the transfer is received from the second counter 18CNT2 with the base 18, the first binary counter 2CNT1 counts clock signals for the formation of the address bits c1 line. The first binary counter 2CNT1 generates a transfer, when the address bit line c1 is changed from 1 to 0. The output signal of the transfer from the first binary counter 2CNT1 is fed to an enable output of the second binary counter 2CNT2, which receives the clock signal on its clock input. Thus, the second binary counter 2CNT2 counts clock signals for the formation of the address bits c0-line whenever the first binary counter 2CNT1 generates a transfer. The second binary counter 2CNT2 generates a transfer, when the address b is th output of the first octal counter 8CNT1, which receives the clock signal on its clock input. Thus, whenever the second binary counter 2CNT2 create an output signal of the transfer, the first octal counter 8CNT1 counts clock signals for the formation of the address bits c4, c3 and c2 lines. Therefore, the read address with the alternation is formed in combination of the address bits column c9, c8, c7, c6 and c5 of the second counter 18CNT2 with the base 18, the address bits c4, c3 and c2 row octal counter 8CNT1, address bits c1 of the first binary counter 2CNT1 and address bits c0 of the second binary counter 2CNT2.

Fig.4 illustrates the organization of data, when data is written to memory interleaving with a speed of 2400 bit/s and 3600 bit/s in accordance with the standard SP-3384 for CDMA PSC mobile station. Although memory addresses with alternation are the same as and at a speed of 9600 bps and 14400 bit/s, the data rate of 2400 bit/s and 3600 bps 4 times slower than the speed of 9600 bps and 14400 bps. Accordingly, the data that should be recorded in the memory interleaving with a speed of 2400 bit/s and 3600 bit/s, recorded on four consecutive addresses. Therefore, the same data appears 4 times in comparison with all DV

Data is recorded sequentially on the four addresses are read in accordance with the read address with the alternation in time alternation, and the sequence of row addresses is read when the alternation is illustrated in Fig. 6. Namely, Fig.6 illustrates a sequence of lowercase address read at the interchange. As shown, the sequence of rows read data at speeds of 2400 bps and 3600 bps is 1, 5, 2, 6, 3, 7, 4, 8, 9, 13, ... and 32.

That is, the sequence of read data at speeds of 2400 bps and 3600 bps should be reading the 18 columns of the first row, and then the 18 columns of the fifth row, and so on, it Should be noted that the sequence of columns is the same as in the case of a data rate of 9600 bps and 14400 bps, but the sequence of reading is changed. Address bits row c4, c3, c2, c1 and c0 according to the reading order of the rows are represented 00000, 00100, 00001, 00101, 00010, 00110,... and 11111.

From the previous description it is seen that when the speed data 2400 bit/s and 3600 bps address bits c2 line switches first, and then switched sequentially address bits c0, c1, c3, and c4. Therefore, the generator read address striped for speed cityware with interleaving for data speeds of 9600 bps and 14400 bps. Namely, the output bits c0, c1 and c2 generator read address with interleaving for data speeds of 9600 bps and 14400 bps change accordingly to bits c2, c0 and c1 for the implementation of the generator read address striped for speed data 2400 bit/s and 3600 bps.

Fig.9 illustrates the generator read address striped for speed data 2400 bit/s and 3600 bps. Generator read address interleaved generates a read address interleaved in the sequence of read address interleaved. Generator read address interleaved includes a third counter 18CNT3 with the base 18, the first and second counters 4CNT1 and 4CNT2 base 4 and the third binary (base 2) counter 2CNT3. The third counter 18CNT3 with base 18 forms a column address bits c9, c8, c7, c6 and c5 and the signal transfer in the same manner as shown in Fig. 7 the first counter 18CNT1 with the base 18 of the generator read address interleaved to 9600 bps and 14400 bps. The output signal of the transfer from the third counter 18CNT3 with the base 18 is fed to an enable output of the third binary counter 2CNT3, which receives the clock signal on its clock input. Thus, whenever the third schneirla signals for the formation of the address bits c2 line. The third binary counter 2CNT3 generates a transfer, when the address bit c2 of rows changed from 1 to 0. The output signal of the transfer from a third binary counter 2CNT3 is fed to an enable output of the first counter 4CNT1 base 4, which receives the clock signal on its clock input. Thus, the first counter 4CNT1 base 4 counts the clock signals for the formation of the address bits c1 and c0 of the line whenever the third binary counter 2CNT3 generates a transfer. The first counter 4CNT1 base 4 forms a transfer whenever the address bits c1 and c0 of rows changed from 11 to 00. The output signal of the first transfer counter 4CNT1 base 4 is fed to an enable output of the second counter 4CNT2 base 4, which receives the clock signal on its clock input. Thus, whenever the first counter 4CNT1 base 4 forms the output signal of the transfer, the second counter 4CNT2 base 4 counts the clock signals for the formation of the address bits c4 and c3 line. Therefore, the read address with the alternation is formed in combination of the address bits c9, c8, c7, c6 and c5 of the third counter 18CNT3 with the base 18, the address bits c4 and c3 of the second counter 4CNT2 with the basis of the m-4.

Fig. 5 illustrates the organization of data, when data is written to memory interleaving at a speed of 1200 bps and 1800 bps in accordance with the standard SP-3384 for CDMA PSC mobile station. Although memory addresses with alternation are the same as and at a speed of 9600 bps and 14400 bit/s, the data rate of 1200 bps and 1800 bps 8 times slower than the speed of 9600 bps and 14400 bps. Accordingly, the data that should be recorded in the memory interleaving at a speed of 1200 bps and 1800 bps, recorded eight consecutive addresses. Therefore, the same data appears 8 times in comparison with all the data, as shown in Fig. 5. However, the data are interleaved by using the address of the device during the rotation.

Data is recorded sequentially in eight addresses are read in accordance with the read address with the alternation in time alternation, and the sequence of row addresses is read when the alternation is illustrated in Fig. 6. Namely, Fig.6 illustrates a sequence of lowercase addresses from the address read at the interchange. As shown, the sequence of rows read data at speeds of 1200 bps and 1800 bps is 1, 9, 2, 10, 3, 11, 4, 12, 5,... and 32.

From the previous description it is seen that when the data rate of 1200 bps and 1800 bps address bits c3 line switches first, and then switched sequentially row address bits c0, c1, c2, and c4. Therefore, the generator read address with interleaving for data speeds of 1200 bps and 1800 bps can be implemented by changing the output signal of the read address with interleaving for data speeds of 9600 bps and 14400 bps. Namely, the output bits c0, c1, c2, and c3 generator read address with interleaving for data speeds of 9600 bps and 14400 bps change accordingly to bits c3, c0, c1 and c2 for the implementation of the generator read address with interleaving for data speeds of 1200 bps and 1800 bps.

Fig.10 illustrates the generator read address with interleaving for data speeds of 1200 bps and 1800 bps. Generator address read from across enerator read address interleaved includes a fourth counter 18CNT4 with the base 18, the fifth and sixth binary counters 2CNT5 and 2CNT6 and second octal (base 8) counter 8CNT2. The fourth counter 18CNT4 with base 18 forms a column address bits c9, c8, c7, c6 and c5 and the signal transfer in the same manner as shown in Fig. 7 the first counter 18CNT1 with the base 18 of the generator read address interleaved to 9600 bps and 14400 bps. The output signal of the transfer of the fourth counter 18CNT4 with the base 18 is fed to an enable output of the fifth binary counter 2CNT5, which receives the clock signal on its clock input. Thus, whenever the fourth counter 18CNT4 with base 18 generates an output signal of the transfer, the fifth binary counter 2CNT5 counts clock signals for the formation of the address bits c3 line. Fifth binary counter 2CNT5 generates a transfer, when the address bits c3 line is changed from 1 to 0. The output signal of the fifth transfer binary counter 2CNT5 is fed to an enable output of the second octal counter 8CNT2, which receives the clock signal on its clock input. Thus, the second octal counter 8CNT2 counts clock signals for the formation of the address bits c2, c1 and c0 whenever the fifth binary Ti c2, c1 and c0 changed from 111 to 000. The output signal of the second transfer octal counter 8CNT2 is fed to an enable output of the sixth binary counter 2CNT6, which receives the clock signal on its clock input. Thus, whenever the second octal counter 8CNT2 create an output signal of the transfer, the sixth binary counter 2CNT6 counts clock signals for the formation of the address bits c4. Therefore, the read address with the alternation is formed in combination of the address bits c9, c8, c7, c6 and c5 fourth counter 18CNT4 with the base 18, the address bits c4 sixth binary counter 2CNT6, address bits c3 fifth binary counter 2CNT5 and address bits c2, c1 and c0 of the second octal counter 8CNT2.

As described above, the read address when the rotation can be freely formed in accordance with the speed data by simply changing the output signals from the address generator read interleaved with 9600 bps and 14400 bit/s, is shown in Fig.7. Therefore, it is possible to implement the address generator read alternation for each speed data by simply changing the input signals shown in Fig. 7 address generator read Fri generator read address with a variable rotation for the formation of the read address interleaved according to another embodiment of the present invention. As shown, the generator read address with a variable rotation includes a fifth counter 18CNT5 with the base 18, the second counter 32CNT2 with the base 32 and the multiplexer MUX. The fifth counter 18CNT5 with base 18 forms a column address bits c9, c8, c7, c6 and c5 and the signal transfer in the same manner as shown in Fig. 7 the first counter 18CNT1 with the base 18 of the generator read address interleaved to 9600 bps and 14400 bps. The output signal of the transfer of the fifth counter 18CNT5 with the base 18 is fed to an enable output of the second counter 32CNT2 with base 32, which receives the clock signal on its clock input. Thus, whenever the fifth counter 18CNT5 with base 18 generates an output signal of the transfer, the second counter 32CNT2 with base 32 counts the clock signals for the formation of the address bits c4, c3', c2', c1' and c0'. The multiplexer MUX receives the address bits c3', c2', c1' and c0' from the second counter 32CNT2 with the base 32 for forming the address bits c3, c2, c1 and c0 in accordance with the signals S3, S2, S1, S0 speed selection data. Table 3 (see the end of the description) is the truth table for the multiplexer MUX.

As can be seen from table 1, the multiplexer MUX generates various adress the s 9600 bit/s 14400 bit/s multiplexer MUX generates data bits c3', c2' c1' and c0' outputs c3, c2, c1 and c0, respectively. At this point, the generator read address interleaved implements the same function as the generator of the read address with the alternation shown in Fig. 7. The read address interleaved to 9600 bps and 14400 bps is formed in combination of the address bits c9, c8, c7, c6 and c5 of the fifth counter 18CNT5 with the base 18, the address bits c4 of the second counter 32CNT2 with the base 32 and the address bits c3, c2, c1 and c0 of the multiplexer MUX.

Further, in the case of a data rate of 4800 bps and 7200 bps multiplexer MUX generates data bits c3', c2' c0' and c1' outputs c3, c2, c1 and c0, respectively. At this point, the generator read address interleaved implements the same function as the generator of the read address with the alternation shown in Fig. 8. The read address interleaved to 4800 bps and 7200 bps is formed in combination of the address bits c9, c8, c7, c6 and c5 of the fifth counter 18CNT5 with the base 18, the address bits c4 of the second counter 32CNT2 with the base 32 and the address bits c3, c2, c1 and c0 of the multiplexer MUX.

In the case of a data rate of 2400 bit/s and 3600 bit/s multiplexer MUX generates data bits c3', c0' c2' and c1' outputs c3, c2, c1 and c0, respectively. At this point, the generator read address with cheredovaniya interleaved for 2400 bit/s and 3600 bps is formed in combination of the address bits c9, c8, c7, c6 and c5 of the fifth counter 18CNT5 with the base 18, the address bits c4 of the second counter 32CNT2 with the base 32 and the address bits c3, c2, c1 and c0 of the multiplexer MUX.

In addition, in the case of a data rate of 1200 bps and 1800 bps multiplexer MUX generates data bits c0', c3', c2' and c1' outputs c3, c2, c1 and c0, respectively. At this point, the generator read address interleaved implements the same function as the generator of the read address with the alternation shown in Fig. 10. The read address interleaved for 1200 bps and 1800 bps is formed in combination of the address bits c9, c8, c7, c6 and c5 of the fifth counter 18CNT5 with the base 18, the address bits c4 of the second counter 32CNT2 with the base 32 and the address bits c3, c2, c1 and c0 of the multiplexer MUX.

Meanwhile, the multiplexer MUX contains from the first to the sixteenth valves And AND1 - screen and16 and first to fourth valves OR OR1 - OR4. Address bits c0' of the second counter 32CNT2 with the base 32 is fed to the 4-th, 7-th, 10-th and 13-th gates AND4, AND7, AND10 and AND13. Address bits c1' of the second counter 32CNT2 with the base 32 is served on the 1st, 5th and 9th and 14th gates AND1, AND5, AND9 and AND14. Address bits c2' of the second counter 32CNT2 with the base 32 is served on the 2nd, 6th 11th and 15th gates AND2, AND6, AND11 and AND15. In addition, the address bits c3' of the second counter 32CNT2 with base 32 PI - fourth valves And AND1 - AND4. Thus, the set of first to fourth valves And AND1 - AND4 generates the address bits c0', c3', c2' and c1' outputs c3, c2, c1 and c0, respectively, in response to the signal S3 speed data from the high logic level to generate the read address interleaved for 1200 bps and 1800 bps.

Similarly, the signal S2 speed selection data is supplied to the fifth - eighth valves AND AND5 - AND8. Thus, the set of the fifth to eighth valves AND AND5 - AND8 generates the address bits c3', c0' c2' and c1' outputs c3, c2, c1 and c0, respectively, in response to the signal S2 speed selection data with a high logic level to generate the read address interleaved for 2400 bit/s and 3600 bps.

The signal S1 speed selection data is fed to the ninth to twelfth valves AND AND9 - AND12. Thus, the set from the ninth through the twelfth valves AND AND9 - AND12 generates the address bits c3', c2', c0' and c1' outputs c3, c2, c1 and c0, respectively, in response to the signal S1 of the speed data from the high logic level to generate the read address interleaved to 4800 bps and 7200 bps.

Further, the signal S0 speed selection data is served by 13 - 16 valves and AND13 - screen and16. Thus, a set of 13 to 16 ventia speed data with a high logical level, to generate the read address interleaved to 9600 bps and 14400 bps.

The first valve OR OR1 receives the output signals from 1, 5, 9 and 13 valves And AND1, AND5, AND9 and AND13 for the formation of the address bits c3. A second valve OR OR2 receives the output signals from the 2, 6, 10 and 14 valves AND AND2, AND6, AND10 and AND14 for the formation of the address bits c2. The third valve OR OR3 receives output signals from 3, 7, 11 and 15 of the valves AND AND3, AND7, AND11 and AND15 for the formation of the address bits c1. The fourth valve OR OR4 receives output signals from the 4, 8, 12 and 16 valves AND AND4, AND8, AND12 and screen and16 for the formation of the address bits c0.

As described above, the generator read address with interleaving is implemented using inexpensive counters. Further, the generator read address with a variable interleaving according to the invention includes a multiplexer for forming the read address with a variable rotation for different data speeds. Therefore, it is possible to create a generator read address interleaved with low cost.

Although the preferred embodiment of the present invention described above in detail, it should be clear that many changes and modifications of the basic concepts of the invention can be made special the ASS="ptx2">

1. Generator read address striped, characterized in that it contains a counter with base 18 for counting input clock pulses modulo 18 for forming the address bits of the colony, and counter with base 32, operationally connected through the signal transfer from the counter with base 18, for counting input clock pulses modulo 32 for forming the address bits of the string.

2. Generator under item 1, characterized in that the generator read address interleaved made with the possibility of forming a read address with interleaving for data speeds of 9600 bps and 14400 bit/s

3. Generator under item 1, characterized in that the generator read address interleaved made with the possibility of sharing with each other lower significant bits (LSB) of the counter with the base 32 and the lower significant bits plus 1 bit (LSB + 1) counter with base 32 for forming a read address for data speeds of 4800 bps and 7200 bit/s

4. Generator under item 1, characterized in that the generator read address interleaved made with the possibility of changes of lower significant bits (LSB) of the counter with the base 32 to the least significant bit plus 2-bit (LSB + 2) counter with base 32, ISM plus 2 bits (LSB + 2) to the least significant bit plus 1 bit (LSB + 1) to generate the read address with interleaving for data speeds of 2400 bps and 3600 bit/s

5. Generator under item 1, characterized in that the generator read address interleaved made with the possibility of changes of lower significant bits (LSB) of the counter with the base 32 to the least significant bit plus 3 bits (LSB + 3) counter with base 32, changes of lower significant bits plus 1 bit (LSB + 1) to the least significant bit (LSB), changes of lower significant bits plus 2 bits (LSB + 2) to the least significant bit plus 1 bit (LSB + 1) and changes of lower significant bits plus 3 bits (LSB + 3) to the least significant bit plus 2-bit (LSB + 2) so as to form a read address with interleaving for data speeds of 1200 bps and 1800 bits/s

6. Generator read address striped, characterized in that it contains a counter with base 18 for counting input clock pulses modulo 18 for forming the address bits column and counter with base 32, operationally connected through the signal transfer from the counter with base 18, for counting input clock pulses modulo 32 for forming the address bit line multiplexer to change the position of the output bits of the counter with the base 32 in saturator on p. 6, wherein the multiplexer is configured to output bits of the counter with base 32 in response to the signal speed selection data corresponding to the data speeds of 9600 bps and 14400 bit/s

8. Generator under item 6, wherein the multiplexer is configured to change the lower significant bits (LSB) of the counter with the base 32 to the least significant bit plus 1 bit (LSB + 1) in response to the signal speed selection data corresponding to the data speeds of 4800 bps and 7200 bit/s

9. Generator under item 6, wherein in response to the signal speed selection data corresponding to the velocity data 2400 bit/s and 3600 bps, the multiplexer is arranged to change the lower significant bits (LSB) of the counter with the base 32 to the least significant bit plus 2-bit (LSB + 2), changes of lower significant bits plus 2 bits (LSB + 2) to the least significant bit plus 1 bit (LSB + 1) and changes of lower significant bits plus 1 bit (LSB + 1) on the least significant bit to generate a read address with interleaving for data speeds of 2400 bps and 3600 bit/s

10. Generator under item 6, wherein in response to the signal speed selection data corresponding to the data speeds of 1200 bps and 1800 bps, multiplex bits plus 3 bits (LSB + 3), changes of lower significant bits plus 3 bits (LSB + 3) to the least significant bit plus 2-bit (LSB + 2), changes of lower significant bits plus 2 bits (LSB + 2) to the least significant bit plus 1 bit (LSB + 1) and changes of lower significant bits plus 1 bit (LSB + 1) to the least significant bit to generate a read address with interleaving for data speeds of 1200 bps and 1800 bps C.

 

Same patents:

The invention relates to information technology, namely the means of reproduction of information, mainly from optical media

The invention relates to computing, and in particular to an external storage device (DDT), and can be used in controllers DDT

FIELD: optical data carriers.

SUBSTANCE: at least one free area is determined in position, following noted data area of user. Said free area is distributed in backward order from the last element of noted area. When replacing damaged elements of user data it is used from last elements of said free data area.

EFFECT: higher efficiency.

2 cl, 7 dwg

FIELD: data carriers.

SUBSTANCE: to determine origin of data carrier disk, errors are used, which appear during manufacture process of master-disk, and are imparted to later batches. Data from said disk in non-corrected form are read, then data about errors is retrieved. Characteristic information about errors is provided and extracted data is compared to characteristic data, which characterizes all data carriers, manufactured by same source. As a result of correlation of compared data, origin of disk is judged either known or unknown.

EFFECT: higher efficiency of copy-protection measures.

4 cl, 7 dwg

FIELD: data carriers.

SUBSTANCE: at least one free area is determined in location, following said user data area. Said free data area is distributed in reverse order from the last element of noted area. When replacing damaged elements of user data it is used starting from last elements of noted free data area.

EFFECT: higher efficiency.

2 cl, 5 dwg

FIELD: optical data carriers.

SUBSTANCE: data carrier has data area. The latter has multiple zones, in which code blocks with error corrections are formed and sectors remaining as a result of sliding replacement at the end of zone, number of which is less than necessary for forming of one code block with error corrections. Said sectors are not used for recording one code block with error corrections and are skipped, and said code block with error corrections is formed at the beginning of next zone after skipping sectors of zone noted above. Carrier has additional free space, necessary for skipping sectors remaining at the end of zone during sliding replacement process.

EFFECT: higher efficiency.

2 cl, 9 dwg

FIELD: optical data carriers.

SUBSTANCE: method includes following stages: forming of a group of multiple zones on disk, while a group includes data area of user, including code block with correction of mistakes, distribution of primary, free space for the group. Additional free space is distributed with possible exclusion of discontinuousness of code block with correction of mistakes contained in user data area, at the limit between zones and distribution of it at two zones. Such distribution may be realized by skipping sectors at the end of zone, of their number is less than needed for forming code block with correction of mistakes with correction of primary position of code block with correction of mistakes at limit between zones.

EFFECT: higher efficiency.

3 cl, 9 dwg

FIELD: optical data carriers.

SUBSTANCE: primary reserved area, marked out during initialization, is present on data carrier. Also present is auxiliary reserved area, marked after initialization and/or expanded reserved area. Additional reserved area is marked in directly, starting from back portion of data zone.

EFFECT: excluded double replacements and marking of normal blocks as defect ones.

2 cl, 11 dwg

FIELD: optical data carriers.

SUBSTANCE: disk has recording area, where data are recorded in at least one physical cluster, defect area, in which defect, preventing recording and/or reproduction of data, is present in recording area, and recording end area, in which information, pointing to end of recording, is recorded prior to defect area. After defect area a link is set.

EFFECT: broader functional capabilities, higher efficiency.

4 cl, 11 dwg

FIELD: technology for recording information onto data carrier, having shape of disc, like those of optical or magnetic disc.

SUBSTANCE: in accordance to recording method, onto disc, having multiple recording tracks, separated on blocks, recording area of which has addressed user area with free access, serial data packets are recorded in different blocks of addressed user area with free access, prior to recording session, given portion of addressed user area with free access is cached as replacement zone, if damaged block is detected, replacing record for appropriate data packet is performed in aforementioned area for replacements of addressed user area with free access, in accordance to which during recording session size of aforementioned replacement zone is altered dynamically in accordance to requirements for replacement zone.

EFFECT: decreased number of leaps of recording head during recording, higher efficiency of disc capacity use.

2 cl, 3 dwg

FIELD: methods of recording and/or playing back for optic record carriers.

SUBSTANCE: method of recording and/or has the following steps: reading address from record carrier out (record carrier has at least first and second areas - data is recorded to first are and the first area goes after the second one. Information of address represents location of the second area), detecting of error, which corresponds to error detection code used for coding address information, which is read out from record carrier. When result of step of determination represents that the error was detected in address information, which was read out of record carrier the note comes to user on the error detected.

EFFECT: improved stability of recording; improved stability in data recording.

125 cl 11 dwg

FIELD: information storage; storage disk with temporary informational area of fault control.

SUBSTANCE: disk contains fault control area, temporary fault information area which is formed in data area and in which temporary fault information is written, and temporary informational area of fault control. Thus, it is possible to write user data to a recordable disk carrying out fault control.

EFFECT: effective usage of fault control area which has a limited capacity.

77 cl, 14 dwg

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