# Neuroprocessor, a device for computing functions of saturation, the computing device and the adder

(57) Abstract:

The invention relates to computing and can be used for the formation of neural networks. The technical result is the extension of functionality by changing the bit results. Neuroprocessor contains registers, memory blocks store type, the switch, the computing device, the shift register and device for calculating functions of saturation, the device for calculating functions of saturation is built on logical units, multiplexers and distribution scheme and the formation of transfers. The computing device contains a matrix multiplication, decoders, flip-flops, elements PROHIBITION and multiplexers. The adder performed on the logical elements and the formation scheme transfers. 4 C. and 4 h.p. f-crystals, 9 Il. The group of inventions relates to the field of computer engineering and can be used for emulation of neural networks and digital signal processing in real time.Known neuroprocessor [1] containing the register input data and four neural node, each of which consists of a shift register, register of weights, eight mind is the processor in each step performs a weighted summation of a fixed number of input data for a fixed number of neurons regardless of the actual range of input data values and their weights. Each input datum, as well as each weight is represented as the operand of a fixed width defined by the width of the hardware nodes neuroprocessor. However, the values of the input data and weights may vary within a wide range as you move from one neural network to another, and from one fragment of a neural network to another segment in the same network. Therefore, when emulating a neural network or its fragment with small values of the input data and / or weights equipment known neuroprocessor is used inefficiently.Thus, the main disadvantage of neuroprocessor is the lack of ability to programmatically change the capacity of processed input data and their weights, which in turn leads to hardware redundancy and relatively low productivity of neuroprocessor when emulation fragments of neural networks with small values of the input data and / or weights.The closest in technical essence to the first invention is neuroprocessor [2], which contains three register, multiplexer, memory block Ramaswamy bit with the cumulative addition result and a device for computing the nonlinear functions.On inputs such neuroprocessor served the input vector and the vector of weighting coefficients. In each step of neuroprocessor performs a weighted summation of several input to a single neuron by calculating the scalar product of the input vector by a vector of weights. Neuroprocessor supports the processing of vectors, the width of individual components which can be programmatically selected from a number of fixed values. With decreasing the capacity of the individual input data and the weights increase their number in each vector, and thereby increases the performance of neuroprocessor. However, the bit width of the obtained results is fixed and is determined by the capacity of the hardware nodes neuroprocessor.Thus, the main disadvantage of neuroprocessor is the lack of ability to programmatically change the bit width of output data, which in turn leads to hardware redundancy and relatively low productivity of neuroprocessor when emulation fragments of neural networks with small values of the input data and / or weights.Known digital devices, the analysis of characters the error correction block, two group elements And group elements OR. Such a device allows for 2N clock cycles to compute a function of saturation for a vector of N input operands.The disadvantages of the known devices limit the number modulo are low productivity and large hardware costs.The closest in technical essence to the second invention is a device for computing functions of saturation [4], which contains a multiplexer, a comparator, and two indicator saturation. Such a device allows for N clock cycles to compute a function of saturation for a vector of N input operands.The disadvantage of this device for calculating functions of saturation is poor performance when processing multiple operands with small values.Known computing device [2], which contains the multipliers, adders, registers, the multiplexer and the memory block store type. This device allows for one clock cycle to compute the scalar product of two vectors, each of which contains M operands, and for N clock cycles to perform the multiplication of a matrix containing the N x M operands to the vector consisting of M operands.The disadvantages of the known its closest to the technical essence to the third invention is a computing device [5], contains 3N/2 logical elements And N/2 decoders bits of the multiplier according to booth's algorithm, matrix multiplication of N columns by N/2 cells, each of which consists of the generation of partial discharge work of booth's algorithm and a single-bit adder, 2N-bit adder, N/2 multiplexers, N/2 additional circuits forming the partial discharge of the work of booth's algorithm and N/2 logic elements implication. This device allows for one step to multiply two N-bit operands or multiply two vectors element-by-element, each of which contains two (N/2)-bit operand.A disadvantage of such a computing device is its limited functionality, not allowing to perform the matrix multiplication of the operands on vector operands.A device for adding vectors of operands programmable bit [6] containing the adders and logic gates BAN.The disadvantages of the known devices are low performance, due to the serial signal transfer between adders, and limited functionality.The closest technodom his discharge - a half-adder and the logical EXCLUSIVE OR element. This adder allows for N clock cycles to perform addition of two vectors consisting of N operands each.The disadvantage of this adder is the low productivity is the sum of data vectors.Technical result achieved in the first invention is to improve the performance of neuroprocessor by providing the ability to programmatically change the bitness of the results.This technical result is achieved by the fact that in neuroprocessor, containing the first, second, and third registers, the first memory block of the store type and the multiplexer, the first information input of each of the discharge of which is connected to the output of the corresponding discharge of the first register, the information input of each of the discharge of the second register connected to the corresponding discharge the first input bus neuroprocessor, the control inputs of the first, second and third registers are the corresponding control inputs of neuroprocessor entered the fourth, fifth and sixth registers, shift register, the logic element And the second memory block store type switch with three dimensions in two, two devices for which barandov, the input bits of the second vector operand, the input bits of the third vector operands, the input limits setting data in the first vectors of operands and results, inputs installation boundaries of the data in the vectors of the second operand inputs of the installation boundaries of the data in the vectors of the third operand, the first and second control inputs of the loading vectors of the third operand in the first memory block, the control input shipment matrix third operands from the first memory block in the second memory block and outputs the bits of the first vector and second vector components of results of operations of vector addition of the first operand with the work of the second vector operand matrix third operands stored in the second memory block, moreover, the first information input of the discharge switch from three directions in the two information inputs of the first memory block store type, the first, third, and fourth registers and parallel information inputs shift register bitwise combined and connected to the corresponding bits of the first input bus neuroprocessor, each digit of the second input bus connected to the second information input of the corresponding discharge switch from three directions in two, the first output is the device for calculating functions of saturation, the control input of each of the discharge of which is connected to the output of the corresponding discharge of the second register, the second output of each of the discharge switch from three directions in the two connected to the input of the corresponding category of vector input operands of the second device to calculate a function of saturation, the control input of each of the discharge of which is connected to the output of the corresponding discharge of the third register, the output of each bit of a vector of results of the first device to calculate the saturation functions connected with the second information input of the corresponding discharge of the multiplexer, the output of each of the discharge of which is connected to the input of the corresponding discharge of the first vector operand of the computing device, the input of each of the discharge of the second vector operand which is connected to the output of the corresponding order of the vector of results of the second device to calculate a function of saturation, the information outputs of the first memory block store type connected to inputs of respective bits of the vector of the third operand of the computing device, the output of each bit of a vector of the first summand of the results of the addition operation of the first vector operand with the work of the second vector operandi discharge of the first vector components of the adder, the input of each bit of a vector of the second summand which is connected to the output of the corresponding rank vector of the second summand of the results of the addition operation of the first vector operand with the work of the second vector operand matrix third operands stored in the second memory block, computing devices, each input set of boundary data in the vectors of the first operands and the results of which is connected to the output of the corresponding discharge of the fifth register and the corresponding input set of boundary data in the vectors of the terms and amounts of the adder, the output of each bit of a vector of the sums of which is connected with the corresponding information input of the second memory block store type, each information output of which is connected to the corresponding bit of the output bus neuroprocessor and is connected to the third input of the corresponding discharge switch from three directions in two, the output of each of the discharge of the fourth register is connected to the information input of the corresponding discharge of the fifth register and the corresponding input set of boundary data in the vectors of the third operand of the computing device, each input set of boundary data in the vectors of the second operand which soy is dine with the output of the corresponding discharge shift register, serial data input and output of which are combined and connected to the first input control loading vectors third operands in the first block of memory of the computing device and to the first input element And the output of which is connected to the control input of the reading of the first memory block of the store, the second input element And the control input of the shift of the shift register and the second control input loading vectors third operands in the first block of memory of the computing device combined and connected to a corresponding control input of neuroprocessor, input relay control matrix third operands from the first memory block to the second block of memory of the computing device and the control inputs of the fifth and sixth registers are combined and connected to a corresponding control input of neuroprocessor control inputs switch from three directions in two, a multiplexer and a fourth register, the control inputs of the write shift register and the first memory block of the store type and the control inputs of the reading and writing of the second memory block store type are the corresponding control inputs of neuroprocessor, the output state of the first and second blockprints computing device, contains a shift register that performs in a single cycle arithmetic shift all of the operands stored in the N-bit vector by J bits to the left, where J is the minimum value which is a multiple of the word length of the data vectors of the second operand of the computing device, a delay element, the first memory block with the input port of the store type and containing N/J cells for storing N-bit data, a second memory block containing N/J cells for storing N-bit data, N/J multiplier units, each of which multiplies the N-bit vector data programmable bit on the J-bit multiplier, and the pattern of addition of vectors, forming a double row code amount N/J+1 vectors programmable data bit, and the input bits of the vector of the third operand of the computing device connected to the information inputs of the shift register, the outputs of which are connected to information inputs of the first memory block, the outputs of each cell which is connected to the information inputs of the corresponding cell of the second memory block, the outputs of each cell which is connected to the input bits of the vector mnimyh corresponding block multiplication, the input bits of the multiplier which is connected to the inputs of the Dogo block multiplication connected to inputs of bits of the corresponding vector components of the scheme of addition of vectors, the input bits (N/J+1)-th vector components which are connected to the inputs of the bits of the first vector operand of the computing device, inputs the installation boundaries data vectors third operands which are connected to corresponding inputs of the installation boundaries of the data in the vectors of operands of the shift register, the input of the mode of operation of which is connected to the first input control loading vectors third operands in the first block of memory of the computing device, the second control input loading vectors third operands in the first memory unit which is connected to the clock input of a shift register and the input of the delay element, the output of which is connected to the control input of the first memory block, the control input of the recording of the second memory block is connected to the input of the relay control matrix third operands from the first memory block to the second block of memory of the computing device, each input set of boundary data in the vectors of the second operand which is connected to the input of a significant correction of the corresponding block multiplication inputs installation boundaries of the data in the vectors of the first operands and results of computing devices connected to the inputs of the installation boundaries data vectors meitav scheme of addition of vectors, the outputs of the bits of the vectors of the first and second components results which are the respective outputs of the computing device.Technical result achieved in the first invention can be enhanced by reducing the duration of the processing cycle.The specified gain the technical result is achieved in that in the above-described neuroprocessor each device to calculate functions of saturation register contains the input data, information inputs, which are inputs of the corresponding bits of vector input operands of this device, the computing device includes an input data register, data inputs, which are inputs of the corresponding bits of the vectors of the first and second operands of the computing device, the adder includes an input data register, the information inputs of which are the corresponding inputs of the adder.Technical result achieved the second invention is to improve the device performance computing functions of saturation by providing the possibility of simultaneous processing of vector input operands programmable bit.Uke in each of the N bits of the first multiplexer, the second information input of which is connected to the input of the corresponding category of vector input operands of the device, the output of each bit of a vector of results which is connected to the output of the first multiplexer of the respective discharge devices, introduced the scheme of distribution of transfers and the formation scheme transfers, and each digit is entered the second multiplexer and the logical XOR, EQUIVALENCE, AND IS NOT a BAN, and direct input element PROHIBITION and the first input element and NOT the EQUIVALENCE of each of the discharge devices combined and connected to the corresponding control input device, the output of the element AND NOT the n-th discharge device is connected to the input distribution transfer through (N-n+1)-th digit shaping circuit transfers the output of the transfer (N-n+2)-th bit which is connected with the control input of the first multiplexer n-th digit of the device, the output element of the PROHIBITION of which is connected with the control input of the second multiplexer of the discharge device, the input generation migration (N-n+1)-m discharge shaping circuit breaks and negative input distribution transfer through (N-n+1)-th digit distribution scheme, the transfers, the carry-in input of the (N-n+1) th RA the NTA XOR and direct input element PROHIBITION of the q-th digit of the device are connected respectively to the second input of the EXCLUSIVE OR element and a negative input element PROHIBITION (q-1)-th digit of the device, the first information input of the second multiplexer which is connected to the output of the transfer in the (N-q+2)-th digit scheme of distribution of transfers (where q=2,3,...,N), inputs the initial transfers of the scheme of distribution of transfers and shaping circuit transfers the second input of the EXCLUSIVE OR element, an inverse input element PROHIBITION and the first information input of the second multiplexer of the N-th discharge devices combined and connected to the bus logic zero, and each discharge device, the output of the second multiplexer is connected to the second input element of the EQUIVALENCE, the output of which is connected to the first information input of the first multiplexer, the second information input of which is connected to the second information input of the second multiplexer and the first input of the EXCLUSIVE OR element, the output of which is connected with the second input element AND IS NOT the same discharge device.In special cases of application of the second invention, when subject to strict requirements to minimize hardware costs, the distribution of transfers the output of the transport in the q-th bit is connected to the carry-in input of the (q-1)-ro discharge (where q=2,3,...,N), and the circuit formation hyphenation contains N logical elements And and OR, each in the sign of the corresponding element, And the output of which is connected to the first input of the corresponding element OR the second input and the output of which is connected respectively to the input of the generation of the transfer in the corresponding discharge shaping circuit breaks and the output of the transfer in the same discharge shaping circuit transfers the second input of the first element is the input of the initial transfer shaping circuit transfers the second input of the q-th element And is connected to the output (q-1)-ro element OR (where q=2,3,...,N).Technical result achieved third invention consists in extending the functionality of the computing device.This technical result is achieved by the computing device, containing N/2 decoders digits of the multiplier and the matrix multiplication of N columns by N/2 cells, each of which consists of the generation of partial discharge works and one-bit adder, and the corresponding control inputs of the circuits forming the partial discharge works i-x cells of all columns of the matrix multiplication combined and connected to the corresponding outputs of the i-th decoder bits of the multiplier (where i= 1,2, . . . N/2), the first input of the one-bit adder of each cell Matricaria, entered N/2 BAN logic elements, the delay elements and N-bit shift register, each category consists of BAN logic element, a multiplexer and a trigger, and in each cell of the matrix multiplying the entered first and second triggers, functions of memory cells, respectively, the first and second blocks of memory devices, the logic element PROHIBITION and the multiplexer, the input of each of the discharge of the first vector operand of the device connected to the second input one-bit adder of the first cell of the corresponding column of matrix multiplication, the control inputs of multiplexers and inverted inputs of the elements of the PROHIBITION of all cells in each column which are United and connected to the corresponding input set of boundary data in the vectors of the first operands and results of the device, each input set of boundary data in the vectors of the second operand which is connected to the inverted input of the corresponding element of the BAN, the output of which is connected to the first input of the corresponding decoder bits of the multiplier, the second and third inputs of the i-th decoder bits of the multiplier are connected to the inputs respectively (2i-1) th and (2i)-th bits of the second vector operand device (where i=1,2,...,N/2), prod each bit of a vector third operands of the device connected to the second information input of the multiplexer corresponding discharge shift register, the first information input connected to the output element of the PROHIBITION of the discharge shift register, the first inverted input of which is connected to the corresponding input set of boundary data in the vectors of the third operand of the device, the second inverse input element PROHIBITION of the q-th bit shift register connected to the first negative input element PROHIBITION (q-1)-th digit shift register (where q=2,3,..., N), direct input element BAN r-th digit shift register connected to the output of the flip-flop (r-2)-th digit shift register (where r=3,4,...,N), the control inputs of multiplexers of all bits of the shift register combined and connected to the first input control loading vectors third operands in the first block of memory devices, input synchronization triggers all bits of the shift register and the input of the delay elements combined and connected to the second input control loading vectors third operands in the first block of the memory device, the output of each multiplexer discharge shift register is connected with the information input trigger of the discharge shift register, the output of which is connected to the information input of the first flip-flop of the last cell sootvetstvuetopredelennyj input of the first flip-flop (j-1)-th cell of the same column of the matrix multiplication (where j= 2,3, ...,N/2), the inputs of the first synchronization triggers all cells of the matrix multiplication combined and connected to the output of delay element that inputs the second synchronization triggers all cells of the matrix multiplication combined and connected to the input of the relay control matrix third operands from the first memory block to the second block of the memory device, the second information input of the differential formation of partial discharge works of the i-th cell of the q-th column of the matrix multiplication is connected with the output element of the PROHIBITION of the i-th cell (q-1)-th column of matrix multiplication (where i=1,2,...,N/2 and q=2,3,...,N), the second input of the one-bit adder of the j-th cell of each column of the matrix multiplication is connected to the output of the sum of one-bit adder (j-1)-th cell of the same column of the matrix multiplication (where j=2,3,...,N/2), the third input one-bit adder of the j-th cell of the q-th column of the matrix multiplication is connected to the output of the multiplexer (j-1)-th cell (q-1)-th column of matrix multiplication (where j=2,3, . . . N/2 and q=2,3,...,N), the third input one-bit adder of the j-th cell of the first column of the matrix multiplication is connected with the third output (j-1) th decoder bits of the multiplier (where j=2,3,...,N/2), the output amount of the one-bit adder of the last cell of each column of the matrix multiplication is output is cake (q-1)-th column of the matrix multiplication is the output of the q-th bit of the second vector components of the results of the device (where q= 2,3, ...,N), the first bit of the second vector components of results which is connected to the third output (N/2) th decoder digits of the multiplier, the second inverse and direct inputs of the element PROHIBITION of the first level and direct entry element PROHIBITION of the second discharge shift register, the second information inputs of the circuits forming the partial discharge works of all cells in the first column of matrix multiplication, the third single-bit inputs of the adders of the first cells of all columns of the matrix multiplication and the direct input of the first element PROHIBITION combined and connected to the bus logic zero, and in each cell of the matrix multiplying the output of the first flip-flop is connected to the information input of the second trigger, the output of which is connected to the direct input element PROHIBITION and the first information input of the differential formation of partial discharge works, the third control input of which is connected with the second information input of the multiplexer, the first information input connected to the output transfer one-bit adder of the same cell of the matrix multiplication.Technical result achieved the fourth invention is to improve the performance of the adder by the introduction of the performed technical result is achieved by in each category adder that contains the diagram of the formation of transfers, and in each of N of its digits is a half-adder and the logical EXCLUSIVE OR element, and the input of each bit of a vector of the first summand of the adder and the input of the corresponding discharge of the second vector components of adder connected respectively to first and second inputs of the half-adder corresponding discharge adder output sum of which is connected to the first input of the EXCLUSIVE OR element of the same category adder whose output is the output of the corresponding order of the vector sums of the adder, the second input of the EXCLUSIVE OR element of the q-th bit of the adder is connected to the output of the transfer in the q-th bit of shaping circuit transfers (where q= 2,3, . . .,N), the input of the initial transfer and the second input of the EXCLUSIVE OR element of the first digit of the adder connected to the bus logic zero, the entered first and second logical elements of the BAN, and the output amount of each digit half-adder adder is connected to the direct input of the first element PROHIBITION of the discharge of the adder, the output of which is connected to the input distribution transfer through appropriate discharge shaping circuit transfers the output of the transfer of the half-adder kotorogo connected to the input of the generation of the transfer in the corresponding discharge shaping circuit transfers inverted inputs of the first and second elements BAN each digit adder United and connected to the corresponding input set of boundary data in the vectors of the terms and amounts of the adder.In Fig. 1 shows a block diagram of neuroprocessor, Fig.2 - General view of the functions of saturation generated by the device to calculate functions of saturation, Fig.3 - model layer of a neural network, emulated neuroprocessors, Fig. 4 is a block diagram of a computing device of Fig.5 is a diagram of a device for computing functions of saturation data vectors programmable bit, Fig.6 is a diagram of the formation of transfers that can be used in the device for calculating functions of saturation, Fig.7 is a diagram of a computing device of Fig.8 - examples of circuit implementations of the decoder bits of the multiplier circuit and the formation of partial discharge work of booth's algorithm used in the computing device of Fig.9 is a diagram of the adder vectors programmable data width.Neuroprocessor, the block diagram of which is shown in Fig.1, contains the first 1, second 2, third 3, fourth 4 fifth 5th and sixth 6th registers, the shift register 7, the logical element And 8, the first 9 and second neusta computing functions of saturation, each of which has inputs bits of vector input operands 15 control inputs 16 and outputs the bits of the vector results 17, the computing device 18 with the input bits of the vector of the first 19, vector second 20 and third vector 21 of the operands, the input limits setting data in the first vectors of operands and results 22 in the second vectors of operands 23 and the third vectors of operands 24, the first 25 and second 26 inputs control loading vectors third operands in the first memory block, input relay control matrix third operands from the first memory block to the second memory unit 27 and outputs the bits of the vector of the first 28 and second vector 29 components of results of operations of vector addition of the first operand with the work of the second vector operand matrix third operands stored in the second memory unit, and the adder 30 with the input bits of the vector of the first 31 and second vector components 32, inputs installation boundaries of the data vectors in the terms and amounts 33 and outputs the bits of the vector sums to 34. Neuroprocessor has the first 35 and second 36 input bus and output bus 37. Control inputs 38 of the switch from three directions in the two 11, the control input 39 of the multiplexer 12, the control input 40 of the first register 1, operated 4, control input record 44 of the shift register 7, the control input record 45 of the first memory block store type 9, the control input record 46 and read 47 of the second memory block store type 10 and the above control inputs 26 and 27 of the computing device 18 are respective control inputs of neuroprocessor. Outputs condition 48 of the first memory block store type 9 and outputs status 49 of the second memory block store type 10 are outputs status neuroprocessor.The first information input of the discharge switch from three directions in the two 11, the information inputs of the first memory block store type 9, the first 1, second 2, third 3 and fourth 4 registers and parallel information inputs shift register 7 bitwise combined and connected to the first input bus 35 neuroprocessor, the bits of the second input bus 36 which is connected to the second information inputs of the respective bits of the switch from three directions in the two 11. The first outputs of the discharge switch from three directions in the two 11 connected to inputs of respective bits of vector input operands 15 of the first device to calculate functions of saturation 13, control whodis switch from three directions in the two 11 connected to inputs of respective bits of vector input operands 15 of the second device to calculate a function of saturation 14, the control inputs of 16 bits which are connected to the outputs of the respective bits of the third register 3. The outputs of the bits of the first register 1 is connected with the first information input of the respective bits of the multiplexer 12, the second information input bits which are connected to the outputs of the respective bits of the vector of results 17 the first device to calculate the saturation functions 13. The outputs of the bits of the multiplexer 12 is connected to the inputs of the respective bits of the first vector operand 19 computing device 18, the input bits of the second vector operand 20 which is connected to the outputs of the respective bits of the vector of results 17 the second device to calculate the saturation functions 14. Information outputs of the first memory block store type 9 connected to inputs of respective bits of the third vector operands 21 computing device 18, the output bits of the first vector components of results 28 which is connected to the inputs of the respective bits of the first vector of terms 31 of the adder 30, the input bits of the second vector components 32 which is connected to the outputs of the respective bits of the second vector components of results 29 the computing device is AMI respective bits of the fifth register 5 and the corresponding inputs of the installation boundaries of the data vectors in the terms and amounts 33 of the adder 30, the outputs of the bits of the vector sums 34 which are connected to the appropriate information inputs of the second memory block store type 10, the information outputs of which are connected to the corresponding bits of the output bus 37 neuroprocessor and is connected to the third inputs of the respective bits of the switch from three directions in the two 11. The outputs of the bits of the fourth register 4 is connected to information inputs of the respective bits of the fifth register 5 and the corresponding inputs of the installation boundaries of the data in the vectors of the third operand 24 computing device 18, the input setting borders data vectors of the second operands 23 which is connected to the outputs of the respective bits of the sixth register 6, the information input of which is connected to the outputs of the respective bits of the shift register 7, serial data input and output of which are combined and connected to the first input control loading vectors third operands in the first memory unit 25 of the computing device 18 and the first input element And 8, the output of which is connected to the control input of the reading of the first memory block store type 9. The control input of the shift of the shift register 7 is connected to a second input e is inogo device 18, input relay control matrix third operands from the first memory block in the second memory block 27 which is connected to control inputs of the fifth 5th and sixth 6th registers.Neuroprocessor works as follows.Executive nodes neuroprocessor are the first 13 and second 14 device for calculating functions of saturation, the computing device 18 and the adder 30. Each of these devices performs operations on vectors programmable data bit represented in two's complement.In each cycle of neuroprocessor computing device 18 generates the row ID of the operation of multiplication of a vector Y = (Y_{1}Y

_{2}.. . Y

_{k}), the bits which are fed to the inputs 20 of the computing device 18, the matrix

< / BR>

pre-loaded and stored in the second memory unit of the computing device 18 is added to the resulting product of the vector X = (X

_{1}X

_{2}... X

_{M}), the bits which are fed to the inputs 19 computing device 18. At the outputs 28 and 29 of the computing device 18 are formed in the discharge of vectors A = (A

_{1}A

_{2}... A

_{M}) and B = (B

_{1}B

_{2}... B

_{M}), seem

(m=1,2,...,M)

The vector X is an N-bit word, in which Packed M data presented in additional code and which elements of this vector. This low-order bits of the vector X are digits the first of this X

_{1}, followed by the digits of the second X

_{2}and so on, the most significant bit of the vector X are the bits of the M-th X

_{M}. When such packing - digit m-th this X

_{m}is

< / BR>

discharge of the vector X, where N

_{m}- bit m-th this X

_{m}of the vector X =1,2,...,N

_{m}, m=1,2,...,M. the Number M of data in the vector X and the number of bits of the N

_{m}in m-m given X

_{m}this vector can take any integer value from 1 to N, where m=1,2,...,M. the Only restriction is that the total width of all data is Packed into a single vector X must be equal to its capacity

< / BR>

The vector Y represents the N-bit word, in which Packed K data presented in additional code and which elements of this vector. The format of the vector Y is the same as the vector X. However, these vectors can vary the number and the capacity of individual data, Packed in these vectors. The minimum width J of each the calculating device 18. When implementing the algorithm of the partial products J is 1, when implementing a modified booth's algorithm J is 2. The number of digits N

^{}

_{k}in k-m this Y

_{k}the vector Y can take an integer value from J to N multiples of J, where k = 1,2,...,K. the Number of data K in the vector Y can take any integer value from 1 to N/J. However, the total width of all data is Packed into a single vector Y must be equal to its capacity

< / BR>

k-th row of the matrix Z represents the data vector Z

_{k}=(Z

_{k,1}Z

_{k,2}... Z

_{k,M}), where k= 1,2, ...,K. each of the vectors Z

_{1}, Z

_{2}, ..., Z

_{K}must have exactly the same format as the vector X.The vectors A and B are generated at the outputs 28 and 29 of the computing device 18, have exactly the same format as the vector X.Configuring the hardware of the computing device 18 to the processing of vectors required formats is carried out by loading the N-bit control word H in the fifth register 5, the outputs of which are connected to the inputs 22 of the computing device 18, and (N/J)-bit control word E in the sixth register 6, the outputs of which are connected to the inputs 23 of the computing device 18.The unit is each of the vectors X, Z

_{1}, Z

_{2}, ..., Z

_{K}as a senior (significant) digit of the corresponding element of the given vector. The number of unit bits in the word H is equal to the number of elements in each of the vectors X, Z

_{1}, Z

_{2}, ..., Z

_{K}< / BR>

< / BR>

A single value of the i-th digit of e

_{i}the words E means that the computing device 18 will consider the i-th J-bit group of bits of the vector Y, as a group of least significant bits of the corresponding element of the given vector. The number of unit bits in the word E is equal to the number of elements in the vector Y

< / BR>

Performing computing device 18 described above, the operation must precede the boot procedure of the matrix Z in the second block of memory of the computing device 18 and the control words H and E in the fifth 5th and sixth 6th registers, respectively. This procedure is performed in several stages.Initially in the first memory block store type 9 with the first input bus 35 neuroprocessor consistently recorded the vectors Z

_{1}, Z

_{2}, ..., Z

_{K}. Download the whole matrix Z in the first memory block store type 9 is performed for K CPU cycles, each of which input 45 neuroprocessor served active signal management account in which cessor loaded control word H, what input 43 neuroprocessor within a single clock cycle is served active signal, allowing the entry in the fourth register 4. In the next stage in the shift register 7 to the first input bus 35 neuroprocessor loaded control word E, which on input 44 neuroprocessor within a single clock cycle is served active signal, allowing the entry in the shift register 7.In the next N/J quanta matrix Z is sent from the first memory block store type 9 in the first block of memory of the computing device 18. In each of these N/J cycles per control input of neuroprocessor connected to the control input of the shift of the shift register 7, to one of the inputs of the element And 8 and the input 26 of the computing device 18, served active control signal. In each step of this signal initiates the shift the contents of shift register 7 for one digit to the right and, as a consequence, the issue on its serial output of the next digit of the control word E. the signal from the serial output shift register is fed to the control input 25 of the computing device 18 and to one of the inputs of the element And 8. When a single value of this signal at the output of the element And 8 is formed by an active signal, Pastukhova device 18 of the first memory block store type 9 enters one of the vectors Z

_{1}, Z

_{2}, . .., Z

_{K}that is written in the first memory unit of the computing device 18. The number of clock cycles required to load a single vector Z

_{k}depends on the bitness of N

^{}

_{k}operand Y

_{k}included in the vector Y, and is equal to N

^{}

_{k}/J (k= 1,2, ...,K). In the process of loading the matrix Z in the first block of memory of the computing device 18 control word H stored all this time in the fourth register 4, is fed to the input 24 of the computing device 18 to configure its hardware to accept vectors Z

_{1}, Z

_{2}, ..., Z

_{K}the required format. Since the signal from the serial output shift register 7 is supplied and its serial data input, and bit shift register 7 is equal to N/J, then at the end of the boot process of the matrix Z in the first block of memory of the computing device 18 of the shift register 7 will be the same information as before the beginning of the process, i.e. the control word eAfter that, the control input of neuroprocessor connected to the control input 27 of the computing device 18 and control inputs fifth 5th and sixth 6th registers, served an active signal. The result of this is sending word H is moved from the fourth register 4 in the fifth register 5, and control word E is overwritten by the shift register 7 in the sixth register 6.Starting with the next quantum computing device 18 will be in each step to perform the above operation

A + B = X + Y zThe adder 30 performs each step of addition of vectors A and B, arriving at its inputs 31 and 32 outputs 28 and 29 of the computing device 18. At the outputs 34 of the adder 30 is formed by a vector S = (S

_{1}S

_{2}... S

_{M}), the m-th element which is equal to the sum of the m-th elements of vectors A and B

S

_{m}= A

_{m}+ B

_{m},

where m=1,2,...,M

Moreover, the vector S will have the same format as the vectors A and B. configuring hardware adder 30 to the processing of vectors required formats are provided by feeding the inputs of the adder 33 30 control word H stored in the fifth register 5.Thus, the series connection of the computing device 18 and the adder 30 allows each step to perform the operation S = X + Y Z over vectors programmable data width. The results of this operation on different sets of vector input operands are written in the second memory block store type 10, performing the functions of battery promenade store type 10.Computing device 18 and the adder 30 can be used as single-ended switch K data, Packed in a single N-bit vector Y are fed to the inputs 20 of the computing device 18, M data, Packed in a single N-bit vector S is generated at the outputs 34 of the adder 30. This switching is performed by the operation S = X + Y Z, by which the inputs 19 computing device 18 is supplied to the vector X, all bits of which have zero values, and the second block of memory of the computing device 18 stores the matrix Z, which determines the rules of commutation. The matrix Z must satisfy the following requirements: item Z

_{k,m}located at the intersection of the k-th row and m-th column of the matrix Z must have a single value (00... 01)b, if you want the m-th element of S

_{m}vector S is equal to k-th element of Y

_{k}vector Y, or a value of zero (00. . . 00)b otherwise; the vector Z

_{k}representing the k-th row elements of the matrix Z must have the same format as the vector S; and each column of the matrix Z must not contain more than one element with a single value (k=1,2,...,K; m=1,2,...,M). The execution of the switching operation must precede described the work of the word E, identifies the format of the vector Y, the sixth register 6 and the matrix Z, which determines the rules of commutation, the second block of memory of the computing device 18.The operation S = X + Y Z is performed in a single cycle, while the process of loading the matrix Z in the first block of memory of the computing device 18 is at least N/J clock cycles. Therefore, efficient use of computing resources neuroprocessor is achieved only for batch processing of data vectors, for which support in the computing device 18 entered the second memory block, and the battery interim results 10 this is not the case, and dual-port block memory store type.For batch processing the set of vectors of the input operands supplied sequentially to each of the inputs 19 and 20 of the computing device 18, is divided into sequentially processed subsets (packages). The set of vectors of the input operands sequentially supplied to each of the inputs 19 and 20 of the computing device 18 and included in the package, can be represented as a vector of vectors of data

< / BR>

where T

_{}- the number of vectors included in each of the first package. Moreover, all vectors in the s during the processing of a single batch of vectors should not be measured.Processing-x package X

^{}

^{}and Y

^{}

^{}runs for T

_{}quanta. While in the t-th step of computing device 18 and the adder 30 performs the operation

S

^{}

^{t}=X

^{}

^{t}+Y

^{}

^{t}Z

^{}

^{}(t=1,2,...T

_{})

where Z

^{}

^{}- the contents of the second memory unit of the computing device 18, which in the process-x package X

^{}

^{}and Y

^{}

^{}should remain unchanged. The entire process-x package X

^{}

^{}and Y

^{}

^{}can be considered as the procedure of multiplying the data matrix the data matrix Z

^{}

^{}with the accumulation of results.Simultaneously with the processing of x packets of vectors is performed, the procedure described above serial load control word H

^{}

^{+1}defining the format of the vectors (+1)-th packet X

^{}

^{+1}in the fourth register 4, the control words E

^{}

^{+1}defining the format of the vectors (+1)-th packet Y

^{}

^{+1}in the shift register 7 and the forward matrix Z

^{}

^{+1}from the first memory block store type 9 in the first block of memory of the computing device 18. And loading new values into the fourth register 4 is required only when loading new values into the shift register 7 is only required in the case if the vectors (+1)-th packet Y

^{}

^{+1}differ in format from vectors on package Y

^{}

^{}. This procedure is no more than N/(J+2 clock cycles.At the end of both of these processes on the control input 27 neuroprocessor served active signal, initiating simultaneous shipment words H

^{}

^{+1}from the fourth register 4 in the fifth register 5, the words E

^{}

^{+1}of the shift register 7 in the sixth register 6, and the matrix Z

^{}

^{+1}from the first to the second block of memory of the computing device 18. All these forwarding are performed in a single cycle.The number of vectors T

_{}each m package can be set programmatically, but should not exceed a value of T

_{max}which is equal to the number of cells in the second memory block store type 10. On the other hand, it is impractical to use packages vectors with T

_{}less than N/J+2, as this will be idle computational tools neuroprocessor.Simultaneously with the forwarding of the matrix Z

^{}

^{+1}from the first memory block store type 9 in the first block of memory of the computing device 18 can be sequentially loaded with the first input bus 35 neuroprocessor the store type 9.Synchronization of all simultaneously occurring processes is done through the analysis of the status signals of the first 9 and second 10 memory blocks store the type issued to the outputs 48 and 49 of neuroprocessor, and supply control signals to corresponding inputs of neuroprocessor.The switch from three directions in the two 11 and the multiplexer 12 to form the switching system, thanks to which, as to the inputs of the first vector operand 19, and to the inputs of the second vector operand 20 computing device 18, can move the contents of the second memory block store type 10 or information on one of the input buses 35 or 36 neuroprocessor. In addition, the inputs 19 computing device 18 can move the contents of register 1, the pre-recorded it with the first input bus 35 neuroprocessor by filing an active signal on the control input 40 neuroprocessor. The choice of sources of information on the inputs 19 and 20 of the computing device 18, is performed by applying a certain combination of signals on the control inputs 38 and 39 of neuroprocessor. Moreover, if the information source is the second memory block store type 10, the control input 47 of neuroprocessor the data, applied to the inputs 19 and 20 of the computing device 18 of the second memory block store type 10 or one of the input buses 35 or 36 neuroprocessor pass through the device to calculate the saturation functions 13 and 14. Each of the devices 13 and 14 calculates for one step function of saturation from each element of the vector D = (D

_{1}D

_{2}... D

_{L}), arriving at the inputs 15 of this device.The vector D represents a N-bit word, in which the Packed L data presented in additional code and which elements of this vector. The format of the vector D is similar to the format described above vector X. However, these vectors can vary the number and the capacity of individual data, Packed in these vectors. Minimum data bit width, the components of the vector D is equal to two. The number of data L in the vector D can take any integer value from 1 to N/2. However, the total width of all data is Packed into a single vector D must be equal to its capacity

< / BR>

At the outputs 17 of the device to calculate the saturation functions 13 or 14 is formed by the vector F = (F

_{1}F

_{2}... F

_{L}), which has exactly the same format as the vector d And the-th element of F

_{}vecto the UB> - setting function of saturation, calculated for operand D

_{}(=1,2,...,L). General view of the functions of saturation, calculated by the devices 13 and 14, shown in Fig.2 and is described by the following expression:

_{Q}(D)=D, if -2

^{Q}D2

^{Q}- 1; Y

_{Q}(D) = 2

^{Q}- 1, if D>2

^{Q}- 1; Y

_{Q}(D) = -2

^{Q}if D<-2

.The number of significant bits in item F

Configuring hardware for each device to calculate the saturation functions 13 or 14 on the desired format of the vectors D and F, and the required parameter values of functions of saturation by filing an N-bit control word U on the control inputs 16 of this device.When this word digits U should have the following values: bits from the first to the (Q

< / BR>

must be zero, and the bits of c

< / BR>

a single value (=1,2,...,L).

If the value of n-th digit of a word U is ysenia 13 or 14 will consider the n-th bit of vector D, as a senior (significant) digit of the corresponding element of the given vector. The number of zero bits in the word U is the total number of significant bits in all elements of the vector result F

< / BR>

If U= (100...0)b, the information from the input device 15 to calculate the saturation functions 13 or 14 will be held at its outputs 17 no change (F=D).Control word the first device to calculate the saturation functions 13 is loaded with the first input bus 35 neuroprocessor in the second register 2, the outputs of which are connected with the control input device 16 to calculate the saturation functions 13. This loading is performed in a single cycle by filing an active signal on the control input 41 of the second case 2.Control word of the second device to calculate a function of saturation 14 is loaded with the first input bus 35 neuroprocessor in the third register 3, the outputs of which are connected with the control input device 16 to calculate the saturation functions 14. This loading is performed in a single cycle by filing an active signal on the control input 42 of the third register 3.Device for calculating saturation functions 13 and 14 are effective to prevent arythmia functions of saturation 13 or 14 can reduce only the number of significant digits in the elements of the processed data vector. The width of individual elements of the vector data and its format

remain unchanged. However, in some cases it is advisable to perform the calculation of the saturation functions for the elements of the vector data by reducing the bit depth of each element of the vector results by discarding all its high-order bits that are the extension of the significant digits of the given element. A reduction in the capacity of elements of the vector F = (F

If you are performing the above operations on conversion device 18 to apply the vector X = (X

< / BR>

the outputs 34 of the adder 30 is formed by the vector S = (S

< / BR>

where W

type 10 receives the vector of partial sums of G

G

which is recorded in the second memory block store type 10.When performing the first microoperation each procedure emulation group of neurons device for computing functions of saturation 13 can be used to restrict the values of the partial sums to exclude the possibility of arithmetic overflow in the weighted summation of the input data. In this case, the preparatory phase of microoperation should include load control word in the second register 2 with the first input bus 35 neuroprocessor.During the preparatory phase (+1)-th microoperation procedures emulation-th group of neurons consistently performs the following operations. With the first input bus 35 neuroprocessor in the third register 3 is loaded control word that defines the parameters of the functions of saturation, calculated for the second group of neurons. Then in the fourth register 4, the shift register 7 and the first block of memory of the computing device 18 is loaded control information, neophocaena each t-th quantum Executive phase (+1)-th microoperation procedures emulation-th group of neurons to the inputs 15 of the device to calculate the saturation functions 14 from the second memory block store type 10 receives the vector of partial sums of G

< / BR>

which is then fed to the inputs 20 of the computing device 18. Computing device 18 and the adder 30 exert compression vector R

< / BR>

which is loaded into the first memory block 52 computing device 18. Moreover, the i-th row of the matrix Z' represents a data vector Z

< / BR>

where l

From the above expression it follows that and so on, i.e. all rows of the matrix Z will be the Pris is performed using a shift register 50 for N/J clock cycles. In each of these N/J cycles per control input 26 of the computing device 18 is supplied to the synchronization signal, which is supplied to the clock input of shift register 50, and the inputs 24 of the computing device 18 is fed continuously above the N-bit control word H, which arrives at the inputs of the installation boundaries of the data in the vectors of operands of the shift register 50. In the i-th step (i=1,2,...,N/J) on the control input 25 of the computing device 18 is supplied to the i-th bit of e

P

The inputs 23 of the computing device 18 is fed a control word E, the j-th bit of e

< / BR>

By grouping the partial works relating to individual elements of the vector Y, the last expression can be represented in the following form

< / BR>

Considering the fact that every k-th element of the vector Y is equal to

< / BR>

the previous expression is converted as follows

< / BR>

Thus, at the outputs 28 and 29 of the computing device is formed by two-row result code of the operation X + Y-zIn General, the duration of the processing cycle neuroprocessor defined by total switching delay cascaded switch from three directions in the two 11, the device for calculating functions of saturation 14, the computing device 18 and the adder 30. Performance neuroprocessor can increase significantly if you use the device for calculation of the saturation functions 13 and 14 containing the registers of the input data, information inputs are connected to the inputs 15 of these devices, the computing device 18 containing the input data register, the information input of which is connected to the inputs 19 and 20 wydluzony to the inputs 31, 32 and 33 of the adder 30. The presence of such registers in the Executive nodes neuroprocessor allows data processing in pipelined mode, providing in each step of the parallel execution of three processes: the formation of the computing device 18 double row code of the weighted summation of the next set of input data, the addition at the adder 30 double row code of the weighted summation of the previous set of input data and computing devices 13 and 14 functions of saturation for the next set of input operands. Since the maximum delay switching device for calculating saturation functions 13 and 14, the computing device 18 and the adder 30 have approximately the same value, then the introduction of pipelined registers allows almost three times to increase the clock frequency neuroprocessor.Device for computing functions of saturation, which is shown in Fig. 5, has inputs bits of vector input operands 15 control inputs 16 and outputs the bits of the vector of results 17. Each of the N bits 56 this unit contains the first 57 and second 58 multiplexers, logic gates XOR 59, EQUIVALENCE 60, the transfer 64, inverted inputs distribution transfer through a separate discharge 65, the inputs of the transfer of the individual bits 66 and outputs transfer in single digits 67, and the formation scheme transfers 68 with the input of the initial transfer 69, inputs distribution transfer through a separate discharge 70, inputs generate transfer in single digits 71 and outputs transfer in single digits 72.The second information input of the first 57 and second 58 of the multiplexer and the first input of the EXCLUSIVE OR element 59 of each of the discharge device 56 combined and connected to the input of the corresponding category of vector input operands device 15, the output of each bit of a vector results 17 which is connected to the output of the first multiplexer 57 of the corresponding discharge device 56. Direct entry element PROHIBITION 62 and the first inputs of elements AND NOT 61 and the EQUIVALENCE of 60 each discharge device 56 combined and connected to the corresponding control input device 16. The first input of the EXCLUSIVE OR element 59 and direct input element PROHIBITION 62 q-th discharge device 56 are connected respectively to the second input of the EXCLUSIVE OR element 59 and the negative input element PROHIBITION 62 (q-1)-th digit 56 device, the first information input VV 63 (where q=2,3,. . . N). The output element AND 61 of the n-th discharge device 56 is connected to the input distribution transfer through (N-n+1)-th bit of 70 shaping circuit transfers 68, the output of transfer (N-n+2)-th bit of 72 which is connected with the control input of the first multiplexer 57 n-th discharge device 56, the output element PROHIBITION 62 which is connected with the control input of the second multiplexer 58 of the discharge device 56, the input generation migration (N-n+1)-m discharge 71 shaping circuit 68 transfers and negative input distribution transfer through (N-n+1)-th bit of a 65-distribution scheme transfers 63, the carry-in input of the (N-n+1)-th digit 66 which is connected to the output of the second multiplexer 58 of the n-th discharge device 56 (n=1,2,...N). Each discharge device 56, the output of the second multiplexer 58 is connected to the second input element of the EQUIVALENCE of 60, the output of which is connected to the first information input of the first multiplexer 57, and the output of the EXCLUSIVE OR element 59 is connected with the second input element AND NOT 61. The second input of the EXCLUSIVE OR element 59, an inverse input element PROHIBITION 62 and the first information input of the second multiplexer 58 of the N-th discharge device 56, the input initial transfer 64-distribution scheme transfers 63 and the input initial perekam 63 and 68 in the device to calculate the saturation functions can be used various schemes of distribution and formation of transfers, used in parallel adders.In the simplest variant distribution scheme 63 transfers the output of the transport in the q-th bit 67 is connected with the input of the transfer of the (q-1)-th digit 66 (where q= 2,3,...,N).In Fig. 6 shows a simple diagram of the formation of transfers that contains N logical elements And 73 OR 74. Each input distribution transfer through appropriate discharge 70 of the circuit connected to the first input of the corresponding element And 73, the output of which is connected to the first input of the corresponding element OR 74, the second input and the output of which is connected respectively to the input of the generation of the transfer in the appropriate category 71 and the output of the transfer in the same category 72 scheme. The second input of the first element And 73 is input initial transfer 69 scheme, and the second input of the q-th element And 73 is connected to the output (q-1)-ro element OR 74 (where q=2,3,...,N).The device for calculating saturation functions is as follows.The input device 15 serves bits of vector input operands D = (D

< / BR>

discharge of the vector D, where N

Minimum data bit width, the components of the vector D is equal to two. In the General case, the number of bits of the N

< / BR>

The device is intended for shaping the outputs 17 of the vector F = (F

< / BR>

where Q

< / BR>

must be zero, and the bits with

< / BR>

a single value (=1,2,...,L).

If the value of N-th digit of a word U is a unit (U

< / BR>

pre-loaded and stored in the second memory block device is added to the resulting product of the first vector operands X = (X

< / BR>

The vector X is an N-bit word, in which Packed M data presented in additional code and which elements of this vector. This low-order bits of the vector X are digits the first of this X

< / BR>

discharge of the vector X, where N

< / BR>

The vector Y represents the N-bit word, in which Packed K data presented in additional code and which elements of this vector. The format of the vector Y is the same as the vector X. However, these vectors can vary the number and the capacity of individual data, Packed in these vectors. The number of digits N

< / BR>

k-th row of the matrix Z represents the data vector Z

< / BR>

A single value of the i-th digit of e

< / BR>

Performing the above operations must be preceded by a boot procedure of the matrix Z in the second block of memory devices, the functions of the memory cells which perform the second triggers 82 cells of the matrix multiplication 77. This procedure is performed in two stages.Initially within N/2 cycles, the matrix Z is converted into the matrix

< / BR>

which is loaded into the first memory block of the device. Moreover, the i-th row of the matrix Z' represents a data vector Z

< / BR>

where l

< / BR>

From the above expression it follows that and so on, i.e. all rows of the matrix Z will be present in the matrix Z', but, as a rule, at other positions.The transformation matrix Z matrix Z' is performed using a shift register 50, which has two modes of operation. In boot mode on the control input 25 of the device is a single signal, and all multiplexers 79 shift register 50 begin to pass on the information inputs of the triggers shift register 80 50 discharges vector data supplied to the inputs 21 of the device. Mode shift control input 25 of the device is a null signal, and all multiplexers 79 shift register 50 begin to pass on the information inputs of the triggers shift register 80 50 information from outputs of the respective elements PROHIBITION 78 shift register ormala, stored in the trigger 80 (r-2)-th digit shift register 50, a h

Information from outputs of shift register 50 is supplied to the information input of the first unit memory device, which is implemented on the first trigger 81 cells of the matrix multiplication 77. The matrix N-by-N/2 triggers 81 forms the N parallel (N/2)-rich in composition of cells of one of the columns of the matrix multiplication 77. Therefore, the matrix triggers 81 can be considered as a block of memory with the input port of the store type and containing N/2 memory cells, each of which provides storage of N-bit words. The function of the i-th cell of the first memory block execute triggers 81 cells of the i-th row of the matrix multiplication 77 (i=1,2,...,N/2).The synchronization signal applied to the input 26 of the device in each step during the whole process of the transformation matrix Z matrix Z' passes through the delay element 51, which may be used a conventional inverter to the inputs of the first synchronization triggers 81 all cells of the matrix multiplication 77. Therefore, simultaneously with the transformation matrix Z matrix Z' will be booted from the matrix Z' in the first block of the memory device. At the end of the boot process in the first triggers 81 cells of the i-th row of the matrix multiplication 77 will contain the vector Z

After that, the control input 27 of the device during a single clock cycle is supplied to the synchronization signal, by which the contents of the first trigger 81 all cells of the matrix multiplication 77 overwritten in the second trigger 82 of the same cell of the matrix multiplication 77. The matrix N-by-N/2 triggers 82 may be considered as the second memory block containing ATI perform the second triggers 82 cells of the i-th row of the matrix multiplication 77 (i= 1,2,...,N/2). Thus, in one stage forward of the matrix Z' from the first to the second memory block devices.Starting from the next tact Executive nodes of a computing device to which the element belongs BAN 75, decoders bits of the multiplier 76, and was also included in the cells of the matrix multiplication 77 elements PROHIBITION 83, generation of partial discharge works 84, one-bit adders 85 and multiplexers 86, will be at each step to perform the above operation

A + B = X + Y zThus the i-th decoder bits of the multiplier 76, i-th element of the BAN 75, and was also included in the cells of the i-th row of the matrix multiplication 77 elements PROHIBITION 83 and circuit 84 are used to generate partial discharges works of the vector Z

P

All partial works are evaluated according to the modified booth's algorithm, according to which the values of the 2i-th and (2i-1)-th bits of the vector Y and the signal transfer c

In normal dvuhoborotnym the multipliers bout the quality of the signal transfer c

< / BR>

where y

< / BR>

These signals control schemes of formation of partial discharge works 84 cells of the i-th row of the matrix multiplication 77, on the first of informara Z

< / BR>

where is the n-th bit of the vector Z

The elements 90 and 91 and the element OR 92 included in the schemes of formation of partial discharge works 84 cells of the i-th row of the matrix multiplication 77, form an N-bit switch, the output of which is at one

< / BR>

where SUB~~1, sub~~

< / BR>

By grouping the partial works relating to individual elements of the vector Y, the last expression can be represented in the following form

< / BR>

Considering the fact that every k-th element of the vector Y is equal to

Computing device focused on batch processing of data vectors, in which the set of vectors of the input operands supplied sequentially to each of the inputs 19 and 20 of the device is divided into sequentially processed subsets (packages). The set of vectors of the input operands supplied to each of the inputs 19 and 20 of the device and included in the first package, can be represented as a vector of vectors of data

< / BR>

where T

A

where Z

< / BR>

discharge of the vector A, where N

< / BR>

The inputs of the adder 32 are bits of N-bit second vector components of B = (B

< / BR>

In the n-th digit adder 94 to the input of half-adder 95 serves the n-th digit and

p

The signals p

S

1. The main directions of developing the hardware implementation of neural network algorithms / Ivanov Y. P. and others (abstracts of the Second Russian conference "Neurocomputers and their application", Moscow, 14.02.1997) // Neurocomputer. - 1996. - N 1, 2. - S. 47-49.2. U.S. patent N 5278945, CL 395/27, 1994 (prototype 1 of the invention).3. USSR author's certificate N 690477, CL G 06 F 7/38, 1979.4. U.S. patent N 5644519, CL 364/736.02, 1997 (the prototype of the 2nd invention).5. U.S. patent N 4825401, CL 364/760, 1989 (prototype 3rd of the invention).6. U.S. patent N 5047975, CL 364/786, 1991.7. U.S. patent N 4675837, CL 364/788, 1987 (prototype 4-th of the invention). 1. Neuroprocessor, containing the first, second, and third registers, the first memory block store type and muda first register, information input each digit in a second register connected to the corresponding discharge the first input bus neuroprocessor, the control inputs of the first, second and third registers are the corresponding control inputs of neuroprocessor, characterized in that it introduced the fourth, fifth and sixth registers, shift register, the logic element And the second memory block store type switch with three dimensions in two, two devices for computing functions of saturation, the adder and the computing device having the input bits of the first vector operand, the input bits of the second vector operand, the input bits of the third vector operands, inputs installation boundaries of the data in the first vectors of operands and results, inputs installation boundaries of the data in the vectors of the second operand inputs of the installation boundaries of the data in the vectors of the third operand, the first and second control inputs of the loading vectors of the third operand in the first memory block, the control input shipment matrix third operands from the first memory block in the second memory block and outputs the bits of the first vector and second vector components of results of operations of vector addition of the first operand with the product of the vector of the second opearates switch from three directions in two, the information inputs of the first memory block store type, the first, third, and fourth registers and parallel information inputs shift register bitwise combined and connected to the corresponding bits of the first input bus neuroprocessor, each digit of the second input bus connected to the second information input of the corresponding discharge switch from three directions in two, the first output of each of the discharge of which is connected to the input of the corresponding category of vector input operands of the first device to calculate functions of saturation, the control input of each of the discharge of which is connected to the output of the corresponding discharge of the second register, the second output of each of the discharge switch from three directions in the two connected to the input of the corresponding category of vector input operands of the second device to calculate a function of saturation, the control input of each of the discharge of which is connected to the output of the corresponding discharge of the third register, the output of each bit of a vector of results of the first device to calculate the saturation functions connected with the second information input of the corresponding discharge of the multiplexer, the output of each of the discharge of which is connected as the second vector operand which is connected to the output of the corresponding order of the vector of results of the second device to calculate a function of saturation, information outputs of the first memory block store type connected to inputs of respective bits of the vector of the third operand of the computing device, the output of each bit of a vector of the first summand of the results of the addition operation of the first vector operand with the work of the second vector operand matrix third operands stored in the second memory block, which is connected to the input of the corresponding discharge of the first vector components of the adder, the input of each bit of a vector of the second summand which is connected to the output of the corresponding rank vector of the second summand of the results of the addition operation of the first vector operand with the work of the second vector operand matrix third operands stored in the second memory block, computing device, each input set of boundary data in the vectors of the first operands and the results of which is connected to the output of the corresponding discharge of the fifth register and the corresponding input set of boundary data in the vectors of the terms and amounts of the adder, the output of each bit of a vector of the sums of which is connected with the corresponding information input of the second memory block store type, each data output of which Pego discharge switch from three directions in two, the output of each of the discharge of the fourth register is connected to the information input of the corresponding discharge of the fifth register and the corresponding input set of boundary data in the vectors of the third operand of the computing device, each input set of boundary data in the vectors of the second operand which is connected to the output of the corresponding discharge of the sixth register, the information input of each of the discharge of which is connected to the output of the corresponding discharge shift register, serial data input and output of which are combined and connected to the first input control loading vectors third operands in the first block of memory of the computing device and to the first input element And the output of which is connected to the control input of the reading of the first memory block store type, the second input element And the control input of the shift of the shift register and the second control input loading vectors third operands in the first block of memory of the computing device combined and connected to a corresponding control input of neuroprocessor, the input to the relay control matrix third operands from the first memory block to the second block of memory of the computing device and inputs pravara, the control inputs of the switch from three directions in two, a multiplexer and a fourth register, the control inputs of the write shift register and the first memory block of the store type and the control inputs of the reading and writing of the second memory block store type are the corresponding control inputs of neuroprocessor, the output state of the first and second memory blocks store type are outputs status neuroprocessor.2. Neuroprocessor under item 1, wherein the computing device comprises a shift register that performs in a single cycle arithmetic shift all of the operands stored in the N-bit vector by J bits to the left, where J is the minimum value which is a multiple of the word length of the data vectors of the second operand of the computing device, a delay element, the first memory block with the input port of the store type and containing N/J cells for storing N-bit data, a second memory block containing N/J cells for storing N-bit data, N/J multiplier units, each of which multiplies the N-bit vector data programmable bit on the J-bit multiplier, and the pattern of addition of vectors, forming a double row code amount N/J + 1 vectors of data is clucene to the information inputs shift register, the outputs of which are connected to information inputs of the first memory block, the outputs of each cell which is connected to the information inputs of the corresponding cell of the second memory block, the outputs of each cell which is connected to the input bits of the vector mnimyh corresponding block multiplication, the input bits of the multiplier which is connected to the inputs of the corresponding J-bit group of bits of the second vector operand of the computing device, the outputs of each block multiplication connected to inputs of bits of the corresponding vector components of the scheme of addition of vectors, the input bits (N/J + 1)-th vector components which are connected to the inputs of the bits of the first vector operand of the computing device, inputs installation boundaries data vectors third operands which are connected to corresponding inputs of the installation boundaries of the data in the vectors of operands of the shift register, the input of the mode of operation of which is connected to the first input control loading vectors third operands in the first block of memory of the computing device, the second control input loading vectors third operands in the first memory unit which is connected to the clock input of a shift register and the input of the element sarago memory block connected to the input of the relay control matrix third operands from the first memory block to the second block of memory of the computing device, each input set of boundary data in the vectors of the second operand which is connected to the input of a significant correction of the corresponding block multiplication inputs installation boundaries of the data in the vectors of the first operands and results of computing devices connected to the inputs of the installation boundaries data vectors mnimyh and results of each block multiplication, and to the inputs of the installation boundaries of the data in the vectors of the terms and results of the scheme of addition of vectors, the outputs of the bits of the vectors of the first and second components results which are the respective outputs of the computing device.3. Neuroprocessor under item 1, characterized in that each of the devices for computing functions of saturation register contains the input data, information inputs, which are inputs of the corresponding bits of vector input operands of this device, the computing device includes an input data register, data inputs, which are inputs of the corresponding bits of the vectors of the first and second operands of the computing device, the adder includes an input data register, the information inputs of which are the corresponding inputs of the adder.4. Device for wiod which is connected to the input of the corresponding category of vector input operands of the device, the output of each bit of a vector of results which is connected to the output of the first multiplexer corresponding discharge device, characterized in that it introduced the scheme of distribution of transfers and the formation scheme transfers, and each digit is entered the second multiplexer and the logical XOR, EQUIVALENCE, AND IS NOT a BAN, and direct input element PROHIBITION and the first input element and NOT the EQUIVALENCE of each of the discharge devices combined and connected to the corresponding control input device, the output of the element AND NOT the n-th discharge device is connected to the input distribution transfer through (N - n + 1)-th digit shaping circuit transfers the output of the transfer (N - n + 2)-th bit which is connected with the control input of the first multiplexer n-th digit of the device, the output element of the PROHIBITION of which is connected with the control input of the second multiplexer of the discharge device, the input generation migration (N - n + 1)-m discharge circuit forming transfers and negative input distribution transfer through (N - n + 1)-th digit distribution scheme, the transfers, the carry-in input of the (N - n + 1)-th digit of which is connected to the output of the second multiplexer n-th digit of the device (inany respectively with the second input of the EXCLUSIVE OR element and a negative input element PROHIBITION (q - 1)-th digit of the device, the first information input of the second multiplexer which is connected to the output of the transfer in the (N - q + 2)-th digit scheme of distribution of transfers (where q = 2, 3, ..., N), inputs the initial transfers of the scheme of distribution of transfers and shaping circuit transfers the second input of the EXCLUSIVE OR element, an inverse input element PROHIBITION and the first information input of the second multiplexer of the N-th discharge devices combined and connected to the bus logic zero, and each discharge device, the output of the second multiplexer is connected to a second input of element EQUIVALENCE, the output of which is connected to the first information input of the first multiplexer, the second information input of which is connected to the second information input of the second multiplexer and the first input of the EXCLUSIVE OR element, the output of which is connected with the second input element AND IS NOT the same discharge device.5. The device according to p. 4, characterized in that the diffusion scheme transfers the output of the transport in the q-th bit is connected to the carry-in input of the (q - 1)-th bit (where q = 2, 3, ..., N).6. The device according to p. 4, characterized in that the circuit formation hyphenation contains N logical elements And and OR, and each is about element And, the output of which is connected to the first input of the corresponding element OR the second input and the output of which is connected respectively to the input of the generation of the transfer in the corresponding discharge circuit and the output of the transfer in the same discharge circuit, the second input of the first element is the input of the initial transfer circuit, the second input of the q-th element And is connected to the output (q - 1)-th element OR (where q = 2, 3, ..., N).7. Computing device containing N/2 decoders digits of the multiplier and the matrix multiplication of N columns by N/2 cells, each of which consists of the generation of partial discharge works and one-bit adder, and the corresponding control inputs of the circuits forming the partial discharge works i-x cells of all columns of the matrix multiplication combined and connected to the corresponding outputs of the i-th decoder bits of the multiplier (where i = 1, 2, ..., N/2), the first input of the one-bit adder of each cell of the matrix multiplication is connected to the output of the circuit forming partial discharge works the same cell of the matrix multiplication, characterized in that it introduced N/2 BAN logic elements, the delay elements and N-bit shift register, each category consists of logs is Oh triggers, performs the functions of the memory cells, respectively, the first and second blocks of memory devices, the logic element PROHIBITION and the multiplexer, the input of each of the discharge of the first vector operand of the device connected to the second input one-bit adder of the first cell of the corresponding column of the matrix multiplication, the control inputs of multiplexers and inverted inputs of the elements of the PROHIBITION of all cells in each column which are United and connected to the corresponding input set of boundary data in the vectors of the first operands and results of the device, each input set of boundary data in the vectors of the second operand which is connected to the inverted input of the corresponding element of the BAN, the output of which is connected to the first input of the corresponding decoder bits of the multiplier, the second and third inputs of the i-th decoder bits of the multiplier are connected to the inputs respectively (2i - 1)-th and 2i-th bit of the second vector operand device (where j = 2, 3, ..., N/2), direct input of the j-th element of the BAN is connected with the third input (j - 1) th decoder bits of the multiplier (where j = 2, 3, ..., N/2), the input of each bit of a vector third operands of the device connected to the second information input of the multiplexer corresponding a discharge shift register, the first inverted input of which is connected to the corresponding input set of boundary data in the vectors of the third operand of the device, the second inverse input element PROHIBITION of the q-th bit shift register connected to the first negative input element PROHIBITION (q - 1)-th digit shift register (where q = 2, 3, ..., N), direct input element BAN r-th digit shift register connected to the output of the flip-flop (r - 2)-th digit shift register (where r = 3, 4, ..., N), the control inputs of multiplexers of all bits of the shift register combined and connected to the first input control loading vectors third operands in the first block of memory devices, input synchronization triggers all bits of the shift register and the input of the delay elements combined and connected to the second input control loading vectors third operands in the first block of the memory device, the output of each multiplexer discharge shift register is connected with the information input trigger of the discharge shift register, the output of which is connected to the information input of the first flip-flop of the last cell of the corresponding column of matrix multiplication, the output of the first flip-flop the j-th cell of each column of the matrix multiplying soedinevol first synchronization triggers all cells of the matrix multiplication combined and connected to the output of the delay element, the inputs of the second synchronization triggers all cells of the matrix multiplication combined and connected to the input of the relay control matrix third operands from the first memory block to the second block of the memory device, the second information input of the differential formation of partial discharge works of the i-th cell of the q-th column of the matrix multiplication is connected with the output element of the PROHIBITION of the i-th cell (q - 1)-th column of matrix multiplication (where i = 1, 2, ..., N/2 and q = 2, 3, ..., N), second input of the one-bit adder of the j-th cell of each column of the matrix multiplication is connected to the output of the sum of one-bit adder (j - 1)-th cell of the same column of the matrix multiplication (where j = 2, 3, ..., N/2), the third input one-bit adder of the j-th cell of the q-th column of the matrix multiplication is connected to the output of the multiplexer (j - 1)-th cell (q - 1-)th column of the matrix multiplication (where j = 2, 3, ..., N/2 and q = 2, 3, ..., N), the third input one-bit adder of the j-th cell of the first column of the matrix multiplication is connected with the third output (j - 1) th decoder bits of the multiplier where (j = 2, 3, ..., N/2), the output amount of the one-bit adder of the last cell of each column of the matrix multiplication is the output of the corresponding order of the vector components of the results of the device, the output multiplexer of the last mesh is istwa (where q = 2, 3, ..., N), the first bit of the second vector components of results which is connected to the third output (N/2) th decoder digits of the multiplier, the second inverse and direct inputs of the element PROHIBITION of the first level and direct entry element PROHIBITION of the second discharge shift register, the second information inputs of the circuits forming the partial discharge works of all cells in the first column of matrix multiplication, the third single-bit inputs of the adders of the first cells of all columns of the matrix multiplication and the direct input of the first element PROHIBITION combined and connected to the bus logic zero, and in each cell of the matrix multiplying the output of the first flip-flop is connected to the information input of the second trigger, the output of which is connected to the direct input element PROHIBITION and the first information input of the differential formation of partial discharge works, the third control input of which is connected with the second information input of the multiplexer, the first information input connected to the output transfer one-bit adder of the same cell of the matrix multiplication.8. The adder containing formation transfers, and each of N of its digits is a half-adder and the logical EXCLUSIVE OR element, and the input of each PAA connected respectively to first and second inputs of the half-adder corresponding digit adder, output the sum of which is connected to the first input of the EXCLUSIVE OR element of the same category adder whose output is the output of the corresponding order of the vector sums of the adder, the second input of the EXCLUSIVE OR element or q-th bit of the adder is connected to the output of the transfer in the q-th bit of shaping circuit transfers (where q = 2, 3, ..., N), the input of the initial transfer and the second input of the EXCLUSIVE OR element of the first digit of the adder connected to the bus logic zero, characterized in that each digit is entered the first and second logical elements PROHIBITION, the sum of each digit half-adder adder is connected to the direct input of the first element PROHIBITION of the discharge of the adder, the output of which is connected to the input distribution transfer through appropriate discharge shaping circuit transfers the output of the transfer of each digit half-adder adder is connected to the direct input of the second element of the PROHIBITION of the discharge of the adder, the output of which is connected to the input of the generation of the transfer in the appropriate category of schemes for the formation of hyphens, inverted inputs of the first and second elements BAN each digit adder United and connected to the appropriate input set is

_{}vector F excluding significant discharge is equal to the value of Q_{}(=1,2,...,L). Obviously, the value of Q_{}must be less than the bit operands D_{}and F_{}.Configuring hardware for each device to calculate the saturation functions 13 or 14 on the desired format of the vectors D and F, and the required parameter values of functions of saturation by filing an N-bit control word U on the control inputs 16 of this device.When this word digits U should have the following values: bits from the first to the (Q

_{1})-th zero, the discharge (Q_{1}+1) th to - single digits with a zero, bit c unit, etc., In the General case, the bits of a word U with< / BR>

must be zero, and the bits of c

< / BR>

a single value (=1,2,...,L).

If the value of n-th digit of a word U is ysenia 13 or 14 will consider the n-th bit of vector D, as a senior (significant) digit of the corresponding element of the given vector. The number of zero bits in the word U is the total number of significant bits in all elements of the vector result F

< / BR>

If U= (100...0)b, the information from the input device 15 to calculate the saturation functions 13 or 14 will be held at its outputs 17 no change (F=D).Control word the first device to calculate the saturation functions 13 is loaded with the first input bus 35 neuroprocessor in the second register 2, the outputs of which are connected with the control input device 16 to calculate the saturation functions 13. This loading is performed in a single cycle by filing an active signal on the control input 41 of the second case 2.Control word of the second device to calculate a function of saturation 14 is loaded with the first input bus 35 neuroprocessor in the third register 3, the outputs of which are connected with the control input device 16 to calculate the saturation functions 14. This loading is performed in a single cycle by filing an active signal on the control input 42 of the third register 3.Device for calculating saturation functions 13 and 14 are effective to prevent arythmia functions of saturation 13 or 14 can reduce only the number of significant digits in the elements of the processed data vector. The width of individual elements of the vector data and its format

remain unchanged. However, in some cases it is advisable to perform the calculation of the saturation functions for the elements of the vector data by reducing the bit depth of each element of the vector results by discarding all its high-order bits that are the extension of the significant digits of the given element. A reduction in the capacity of elements of the vector F = (F

_{1}F_{2}. . . F_{L}) formed at the outputs 17 of the device to calculate functions of saturation 14, and the associated repackaging of elements in the vector can be accomplished in one step by computing device 18 and the adder 30, the mode switch data with 2L directions in L+1. In the example below describes the conversion of the vector F to be generated at the outputs 34 of the adder 30, the vector S = (S_{1}S_{2}... S_{L+1}), whose th element of S_{}is a Q_{}+1 Junior (significant) digits-th element of F_{}vector F (=1,2,...,L), a (L+1)-th element of S_{L+1}located in the upper bits of the vector S, is equal to (00...0)b. The vector F generated at the outputs 17 of the device to calculate the saturation functions 14 can be represented wow first Y_{2-1}and the second Y_{2}the elements of the first pair of elements are respectively Q_{}+1 the Junior and senior ranks-th bit element F_{}vector F (=1,2,...,L). Mode switching data to the inputs 19 computing device 18 serves zero values, resulting in the outputs 34 of the adder 30 is formed in the result of the multiplication of the vector Y on the matrix Z is stored in the second memory unit of the computing device 18. This result will be a vector S of the required format, if in the fifth register 5 is stored control word H that defines the above-described format of the vector S, in the sixth register 6 - control word E that determines the above-described format of the vector Y, and the second block of memory of the computing device 18 matrix Z, containing L+1 elements in each of the 2L rows. Moreover, the matrix Z must satisfy the following requirements: the width of each element-th column of the matrix Z must be equal to Q_{}+1; item Z_{2-1,}located at the intersection of the (2-1)-th row and-th column of the matrix Z must have a single value (00... 01)b, and the remaining elements of the matrix Z - zero (00...00)b (=1,2,...,L).If you are performing the above operations on conversion device 18 to apply the vector X = (X

_{1}X_{2}... X_{M+1}), the first element of X_{1}which is equal to zero and has a width equal to< / BR>

the outputs 34 of the adder 30 is formed by the vector S = (S

_{1}S_{2}... S_{L+M}), whose th element of S_{}is a Q_{}+1 Junior (significant) digits-th element of F_{}vector F (=1,2,...,L), a (L+m)-th element is equal to (m+1)-th element of X_{m+1}vector X (m=1,2,...,M). Thus, neuroprocessor allows for one clock cycle to perform an operation on the computation of saturation functions over the elements of the input vector and packaging the results in another vector of the input data.The main purpose of neuroprocessor is the emulation of various neural networks. In Fig. 3 presents the model layer of a neural network, implemented by the proposed neuroprocessors. In the General case, a single layer neural network consists of neurons and has a neuron inputs. While th neuron performs a weighted summation of data C_{1}C_{2}, ... applied to the corresponding neural inputs, with the threshold bias V_{}this neuron< / BR>

where W

_{,}- weighting factor input in th neuron(=1,2,...,; =1,2,...,). Then th neuron computes a function of saturation from unwesen is shown in Fig.2. All input data, weights, thresholds and the results are presented in additional code.The specifics of the proposed neuroprocessor is that when using it the user can programmatically set the following parameters for the neural network: the number of layers, number of neurons and neural inputs in each layer, the data bit width of each neural input, bit width of each weighting coefficient, the bit width of the output value of each neuron, the parameter of a function of saturation for each neuron.One neuroprocessor allows you to emulate the neural network is virtually unlimited sizes. Emulation of neural network layer-by-layer (one layer per layer).Each layer of the neural network is divided into sequentially processed fragments. This splitting is carried out as follows. Many neural input layer is divided into groups of inputs such that the total data bit width applied to all inputs of each group of inputs was equal to the capacity of neuroprocessor N. Many of the neurons of the layer is divided into groups of neurons such that the total bit width of the weighted summation results vyronas network is split into segments of two types, with a different functional purpose. Each fragment of the first type performs a weighted summation of the data submitted for all neural inputs that are included in one group of inputs to all neurons included in one group of neurons. Each fragment of the second type generates output values for all neurons included in one group of neurons, by calculating a function of saturation results from the weighted summation of all input data.Fig.3 can be used to illustrate the above principle of partitioning layer of a neural network into fragments. For this purpose it is necessary to imagine that each block shown in Fig.3, performs operations on N-bit vector data, and to interpret, is shown in Fig. 3 indicate the following: C_{}the vector of input data supplied to the second group of neural inputs (=1,2,...,); V_{}the vector of threshold values of the second group of neurons (=1,2,...,); W_{,}matrix of weight coefficients of the input data supplied to the second group of neural inputs, in the second group of neurons(=1,2,...,; =1,2,...,); G_{}- vector results weighted summation of the input data in the second group of neurons (=1,2,...); R_{}the vector of output values , polnaya multiplication and addition, and each fragment of the second type corresponds to one unit of the computing functions of saturation.The whole process emulation layer neural network on the same neuroprocessor can be represented in the form of sequentially performed procedures, each of which emulates one group of neurons and consists of +1 sequentially performed microoperation, each of which emulates one portion of a layer of the neural network. And I microoperation this procedure emulates a fragment of the first type, performing a weighted summation of the data supplied to the second group of neural inputs, with the accumulation result (=1,2,...,). Last microoperation procedure emulates a fragment of a second type that performs a calculation function of saturation from the weighted sum data supplied to all neural inputs, a corresponding group of neurons.Each microoperation running in emulation layer neural network has a preparatory and execution phases. Data processing applied to neural inputs is carried out in batch mode - T sets the input data in each packet.During the preparatory phase of the first microoperation the 35 neuroprocessor in the first register 1 is loaded vector V_{}. With the first input bus 35 neuroprocessor in the fourth register 4 is loaded control word that specifies the format of the vector V_{}and all vectors of the partial sums generated as a result of executing each of the first microoperation (=1,2,...,). With the first input bus 35 neuroprocessor in the shift register 7 is loaded control word that specifies the format of vector data supplied to the first group of neural inputs. The matrix W_{1,}sent from the first memory block store type 9, where this matrix should be pre-loaded with the first input bus 35 neuroprocessor, in the first block of memory of the computing device 18.During each t-th beat of the Executive phase of the first microoperation procedures emulation-th group of neurons to the inputs of the first vector operand 19 computing device 18 of the first register 1 receives a vector V_{}and to the inputs of the second vector operand 20 computing device 18 with the second input bus 36 neuroprocessor arrives vector C^{t}_{1}representing the t-th set of input data supplied to the first group of neural input layer (t=1,2,...,T). This computing device 18 and the adder 30 form the vector of partial sunamachi store type 10. Moreover, since the procedures emulation of the second group of neurons, simultaneously with this operation in each step will be forwarding the contents of one of the cells of the second memory block store type 10 in the external memory via the output bus 37 neuroprocessor.During the preparatory phase-second microoperation procedures emulation-th group of neurons consistently performs the following operations. With the first input bus 35 neuroprocessor in the shift register 7 is loaded control word that specifies the format of vector data supplied to the second group of neural inputs. The matrix W_{,}sent from the first memory block store type 9, where this matrix should be pre-loaded with the first input bus 35 neuroprocessor, in the first block of memory of the computing device 18.During each t-th quantum Executive phase-th microoperation (=2,3,...) procedure emulation-th group of neurons to the inputs of the first vector operand 19 computing device 18 of the second memory block storetype 10 receives the vector of partial sums of G

^{t}_{}_{of -1}generated when executing the previous microoperation, and the inputs of the second vector operand 20 in alausi a t-th set of input data, supplied to the second group of neural input layer (t=1,2,...,T). This computing device 18 and the adder 30 form the vector of partial sumsG

^{t}_{}_{,}=G^{t}_{}_{of -1}W_{,},which is recorded in the second memory block store type 10.When performing the first microoperation each procedure emulation group of neurons device for computing functions of saturation 13 can be used to restrict the values of the partial sums to exclude the possibility of arithmetic overflow in the weighted summation of the input data. In this case, the preparatory phase of microoperation should include load control word in the second register 2 with the first input bus 35 neuroprocessor.During the preparatory phase (+1)-th microoperation procedures emulation-th group of neurons consistently performs the following operations. With the first input bus 35 neuroprocessor in the third register 3 is loaded control word that defines the parameters of the functions of saturation, calculated for the second group of neurons. Then in the fourth register 4, the shift register 7 and the first block of memory of the computing device 18 is loaded control information, neophocaena each t-th quantum Executive phase (+1)-th microoperation procedures emulation-th group of neurons to the inputs 15 of the device to calculate the saturation functions 14 from the second memory block store type 10 receives the vector of partial sums of G

^{t}_{}_{,}, resulting in the outputs 17 of the device to calculate the saturation functions 14 is formed vector< / BR>

which is then fed to the inputs 20 of the computing device 18. Computing device 18 and the adder 30 exert compression vector R

^{t}_{}by eliminating every element of all places, which is the extension of the sign bit. If the inputs 19 computing device 18 is not the zero vector, and the vector data with one of the input buses 35 or 36 neuroprocessor, the result of the compression of the vector R^{t}_{}will be Packed in this vector input. As such a vector of input data may be used in the result obtained in the t-th step of the Executive phase (+1)-th microoperation procedures emulation (-1)-th group of neurons and stored in the external memory. The result is written to the second memory block store type 10.When performing any microoperation in emulation of the slice layer of the neural network the transition from the preparatory phase to the Executive by filing an active signal on the control input 27 neuroprocessor within a single clock cycle before the first beat of the Executive phase. This is highlighted in the sixth register 6, and the contents of the first memory unit of the computing device 18 is sent to the second memory block.Consistent implementation of microoperation is neuroprocessor in pipelined mode, in which the Executive phase of the next microoperation is performed simultaneously with the preparation of the next microoperation. The number of clock cycles necessary to perform all operations preparatory phase microoperation, ranges from N/J N/J+4 depending on the number of control words are loaded into the registers neuroprocessor. The number of clock cycles necessary to perform the Executive phase of any microoperation, equal to the number of sets of input data T, which is set by the user. Thus, the minimum run time of microoperation is determined by the duration of the preparatory phase and of equal length N/J CPU cycles. The value of T is advisable to select equal to N/J, since at smaller values of T will stand for the Executive nodes neuroprocessor, and at large values of T increases the response time of neuroprocessor at the next set of data on the neural inputs that are not desirable in emulation of neural set is a (+1) fragments, for the T sets of input data is performed on the same neuroprocessor for (+1)T clock cycles, but not less than (+1)N/J clock cycles.A small layer neural network whose total bit width data supplied to all neural inputs, and the total bit width of the weighted summation results for all neurons do not exceed the capacity of neuroprocessor N each emulated by performing two microoperation. First microoperation emulates a weighted summation of all input to all neurons in the layer, and the second is the calculation of the saturation functions for all neurons of a layer.The presence neuroprocessor two input 35 and 36 and one output 37 of the tire allows you to create on its basis effectively operating a multiprocessor system. The system consists of a neuroprocessor, will perform the emulation layer of a neural network in times faster than one neuroprocessor. In the limiting case, each portion of each layer of a neural network can be emulated separate neuroprocessors.The main node neuroprocessor is a computing device 18. In Fig.4 shows a block diagram of one of the possible implementations of the computing device 18 to perform operations on vectors dannykh all operands stored N-bit vector by J bits to the left where J is the minimum value which is a multiple of the word length of the data vectors of the second operand of the computing device 18, a delay element 51, the first memory block 52 with the input port of the store type and containing N/J cells for storing N-bit data, the second memory block 53, containing N/J cells for storing N-bit data, N/J multiplier units 54, each of which multiplies the N-bit vector data programmable bit on the J-bit multiplier, and the pattern of addition of vectors 55, forming a double row code amount N/J+1 vectors programmable data width.The input bits of the third vector operands 21 computing device 18 is connected to information inputs of the shift register 50, the outputs of which are connected to information inputs of the first memory block 52, the outputs of each cell which is connected to the information inputs of the corresponding cell of the second memory block 53, the outputs of each cell which is connected to the input bits of the vector mnimyh corresponding block multiplication 54, the input bits of the multiplier which is connected to the inputs of the corresponding J-bit group of bits of the second vector operand 20 computing device 18. The outputs of each block AA is sragow (N/J+1)-th vector components which are connected to the inputs of the bits of the first vector operand 19 computing device 18, inputs installation boundaries of the data in the vectors of the third operand 24 which is connected to the corresponding inputs of the installation boundaries of the data in the vectors of operands of the shift register 50, the input of the mode of operation of which is connected to the first input control loading vectors third operands in the first memory unit 25 of the computing device 18, the second control input loading vectors third operands in the first memory block 26 which is connected to the clock input of shift register 50 and the input of the delay element 51, the output of which is connected to the control input of the first memory block 52. Control input recording the second memory unit 53 is connected to the input of the relay control matrix third operands from the first memory block in the second memory block 27 computing device 18, each input set of boundary data in the vectors of the second operands 23 which is connected to the input of a significant correction of the corresponding block multiplication 54. Inputs installation boundaries of the data in the vectors of the first operands and results 22 of the computing device 18 is connected to the inputs of the installation boundaries data vectors mnimyh and results of each block multiplication 54 and to the inputs of the installation boundaries of the data in the vector components and the results which are relevant outputs 28 and 29 of the computing device 18.Computing device 18 operates as follows.The download procedure of the matrix Z in the second memory block 53 computing device 18 is performed in two stages.Originally for N/J quanta matrix Z is converted into the matrix< / BR>

which is loaded into the first memory block 52 computing device 18. Moreover, the i-th row of the matrix Z' represents a data vector Z

^{}_{i}=(Z^{}_{i}_{,1}Z^{}_{i}_{,2}... Z^{}_{i}_{M}), which is subsequently multiplied by the i-th J-bit group of bits of the vector Y (i=1,2,..., N/J). All vectors Z^{}_{1}, Z^{}_{2},...,Z^{}_{N}_{/J}have exactly the same format as any of the vectors Z_{1}, Z_{2}, . .., Z_{K}. The transformation matrix Z matrix Z' is performed by replacing the k-th row of Z_{k}(k=1,2,...,K) of the matrix Z to the N^{}_{k}/J rows of the matrix Z', formed in accordance with the expression< / BR>

where l

_{k}- the total number of J-bit groups of bits k of the first operand vector Y, N^{}_{k}_{/}- the width of the k-th element of Y_{k}vector Y.< / BR>From the above expression it follows that and so on, i.e. all rows of the matrix Z will be the Pris is performed using a shift register 50 for N/J clock cycles. In each of these N/J cycles per control input 26 of the computing device 18 is supplied to the synchronization signal, which is supplied to the clock input of shift register 50, and the inputs 24 of the computing device 18 is fed continuously above the N-bit control word H, which arrives at the inputs of the installation boundaries of the data in the vectors of operands of the shift register 50. In the i-th step (i=1,2,...,N/J) on the control input 25 of the computing device 18 is supplied to the i-th bit of e

_{i}described above (N/J)-bit control word E. This signal is applied to the control input mode shift register 50.In (l_{k+1}+1)-th step (k= 1,2, . ..,K), when the input 25 of the computing device 18 is supplied to the discharge of the word E with a single value, the shift register 50 goes into download mode vector Z_{k}applied to the inputs 21 of the computing device 18. In each of the remaining N/J-K cycles when the input 25 of the computing device 18 is supplied to the discharge of the word E having a value of zero, the shift register 50 will perform an arithmetic shift by J bits to the left stored in the data vector.Thus, at the end of the i-th step (i=1,2,...,N/J) process transformation matrix Z matrix Z is admitted to the information inputs of the first memory block 52, with the input port of the store type.The synchronization signal applied to the input 26 of the computing device 18 in each step during the whole process of the transformation matrix Z matrix Z' passes through the delay element 51, which may be used in a conventional inverter, the input of the control record of the first memory block 52 computing device 18. Therefore, simultaneously with the transformation matrix Z matrix Z' will be booted from the matrix Z' in the first memory block 52 computing device 18. At the end of the boot process in the i-th cell of the first memory block 52 computing device 18 will contain the vector Z^{}_{i}(i=1,2,...,N/J).After that, the control input 27 of the computing device 18 within a single clock cycle is supplied to the synchronization signal, by which the contents of all cells of the first memory block 52 is moved into the corresponding cells of the second memory block 53 computing device 18. Thus, in one stage forward of the matrix Z' from the first 52 53 in the second block of memory of the computing device 18.Starting from the next tact Executive nodes of the computing device 18, which include blocks 54 and multiplication of the i-th block multiplication 54 serves to form a partial product of vector Z^{}_{i}stored in the i-th cell of the second memory block 53 computing device 18 to the i-th group of bits Y^{}_{i}vector Y applied to the input 20 of the computing device 18P

_{i}=Z^{}_{i}Y^{}_{i}.The inputs 23 of the computing device 18 is fed a control word E, the j-th bit of e

_{j}which is fed to the input of the iconic correction (j-1)-th block multiplication 54 (j=2,3,...,N/J). On the entrance sign correction (N/J)-th block multiplication 54 receives the low-order e_{1}control word e. Therefore, each block multiplication 54, to the inputs of the digits of the multiplier which is a group of high-order bits of one of the elements of the vector Y, will perform the multiplication in two's complement. Other N/J-K multiplier units 54 will operate in the direct code.Scheme of addition of vectors 55 forms a double row code sums the partial products P_{1}P_{2}, ..., P_{N/J}and the vector X applied to the input 19 of the computing device 18. This scheme can be built on the basis of adders with pending transfers.The inputs 22 of the computing device 18 is fed a control word H, which arrives at the inputs of the installation boundaries data vectors mnimyh each blogdom Executive host computing device 18 will be blocked distribution of transfers between discharges of these nodes, handle different elements of the input vectors.At the outputs of the circuit of addition of vectors 55 are formed vectors A and B, the sum of which is equal to< / BR>

By grouping the partial works relating to individual elements of the vector Y, the last expression can be represented in the following form

< / BR>

Considering the fact that every k-th element of the vector Y is equal to

< / BR>

the previous expression is converted as follows

< / BR>

Thus, at the outputs 28 and 29 of the computing device is formed by two-row result code of the operation X + Y-zIn General, the duration of the processing cycle neuroprocessor defined by total switching delay cascaded switch from three directions in the two 11, the device for calculating functions of saturation 14, the computing device 18 and the adder 30. Performance neuroprocessor can increase significantly if you use the device for calculation of the saturation functions 13 and 14 containing the registers of the input data, information inputs are connected to the inputs 15 of these devices, the computing device 18 containing the input data register, the information input of which is connected to the inputs 19 and 20 wydluzony to the inputs 31, 32 and 33 of the adder 30. The presence of such registers in the Executive nodes neuroprocessor allows data processing in pipelined mode, providing in each step of the parallel execution of three processes: the formation of the computing device 18 double row code of the weighted summation of the next set of input data, the addition at the adder 30 double row code of the weighted summation of the previous set of input data and computing devices 13 and 14 functions of saturation for the next set of input operands. Since the maximum delay switching device for calculating saturation functions 13 and 14, the computing device 18 and the adder 30 have approximately the same value, then the introduction of pipelined registers allows almost three times to increase the clock frequency neuroprocessor.Device for computing functions of saturation, which is shown in Fig. 5, has inputs bits of vector input operands 15 control inputs 16 and outputs the bits of the vector of results 17. Each of the N bits 56 this unit contains the first 57 and second 58 multiplexers, logic gates XOR 59, EQUIVALENCE 60, the transfer 64, inverted inputs distribution transfer through a separate discharge 65, the inputs of the transfer of the individual bits 66 and outputs transfer in single digits 67, and the formation scheme transfers 68 with the input of the initial transfer 69, inputs distribution transfer through a separate discharge 70, inputs generate transfer in single digits 71 and outputs transfer in single digits 72.The second information input of the first 57 and second 58 of the multiplexer and the first input of the EXCLUSIVE OR element 59 of each of the discharge device 56 combined and connected to the input of the corresponding category of vector input operands device 15, the output of each bit of a vector results 17 which is connected to the output of the first multiplexer 57 of the corresponding discharge device 56. Direct entry element PROHIBITION 62 and the first inputs of elements AND NOT 61 and the EQUIVALENCE of 60 each discharge device 56 combined and connected to the corresponding control input device 16. The first input of the EXCLUSIVE OR element 59 and direct input element PROHIBITION 62 q-th discharge device 56 are connected respectively to the second input of the EXCLUSIVE OR element 59 and the negative input element PROHIBITION 62 (q-1)-th digit 56 device, the first information input VV 63 (where q=2,3,. . . N). The output element AND 61 of the n-th discharge device 56 is connected to the input distribution transfer through (N-n+1)-th bit of 70 shaping circuit transfers 68, the output of transfer (N-n+2)-th bit of 72 which is connected with the control input of the first multiplexer 57 n-th discharge device 56, the output element PROHIBITION 62 which is connected with the control input of the second multiplexer 58 of the discharge device 56, the input generation migration (N-n+1)-m discharge 71 shaping circuit 68 transfers and negative input distribution transfer through (N-n+1)-th bit of a 65-distribution scheme transfers 63, the carry-in input of the (N-n+1)-th digit 66 which is connected to the output of the second multiplexer 58 of the n-th discharge device 56 (n=1,2,...N). Each discharge device 56, the output of the second multiplexer 58 is connected to the second input element of the EQUIVALENCE of 60, the output of which is connected to the first information input of the first multiplexer 57, and the output of the EXCLUSIVE OR element 59 is connected with the second input element AND NOT 61. The second input of the EXCLUSIVE OR element 59, an inverse input element PROHIBITION 62 and the first information input of the second multiplexer 58 of the N-th discharge device 56, the input initial transfer 64-distribution scheme transfers 63 and the input initial perekam 63 and 68 in the device to calculate the saturation functions can be used various schemes of distribution and formation of transfers, used in parallel adders.In the simplest variant distribution scheme 63 transfers the output of the transport in the q-th bit 67 is connected with the input of the transfer of the (q-1)-th digit 66 (where q= 2,3,...,N).In Fig. 6 shows a simple diagram of the formation of transfers that contains N logical elements And 73 OR 74. Each input distribution transfer through appropriate discharge 70 of the circuit connected to the first input of the corresponding element And 73, the output of which is connected to the first input of the corresponding element OR 74, the second input and the output of which is connected respectively to the input of the generation of the transfer in the appropriate category 71 and the output of the transfer in the same category 72 scheme. The second input of the first element And 73 is input initial transfer 69 scheme, and the second input of the q-th element And 73 is connected to the output (q-1)-ro element OR 74 (where q=2,3,...,N).The device for calculating saturation functions is as follows.The input device 15 serves bits of vector input operands D = (D

_{1}D_{2}... D_{L}). The vector D represents a N-bit word, in which the Packed L data presented in additional code and which elements of this vector. While Lam is 2 and so on, the most significant bit of the vector D are the digits L-th given D_{L}. When such packing grade th given D_{}is< / BR>

discharge of the vector D, where N

_{}- width-th given D_{}vector D =1,2,...,N_{}, =1,2,...,L.Minimum data bit width, the components of the vector D is equal to two. In the General case, the number of bits of the N

_{}in-m this D_{}vector D can take any integer value from 2 to N (=1,2,...,L), and the number of data L, Packed in this vector, from 1 to N/2. The only restriction is that the total width of all data is Packed into a single vector D must be equal to its capacity< / BR>

The device is intended for shaping the outputs 17 of the vector F = (F

_{1}F_{2}... F_{L}), -th element of F_{}which is the result of a calculation function of saturation from-th operand D_{/ }vector D< / BR>

where Q

_{}- setting function of saturation, calculated for operand D_{}(=1,2,...,L). General view of the functions of saturation, calculated by the device shown in Fig.2 and is described by the following expression:_{Q}(D)=D, if -2^{Q}D 2^{Q}-1;_{Q}(D)=2^{Q}-1, if D > 2^{Q}-1;_{Q}(D)=-2^{Q}if D < -2^{Q}.When this word digits U should have the following values: bits first to the Q_{1}th is zero, the discharge (Q_{1}+1)-th to N_{1}th - single, bits (N_{1}+1) th to (N_{1}+Q_{2})-th zero, bits (N_{1}+Q_{2}+1) th to (N_{1}+N_{2})-St - unit, etc., In the General case, the bits of the control word U with< / BR>

must be zero, and the bits with

< / BR>

a single value (=1,2,...,L).

If the value of N-th digit of a word U is a unit (U

_{n}=1) and the value (n+1)-th digit zero (U_{n+1}=0), the device will consider the n-th bit of vector D, as senior (significant) digit of the corresponding element of the given vector. The number of zero bits in the word U is the total number of significant bits in all elements of the vector of results F.Item BAN 62 of the n-th discharge device 56 generates a signal which is an indication of ect and below n=1,2,...,N). The second multiplexer 58 of the n-th discharge device 56 generates a signal which has a value of sign (senior) level of the input operand, the discharge of which is the n-th bit of d_{n}vector D.To accelerate the formation of the signals v_{n}for all 56 bits in the device is the distribution scheme transfers 63, which can be used any known sequential or bypass transfer used in conventional parallel adders. To apply the scheme of distribution of transfers 63 in the proposed device is characterized that as a signal input and output transfers are used, the signals v_{n}and as signals propagate transfer through a separate discharge - inverted values of the signals g_{n}. Moreover, the migration extends from the senior ranks of the device to the younger.The XOR 59 and NOT 61 of the n-th discharge device 56 are used to signal which is an indication that the value of n-th digit of d_{n}vector D does not exceed the threshold saturation installed word U to the input operand, the discharge of which is the n-th bit of d_{n}vector D.The FD scheme is n that is a sign that the values of all bits of the vector D, starting from the n-th digit of d_{n}and ending the discharge of the input operand, the discharge of which is the n-th bit of d_{n}vector D does not exceed the threshold saturation installed word U for this input operand. As circuit 68 may be used any known method of forming a consistent or group transfers used in conventional parallel adders. To apply shaping circuit 68 transfers in the proposed device is characterized that as a signal generation migration applied to the inputs 71, uses signals g_{n}as signals propagate transfer applied to the inputs 70, uses signals p_{n}and at the outputs of the transfer 72 are formed signals c_{n}. Moreover, the migration extends from the senior ranks of the device to the younger.Item EQUIVALENCE 60 and the first multiplexer 57 n-th discharge device 56 is formed of the n-th digit (f_{n}vector result F in accordance with the expression If c_{n}=1, then the output of the first multiplexer 57 is set to discharge d_{n}vector D; if (c_{n}=0 and u_{n}=1, in the on operand vector D; if c_{n}=0 and u_{n}= 0, then the output of the first multiplexer 57 is set to the inverse value of the sign digit of an operand vector d Obtained at the outputs of the first multiplexer 57 discharges vector results arrive at the outputs 17 of the device.It should be noted that if the inputs 16 of the device is a control word U=(100...0)b, the information input to the input device 15, will be held at its outputs 17 no change (F=D).Thus, the proposed device for computing functions of saturation has a switching delay approximately equal to the switching delay of conventional parallel adder of two N-bit numbers. This device allows you to simultaneously compute a function of saturation for multiple data bit width which can be programmed by the user.Computing device, the scheme of which is shown in Fig.7, has inputs bits of the vector of the first 19, vector second 20 and third vector 21 of the operands, the input limits setting data in the first vectors of operands and results 22 in the second vectors of operands 23 and third vectors of operands 24, the first 25 and second 26 inputs control loading ve the th block of memory to the second memory unit 27 and outputs the bits of the vectors of the first summand of 28 results and vectors of the second summand results 29. This device comprises a shift register 50, a delay element 51, N/2 logic elements PROHIBITION 75, N/2 decoders bits of the multiplier 76, matrix multiplication 77 of N columns by N/2 cells each. Each discharge shift register 50 contains the logical element PROHIBITION 78, the multiplexer 79 and the trigger 80. Each cell of the matrix multiplication 77 contains the first 81 and second 82 triggers, functions of memory cells, respectively, the first and second blocks of memory devices, the logic element PROHIBITION 83, a method of forming the partial discharge works 84, bit adder multiplexer 85 and 86. Moreover, in Fig.7 numbering of the columns of cells of the matrix multiplication 77 is made from right to left, and the numbering of the cells in the columns of cells of the matrix multiplication 77 from top to bottom.The input of each of the discharge of the first vector operand device 19 is connected to the second input single-bit adder 85 of the first cell of the corresponding column of the matrix multiplication 77, the first input single-bit adder 85 of each cell which is connected to the output of the circuit forming discharge partial pieces 84 of the same cell of the matrix multiplication 77, the control inputs of multiplexers 86 and inverted inputs of the elements of the PROHIBITION 83 all cells of each Stoianov and results 22 of the device. Each input set of boundary data in the vectors of the second operand device 23 is connected to the inverted input of the corresponding element of the BAN 75, the output of which is connected to the first input of the corresponding decoder bits of the multiplier 76. The respective control inputs of the circuits forming the partial discharge works 84 i-x cells of all columns of the matrix multiplication 77 combined and connected to the corresponding outputs of the i-th decoder bits of the multiplier 76, second and third inputs of which are connected to the inputs respectively (2i-1) th and (2i)-th bits of the second vector operand 20 devices (where i=1,2,...,N/2). Direct entry of the j-th element of the BAN 75 is connected to the third input of the (j-1) th decoder bits of the multiplier 76 (where j=2,3,..., N/2). The input of each bit of a vector third operands device 21 is connected to the second information input of the multiplexer 79 corresponding discharge shift register 50, the first information input connected to the output element PROHIBITION 78 the same level of shift register 50, the first inverted input of which is connected to the corresponding input set of boundary data in the vectors of the third operand device 24. The second inverse input element PROHIBITION 78 q-th bit shift reg). Direct entry element PROHIBITION 78 r-th digit shift register 50 is connected to the output of the trigger 80 (r-2)-th digit shift register 50 (where r= 3,4, . ..,N). The control inputs of multiplexers 79 all bits of the shift register 50 combined and connected to the first input control loading vectors third operands in the first memory unit 25 of the device. Inputs synchronization triggers 80 all bits of the shift register 50 and the input of the delay element 51 of the joint and connected to the second input control loading vectors third operands in the first block of the memory device 26. The output of multiplexer 79 each digit shift register 50 is connected to the information input of the trigger 80 the same level of shift register 50, the output of which is connected to the information input of the first flip-flop 81 the last cell of the corresponding column of the matrix multiplication 77. The output of the first flip-flop 81 j-th cell of each column of the matrix multiplication 77 is connected to the information input of the first flip-flop 81 (j-1)-th cell of the same column of the matrix multiplication 77 (where j=2,3,...,N/2). The inputs of the first synchronization triggers 81 all cells of the matrix multiplication 77 combined and connected to the output of the delay element 51. The inputs of the second synchronization triggers 82 all I had first memory block to the second block of the memory device 27. The second information input of the differential formation of partial discharge works 84 of the i-th cell of the q-th column of the matrix multiplication 77 is connected with the output element PROHIBITION 83 i-th cell (q-1)-th column of the matrix multiplication 77 (where i= 1,2,...,N/2 and q=2,3,...,N). Second input of the one-bit adder 85 j-th cell of each column of the matrix multiplication 77 is connected to the output sum bit adder 85 (j-1)-th cell of the same column of the matrix multiplication 77 (where j=2,3,...,N/2). The third input one-bit adder 85 j-th cell of the q-th column of the matrix multiplication 77 is connected to the output of multiplexer 86 (j-1)-th cell (q-1)-th column of the matrix multiplication 77 (where j=2,3,...,N/2 and q= 2,3, ...,N), and the third input one-bit adder 85 j-th cell of the first column of the matrix multiplication 77 is connected to the third output (j-1) th decoder bits of the multiplier 76 (where j=2,3,...,N/2).The output sum bit adder 85 the last cell of each column of the matrix multiplication 77 is the output of the corresponding discharge of the first vector components of results 28 of the device. The output of multiplexer 86 last cell (q-1)-th column of the matrix multiplication 77 is the output of the q-th bit of the second vector components of results 29 the device (where q=2,3,...,N), the first bit of the second vector components resuli input element PROHIBITION 78 of the first level and direct entry element PROHIBITION 78 of the second discharge shift register 50, the second information inputs of the circuits forming the partial discharge works 84 all cells in the first column of matrix multiplication 77, the third inputs of the single-digit adders 85 of the first cells of all columns of the matrix multiplication 77 and direct input of the first element PROHIBITION 75 combined and connected to the bus logic zero. In each cell of the matrix multiplication 77 the output of the first flip-flop 81 is connected to the information input of the second trigger 82, the output of which is connected to the direct input element PROHIBITION 83 and the first information input of the differential formation of partial discharge works 84, the third control input of which is connected with the second information input of the multiplexer 86, the first information input connected to the output transfer one-bit adder 85 of the same cell of the matrix multiplication 77.In Fig. 8 shows examples of circuit implementations of the decoder bits of the multiplier 76 and schema formation of partial discharge works 84 in accordance with the modified booth's algorithm. The decoder bits of the multiplier 76 contains a logical XOR 87, EQUIVALENCE 88 and OR NOT 89. The method of forming the partial discharge works 84 contains logic elements 90 and 91, And the ode of the multiplication of the second vector operand Y = (Y_{1}Y_{2}... Y_{k}), the bits which are fed to the inputs 20 of the device, the matrix third operands< / BR>

pre-loaded and stored in the second memory block device is added to the resulting product of the first vector operands X = (X

_{1}X_{2}... X_{M}), the bits which are fed to the inputs 19 of the device. Thus in each cycle of operation of the device at the outputs 28 and 29 are formed in the discharge of vectors A = (A_{1}A_{2}... A_{M}) and B = (B_{1}B_{2}... B_{M}), which sum is a result of the operation X + Y z the sum of the m-th elements of vectors A and B is defined by the expression< / BR>

The vector X is an N-bit word, in which Packed M data presented in additional code and which elements of this vector. This low-order bits of the vector X are digits the first of this X

_{1}, followed by the digits of the second X_{2}and so on, the most significant bit of the vector X are the bits of the M-th X_{M}. When such packing-th bit of the m-th X_{m}is< / BR>

discharge of the vector X, where N

_{m}- bit m-th this X_{m}of the vector X = 1,2, . ..,N_{m}, m=1,2,...,M. the Number of data M in the vector X and the number of razlagova N. The only restriction is that the total width of all data is Packed into a single vector X must be equal to its capacity< / BR>

The vector Y represents the N-bit word, in which Packed K data presented in additional code and which elements of this vector. The format of the vector Y is the same as the vector X. However, these vectors can vary the number and the capacity of individual data, Packed in these vectors. The number of digits N

^{}_{k}_{/}in k-m this Y_{k}(k=1,2,..., K) of the vector Y can take integer is an even value from 2 to N. the Number of data K in the vector Y can take any integer value from 1 to N/2. However, the total width of all data is Packed into a single vector Y must be equal to its capacity< / BR>

k-th row of the matrix Z represents the data vector Z

_{k}= (Z_{k,1}, Z_{k,2}. . . Z_{k,M}), where k=1,2,...,K. each of the vectors Z_{1}, Z_{2}, ..., Z_{K}must have exactly the same format as the vector X.The vectors A and B are generated at the outputs 28 and 29 of the device, have the same format as the vector X.Configuring hardware computing device, the moves installation boundaries of the data in the vectors of the first operands and results 22 of the device and (N/2)-bit control word E to the inputs of installation boundaries of the data in the vectors of the second operands 23.A single value of the n-th digit h_{n}words H means that the device will consider the n-th bit of each of the vectors X, Z_{1}, Z_{2}, ..., Z_{K}as the high order bit of the corresponding element of the given vector. The number of unit bits in the word H is equal to the number of elements in each of the vectors X, Z_{1}, Z_{2}, ..., Z_{K}< / BR>< / BR>

A single value of the i-th digit of e

_{i}the words E means that the device will consider the i-th pair of bits of the vector Y, as a group of least significant bits of the corresponding element of the given vector. The number of unit bits in the word E is equal to the number of elements in the vector Y< / BR>

Performing the above operations must be preceded by a boot procedure of the matrix Z in the second block of memory devices, the functions of the memory cells which perform the second triggers 82 cells of the matrix multiplication 77. This procedure is performed in two stages.Initially within N/2 cycles, the matrix Z is converted into the matrix

< / BR>

which is loaded into the first memory block of the device. Moreover, the i-th row of the matrix Z' represents a data vector Z

^{}_{i}=(Z^{}_{i}_{,1}Z^{}_{i}_{,2}... Z^{}_{i}_{M}), which is>SUB>N_{/2}have exactly the same format as any of the vectors Z_{1}, Z_{2}, ..., Z_{K}. The transformation matrix Z matrix Z' is performed by replacing the k-th row of Z_{k}(k=1,2,...,K) of the matrix Z to the N^{}_{k}/2 rows of the matrix Z', formed in accordance with the expression< / BR>

where l

_{k}- the total number of pairs of digits in k the first operand vector Y equal to< / BR>

From the above expression it follows that and so on, i.e. all rows of the matrix Z will be present in the matrix Z', but, as a rule, at other positions.The transformation matrix Z matrix Z' is performed using a shift register 50, which has two modes of operation. In boot mode on the control input 25 of the device is a single signal, and all multiplexers 79 shift register 50 begin to pass on the information inputs of the triggers shift register 80 50 discharges vector data supplied to the inputs 21 of the device. Mode shift control input 25 of the device is a null signal, and all multiplexers 79 shift register 50 begin to pass on the information inputs of the triggers shift register 80 50 information from outputs of the respective elements PROHIBITION 78 shift register ormala, stored in the trigger 80 (r-2)-th digit shift register 50, a h

_{r}- value of r-th digit of the N-bit control word H, which is applied to the input 24 of the device and sets the bounds of the data in the processed vectors. Elements PROHIBITION 78 prevent the dissemination of information between the bits of the shift register 50, which stores the bits of the various elements of vector data loaded in the shift register 50. Output elements PROHIBITION 78 the two low-order bits of the shift register continuously generates zero signals, because of their direct inputs connected to the bus logic zero. Thus, the shift register 50, which is in a mode shift, performs an arithmetic shift of the stored data vector on the two digits to the left, which is equivalent to multiplying the elements of this vector by four.The transformation matrix Z matrix Z' is N/2 clock cycles. In each of these N/2 clock cycles on the control input 26 of the device is the synchronization signal, which is fed to the inputs of the synchronization triggers 80 shift register 50, and the inputs of the installation boundaries of the data in the vectors of the third operand device 24 is fed continuously above the N-bit control word H, which is the act (i=1,2,..., N/2) at the control input 25 of the device is the i-th bit of e_{i}described above (N/2)-bit control word E, which when the operation X + Y Z at the end of the process of transformation, and loading of the matrix Z will be fed to the inputs 23 of the device.In (l_{k-1}+1)-th step (k=1,2,...,K), when the input 25 of the device is the category of words E, having a single value, the input device 21 receives the bits of the vector Z_{k}that will be written without changes to the triggers 80 shift register 50. In each of the remaining N/2-K cycles when the input 25 of the device is the category of words E having a value of zero, triggers 80 shift register 50 will be recorded increased four times the values of the elements of the vector data stored in the shift register 50.Thus, at the end of the i-th step (i=1,2,...,N/2) of the process of transformation matrix Z matrix Z' in triggers 80 shift register 50 will be stored vector Z^{}_{i}.Information from outputs of shift register 50 is supplied to the information input of the first unit memory device, which is implemented on the first trigger 81 cells of the matrix multiplication 77. The matrix N-by-N/2 triggers 81 forms the N parallel (N/2)-rich in composition of cells of one of the columns of the matrix multiplication 77. Therefore, the matrix triggers 81 can be considered as a block of memory with the input port of the store type and containing N/2 memory cells, each of which provides storage of N-bit words. The function of the i-th cell of the first memory block execute triggers 81 cells of the i-th row of the matrix multiplication 77 (i=1,2,...,N/2).The synchronization signal applied to the input 26 of the device in each step during the whole process of the transformation matrix Z matrix Z' passes through the delay element 51, which may be used a conventional inverter to the inputs of the first synchronization triggers 81 all cells of the matrix multiplication 77. Therefore, simultaneously with the transformation matrix Z matrix Z' will be booted from the matrix Z' in the first block of the memory device. At the end of the boot process in the first triggers 81 cells of the i-th row of the matrix multiplication 77 will contain the vector Z

^{}_{i}(i=1,2,...,N/2).After that, the control input 27 of the device during a single clock cycle is supplied to the synchronization signal, by which the contents of the first trigger 81 all cells of the matrix multiplication 77 overwritten in the second trigger 82 of the same cell of the matrix multiplication 77. The matrix N-by-N/2 triggers 82 may be considered as the second memory block containing ATI perform the second triggers 82 cells of the i-th row of the matrix multiplication 77 (i= 1,2,...,N/2). Thus, in one stage forward of the matrix Z' from the first to the second memory block devices.Starting from the next tact Executive nodes of a computing device to which the element belongs BAN 75, decoders bits of the multiplier 76, and was also included in the cells of the matrix multiplication 77 elements PROHIBITION 83, generation of partial discharge works 84, one-bit adders 85 and multiplexers 86, will be at each step to perform the above operation

A + B = X + Y zThus the i-th decoder bits of the multiplier 76, i-th element of the BAN 75, and was also included in the cells of the i-th row of the matrix multiplication 77 elements PROHIBITION 83 and circuit 84 are used to generate partial discharges works of the vector Z

^{}_{i}stored in the second triggers 82 cells of the i-th row of the matrix multiplication 77 and i-a couple of bits Y^{}_{i}vector Y (here and below i=1,2,...,N/2)P

_{i}=Z^{}_{i}Y^{}_{i}.All partial works are evaluated according to the modified booth's algorithm, according to which the values of the 2i-th and (2i-1)-th bits of the vector Y and the signal transfer c

_{i}from the neighbouring Junior pairs of digits of the multiplier to determine the value of the partial UB>=1, P_{i}=0; if y_{2i}=0, y_{2i-1}=0 and c_{i}= 1 or y_{2i}= 0, y_{2i-1}= 1 and c_{i}=0, then P_{i}=Z^{}_{i}; if y_{2i}=0, y_{2i-1}=1 and c_{i}=1, P_{i}=2Z^{}_{i}; if y_{2i}=1, y_{2i-1}=0 and c_{i}=0, then P_{i}=-2Z^{}_{i}; if y_{2i}=1, y_{2i-1}=0 and c_{i}or y_{2i}=1, y_{2i-1}=1 and c_{i}=0, then P_{i}=-Z^{}_{i}.In normal dvuhoborotnym the multipliers bout the quality of the signal transfer c

_{i}used (2i-2)-th digit of the multiplier. In the proposed device, where mnimum is a vector of operands programmable bit signal transfer with_{i}is formed at the output of the i-th element of the BAN 75 and is described by the following logical expression< / BR>

where y

_{2i-2}- (2i-2)-th bit of the vector Y, e_{i}- the i-th bit of the control word E. Applying elements PROHIBITION 75 allows you to block the distribution of transfers between pairs of digits of the vector Y, belonging to different elements in the vector.The outputs of the i-th decoder bits of the multiplier 76 is formed following signals< / BR>

These signals control schemes of formation of partial discharge works 84 cells of the i-th row of the matrix multiplication 77, on the first of informara Z

^{}_{i}and on the second information inputs from the outputs of the elements PROHIBITION 83 cells of the i-th row of the matrix multiplication 77 serves bits of the vector Element PROHIBITION 83 i-th cell of the n-th column of the matrix multiplication 77 generates (n+1)-th bit of the vector in accordance with expression< / BR>

where is the n-th bit of the vector Z

^{}_{i}stored in the trigger 82 of the i-th cell of the n-th column of the matrix multiplication 77, h_{n}- the n-th digit of the control word H (i= 1,2, . . . N/2 and n=1,2,...,N). From this expression it follows that the vector is equal to 2Z^{}_{i}has exactly the same format as the vector Z^{}_{i}.The elements 90 and 91 and the element OR 92 included in the schemes of formation of partial discharge works 84 cells of the i-th row of the matrix multiplication 77, form an N-bit switch, the output of which is at one

_{i}=1 and two_{i}=0 is the vector Z^{}_{i}when one_{i}=0 and two_{i}=1 is the vector with one_{i}=0 and two_{i}=0 - vector with zero values for all digits. Thus, the outputs of this switch is formed by a vector of P^{}_{i}that when sub_{i}=0 is equal to the vector of the partial products P_{i}and at sub_{i}=1 is equal to - P_{i}.The change of sign of each element of the vector P^{}_{i}required to obtain UB>iand adding one to each element of the inverse of the vector. The XOR 93 included in the schemes of formation of partial discharge works 84 cells of the i-th row of the matrix multiplication 77 function as inverters, controlled by the signal sub_{i}. If sub_{i}=0, the vector of P^{}_{i}passes through the XOR 93 on the outputs of the circuits forming the partial discharge works 84 cells of the i-th row of the matrix multiplication 77 unchanged. If sub_{i}=1 XOR 93 invert each rank of this vector. Thus, at the outputs of the circuits forming the partial discharge works 84 cells of the i-th row of the matrix multiplication 77 is formed of N-bit vector with exactly the same format as the vectors X,Z^{}_{1},Z^{}_{2},..., Z^{}_{N}_{/2}satisfying the expression< / BR>

where SUB

_{i}N-bit vector, m-th element of which is the N_{m}-bit operand (00...0 sub_{i}b, the least significant digit is equal sub_{i}and the remaining bits have values of zero.One-bit adders 85 and multiplexers 86 cells of the matrix multiplication are used for forming double row code amount vectors SUB_{1}, SUB_{2}, . . ., SUB_{2}, ..., sub

_{N/2}. If (q-1) the category of h

_{q-1}control word H is equal to zero, then the multiplexers 86 cells (q-1)-th column of the matrix multiplication 77 is passed to corresponding inputs of the single-digit adders 85 cells q-th column of the matrix multiplication 77 signals from the outputs of the transfer of one-bit adders 85 cells (q-1)-th column of the matrix multiplication 77 (q= 2,3, ...,N). If (q-1)-th bit of h

_{q-1}control word H is equal to one, then the multiplexers 86 cells (q-1)-th column of the matrix multiplication 77 is passed to corresponding inputs of the single-digit adders 85 cells q-th column of the matrix multiplication 77 signals sub

_{1}, sub

_{2},..., sub

_{N/2}from the outputs of the decoders of the digits of the multiplier 76 (q=2,3,...,N). As a result, the outputs 28 and 29 of the device are formed vectors A and B, the sum is equal to

< / BR>

By grouping the partial works relating to individual elements of the vector Y, the last expression can be represented in the following form

< / BR>

Considering the fact that every k-th element of the vector Y is equal to

< / BR>

where T

_{}- the number of vectors included in each of the first package. All of vectors included in the same package must have the same format, that is, the information supplied to control inputs 22 and 23 of the device should not change during the processing of a single batch of vectors.Processing-x package X^{}^{}and Y^{}^{}runs for T_{}quanta. In each t-th quantum computing device performs the operationA

^{}^{t}+B^{}^{t}=X^{}^{t}+Y^{}^{t}Z^{}^{}(t=1,2,...,T_{})where Z

^{}^{}- the contents of the second memory block devices, which in the process-x package X^{}^{}and Y^{}^{}should remain unchanged.Although the s Z^{}_{1}^{+1}, Z^{}_{2}^{+1},..., Z^{}_{K}^{+1}c inputs 21 of the device in the first memory block of the device. This procedure is performed for N/2 clock cycles.At the end of both of these processes on the control input 27 neuroprocessor served active signal initiating the shipment of the matrix Z^{}^{+1}from the first to the second block of memory devices. This forwarding is performed in a single cycle. After this, the operation moves to the processing procedures (+1)-x packages vectors X^{}^{+1}and Y^{}^{+1}and loading matrices Z^{}^{+2}.The number of vectors T_{}each m package can be set programmatically. Moreover, it is impractical to use packages vectors with T_{}less than N/J+2, as this will be idle computational tools neuroprocessor.The adder circuit which is shown in Fig.9, has inputs bits of the vector of the first 31 and second vector components 32, inputs installation boundaries of the data vectors in the terms and amounts 33 and outputs the bits of the vector sums to 34. Each of the N bits of the adder 94 contains a half-adder 95, logical EXCLUSIVE OR element 96, the first 97 and 98 second logical elements of a BAN. The composition of the adder I input bits of the second vector components of adder 32 is connected respectively to the first and second inputs of Polyommatus 95 bits of the adder 94. Inverted inputs of the first 97 and 98 second elements BAN each digit adder 94 United and connected to the corresponding input set of boundary data in the vectors of the terms and amounts adder 33. The outputs of XOR 96 94 discharges adder outputs are the bits of the vector sum adder 34. The output of the first element PROHIBITION 97 each digit adder 94 is connected to the input distribution transfer through appropriate discharge shaping circuit transfers 99, entry generation migration in each category which is connected to the output of the second element PROHIBITION 98 of the respective discharge adder 94. The second input of the EXCLUSIVE OR element 96 q-th digit adder 94 is connected to the output of the transfer in the q-th bit of shaping circuit transfers 99 (where q= 2,3,...,N), the input of the initial transfer and the second input of the EXCLUSIVE OR element 96 of the first discharge 94 adder connected to the bus logic zero. Each discharge 94 adder output sum of the half-adder 95 is connected to the first input of the EXCLUSIVE OR element 96 and the direct input of the first element PROHIBITION 97, and the output of the transfer of the half-adder 95 is connected to the direct input of the second element PROHIBITION 98.The adder operates as follows.On vleet an N-bit word, in which Packed M data presented in additional code and which elements of this vector. This low-order bits of the vector A are the digits of the first of this A_{1}, followed by the digits of the second given A_{2}and so on, the most significant bit of the vector A are the bits of the M-th this A_{M}. When such packing-th bit of the m-th this A_{m}is< / BR>

discharge of the vector A, where N

_{m}-bit m-th this A_{m}vector A, =1,2,...,N_{m}, m=1,2,...,M. the Number M of data in the vector A and the number of bits of the N_{m}in each m-m this A_{m}this vector can take any integer value from 1 to N (m=1,2,...,M). The only restriction is that the total width of all data is Packed into a single vector A should be equal to its capacity< / BR>

The inputs of the adder 32 are bits of N-bit second vector components of B = (B

_{1}B_{2}... B_{M}), which has exactly the same format as vector A.Configuring hardware adder for processing vectors required formats are provided by feeding on its inputs 33 N-bit control word H. thus a single value of the n-th digit h_{n}words H means that the vector adder. The number of unit bits in the word H is equal to the number of elements in each of the vectors A and B (here and below n=1,2,...,N)< / BR>

In the n-th digit adder 94 to the input of half-adder 95 serves the n-th digit and

_{n}vector A and the n-th bit of b_{n}vector B. the outputs of the sum and transfer of the half-adder 95 is formed auxiliary signals distribution p_{n}and generation g_{n}transfer for a given discharge adder 94p

_{n}=a_{n}b_{n}, g_{n}=a_{n}b_{n}.The signals p

_{n}and g_{n}come on direct inputs respectively of the first 97 and 98 second elements PROHIBITION on the inverse input of which is supplied to the n-th bit of h_{n}control word H. If n-th bits a_{n}and b_{n}vectors A and B are not significant digits of the individual elements of the data vectors, h_{n}= 0, and the signals p_{n}and g_{n}pass on the outputs of the elements PROHIBITION 97 and 98 without changes. If the n-th bits a_{n}and b_{n}vectors A and B are significant discharges of their elements, then h_{n}=1, and the outputs of the elements PROHIBITION 97 and 98 are set zero value signals. Thus, the elements of the PROHIBITION 97 and 98 serve to block signals of generation and distribution of transfers in the discharge 94 the crystals from the outputs of the elements PROHIBITION 97 and 98 are received at the inputs of distribution and generation hyphenation scheme 99, which serves to accelerate the formation of signal transfer in the individual bits of the adder. As circuit 99 may be used any known bypass scheme, group or gradual migration used in common dvuhoborotnym the adders. At the outputs of the circuit 99 generates signals hyphenation in a separate bit of the adder in accordance with the expression c_{n+1}=g_{n}p_{n}c_{n}. Therefore, if h_{n}= 1, p_{n}= g_{n}= 0, and circuit 99 will form the signal c_{n+1}= 0.The transfers signals generated by the circuit 99, proceed to the inputs of XOR 96 of the respective bits of the adder 94, the other input of which receives signals distribution of transfers from the outputs of the sum of Polyommatus 95. At the output of the EXCLUSIVE OR element 96 of each n-th digit adder 94 is formed, the signal s_{n}=p_{n}c_{n}. Thus the outputs of the adder 34 is formed by a vector S = (S_{1}S_{2}... S_{M}), each element of which is equal to the sum of the corresponding elements of vectors A and BS

_{m}= A_{m}+ B_{m}(m-1,2,...,M).Moreover, the vector S will have exactly the same format as the vectors A and B.In contrast to the known amatoriali adjacent operands input vectors, at the level of the formation of the auxiliary functions of generation and distribution of transfer. This allows to use the adder circuit distribution transfer used in common dvuhoborotnym the adders. Therefore, the proposed adder, designed to add vectors programmable data bit has almost the same switching delay that dvuhoborotny adders.Bibliographic data1. The main directions of developing the hardware implementation of neural network algorithms / Ivanov Y. P. and others (abstracts of the Second Russian conference "Neurocomputers and their application", Moscow, 14.02.1997) // Neurocomputer. - 1996. - N 1, 2. - S. 47-49.2. U.S. patent N 5278945, CL 395/27, 1994 (prototype 1 of the invention).3. USSR author's certificate N 690477, CL G 06 F 7/38, 1979.4. U.S. patent N 5644519, CL 364/736.02, 1997 (the prototype of the 2nd invention).5. U.S. patent N 4825401, CL 364/760, 1989 (prototype 3rd of the invention).6. U.S. patent N 5047975, CL 364/786, 1991.7. U.S. patent N 4675837, CL 364/788, 1987 (prototype 4-th of the invention). 1. Neuroprocessor, containing the first, second, and third registers, the first memory block store type and muda first register, information input each digit in a second register connected to the corresponding discharge the first input bus neuroprocessor, the control inputs of the first, second and third registers are the corresponding control inputs of neuroprocessor, characterized in that it introduced the fourth, fifth and sixth registers, shift register, the logic element And the second memory block store type switch with three dimensions in two, two devices for computing functions of saturation, the adder and the computing device having the input bits of the first vector operand, the input bits of the second vector operand, the input bits of the third vector operands, inputs installation boundaries of the data in the first vectors of operands and results, inputs installation boundaries of the data in the vectors of the second operand inputs of the installation boundaries of the data in the vectors of the third operand, the first and second control inputs of the loading vectors of the third operand in the first memory block, the control input shipment matrix third operands from the first memory block in the second memory block and outputs the bits of the first vector and second vector components of results of operations of vector addition of the first operand with the product of the vector of the second opearates switch from three directions in two, the information inputs of the first memory block store type, the first, third, and fourth registers and parallel information inputs shift register bitwise combined and connected to the corresponding bits of the first input bus neuroprocessor, each digit of the second input bus connected to the second information input of the corresponding discharge switch from three directions in two, the first output of each of the discharge of which is connected to the input of the corresponding category of vector input operands of the first device to calculate functions of saturation, the control input of each of the discharge of which is connected to the output of the corresponding discharge of the second register, the second output of each of the discharge switch from three directions in the two connected to the input of the corresponding category of vector input operands of the second device to calculate a function of saturation, the control input of each of the discharge of which is connected to the output of the corresponding discharge of the third register, the output of each bit of a vector of results of the first device to calculate the saturation functions connected with the second information input of the corresponding discharge of the multiplexer, the output of each of the discharge of which is connected as the second vector operand which is connected to the output of the corresponding order of the vector of results of the second device to calculate a function of saturation, information outputs of the first memory block store type connected to inputs of respective bits of the vector of the third operand of the computing device, the output of each bit of a vector of the first summand of the results of the addition operation of the first vector operand with the work of the second vector operand matrix third operands stored in the second memory block, which is connected to the input of the corresponding discharge of the first vector components of the adder, the input of each bit of a vector of the second summand which is connected to the output of the corresponding rank vector of the second summand of the results of the addition operation of the first vector operand with the work of the second vector operand matrix third operands stored in the second memory block, computing device, each input set of boundary data in the vectors of the first operands and the results of which is connected to the output of the corresponding discharge of the fifth register and the corresponding input set of boundary data in the vectors of the terms and amounts of the adder, the output of each bit of a vector of the sums of which is connected with the corresponding information input of the second memory block store type, each data output of which Pego discharge switch from three directions in two, the output of each of the discharge of the fourth register is connected to the information input of the corresponding discharge of the fifth register and the corresponding input set of boundary data in the vectors of the third operand of the computing device, each input set of boundary data in the vectors of the second operand which is connected to the output of the corresponding discharge of the sixth register, the information input of each of the discharge of which is connected to the output of the corresponding discharge shift register, serial data input and output of which are combined and connected to the first input control loading vectors third operands in the first block of memory of the computing device and to the first input element And the output of which is connected to the control input of the reading of the first memory block store type, the second input element And the control input of the shift of the shift register and the second control input loading vectors third operands in the first block of memory of the computing device combined and connected to a corresponding control input of neuroprocessor, the input to the relay control matrix third operands from the first memory block to the second block of memory of the computing device and inputs pravara, the control inputs of the switch from three directions in two, a multiplexer and a fourth register, the control inputs of the write shift register and the first memory block of the store type and the control inputs of the reading and writing of the second memory block store type are the corresponding control inputs of neuroprocessor, the output state of the first and second memory blocks store type are outputs status neuroprocessor.2. Neuroprocessor under item 1, wherein the computing device comprises a shift register that performs in a single cycle arithmetic shift all of the operands stored in the N-bit vector by J bits to the left, where J is the minimum value which is a multiple of the word length of the data vectors of the second operand of the computing device, a delay element, the first memory block with the input port of the store type and containing N/J cells for storing N-bit data, a second memory block containing N/J cells for storing N-bit data, N/J multiplier units, each of which multiplies the N-bit vector data programmable bit on the J-bit multiplier, and the pattern of addition of vectors, forming a double row code amount N/J + 1 vectors of data is clucene to the information inputs shift register, the outputs of which are connected to information inputs of the first memory block, the outputs of each cell which is connected to the information inputs of the corresponding cell of the second memory block, the outputs of each cell which is connected to the input bits of the vector mnimyh corresponding block multiplication, the input bits of the multiplier which is connected to the inputs of the corresponding J-bit group of bits of the second vector operand of the computing device, the outputs of each block multiplication connected to inputs of bits of the corresponding vector components of the scheme of addition of vectors, the input bits (N/J + 1)-th vector components which are connected to the inputs of the bits of the first vector operand of the computing device, inputs installation boundaries data vectors third operands which are connected to corresponding inputs of the installation boundaries of the data in the vectors of operands of the shift register, the input of the mode of operation of which is connected to the first input control loading vectors third operands in the first block of memory of the computing device, the second control input loading vectors third operands in the first memory unit which is connected to the clock input of a shift register and the input of the element sarago memory block connected to the input of the relay control matrix third operands from the first memory block to the second block of memory of the computing device, each input set of boundary data in the vectors of the second operand which is connected to the input of a significant correction of the corresponding block multiplication inputs installation boundaries of the data in the vectors of the first operands and results of computing devices connected to the inputs of the installation boundaries data vectors mnimyh and results of each block multiplication, and to the inputs of the installation boundaries of the data in the vectors of the terms and results of the scheme of addition of vectors, the outputs of the bits of the vectors of the first and second components results which are the respective outputs of the computing device.3. Neuroprocessor under item 1, characterized in that each of the devices for computing functions of saturation register contains the input data, information inputs, which are inputs of the corresponding bits of vector input operands of this device, the computing device includes an input data register, data inputs, which are inputs of the corresponding bits of the vectors of the first and second operands of the computing device, the adder includes an input data register, the information inputs of which are the corresponding inputs of the adder.4. Device for wiod which is connected to the input of the corresponding category of vector input operands of the device, the output of each bit of a vector of results which is connected to the output of the first multiplexer corresponding discharge device, characterized in that it introduced the scheme of distribution of transfers and the formation scheme transfers, and each digit is entered the second multiplexer and the logical XOR, EQUIVALENCE, AND IS NOT a BAN, and direct input element PROHIBITION and the first input element and NOT the EQUIVALENCE of each of the discharge devices combined and connected to the corresponding control input device, the output of the element AND NOT the n-th discharge device is connected to the input distribution transfer through (N - n + 1)-th digit shaping circuit transfers the output of the transfer (N - n + 2)-th bit which is connected with the control input of the first multiplexer n-th digit of the device, the output element of the PROHIBITION of which is connected with the control input of the second multiplexer of the discharge device, the input generation migration (N - n + 1)-m discharge circuit forming transfers and negative input distribution transfer through (N - n + 1)-th digit distribution scheme, the transfers, the carry-in input of the (N - n + 1)-th digit of which is connected to the output of the second multiplexer n-th digit of the device (inany respectively with the second input of the EXCLUSIVE OR element and a negative input element PROHIBITION (q - 1)-th digit of the device, the first information input of the second multiplexer which is connected to the output of the transfer in the (N - q + 2)-th digit scheme of distribution of transfers (where q = 2, 3, ..., N), inputs the initial transfers of the scheme of distribution of transfers and shaping circuit transfers the second input of the EXCLUSIVE OR element, an inverse input element PROHIBITION and the first information input of the second multiplexer of the N-th discharge devices combined and connected to the bus logic zero, and each discharge device, the output of the second multiplexer is connected to a second input of element EQUIVALENCE, the output of which is connected to the first information input of the first multiplexer, the second information input of which is connected to the second information input of the second multiplexer and the first input of the EXCLUSIVE OR element, the output of which is connected with the second input element AND IS NOT the same discharge device.5. The device according to p. 4, characterized in that the diffusion scheme transfers the output of the transport in the q-th bit is connected to the carry-in input of the (q - 1)-th bit (where q = 2, 3, ..., N).6. The device according to p. 4, characterized in that the circuit formation hyphenation contains N logical elements And and OR, and each is about element And, the output of which is connected to the first input of the corresponding element OR the second input and the output of which is connected respectively to the input of the generation of the transfer in the corresponding discharge circuit and the output of the transfer in the same discharge circuit, the second input of the first element is the input of the initial transfer circuit, the second input of the q-th element And is connected to the output (q - 1)-th element OR (where q = 2, 3, ..., N).7. Computing device containing N/2 decoders digits of the multiplier and the matrix multiplication of N columns by N/2 cells, each of which consists of the generation of partial discharge works and one-bit adder, and the corresponding control inputs of the circuits forming the partial discharge works i-x cells of all columns of the matrix multiplication combined and connected to the corresponding outputs of the i-th decoder bits of the multiplier (where i = 1, 2, ..., N/2), the first input of the one-bit adder of each cell of the matrix multiplication is connected to the output of the circuit forming partial discharge works the same cell of the matrix multiplication, characterized in that it introduced N/2 BAN logic elements, the delay elements and N-bit shift register, each category consists of logs is Oh triggers, performs the functions of the memory cells, respectively, the first and second blocks of memory devices, the logic element PROHIBITION and the multiplexer, the input of each of the discharge of the first vector operand of the device connected to the second input one-bit adder of the first cell of the corresponding column of the matrix multiplication, the control inputs of multiplexers and inverted inputs of the elements of the PROHIBITION of all cells in each column which are United and connected to the corresponding input set of boundary data in the vectors of the first operands and results of the device, each input set of boundary data in the vectors of the second operand which is connected to the inverted input of the corresponding element of the BAN, the output of which is connected to the first input of the corresponding decoder bits of the multiplier, the second and third inputs of the i-th decoder bits of the multiplier are connected to the inputs respectively (2i - 1)-th and 2i-th bit of the second vector operand device (where j = 2, 3, ..., N/2), direct input of the j-th element of the BAN is connected with the third input (j - 1) th decoder bits of the multiplier (where j = 2, 3, ..., N/2), the input of each bit of a vector third operands of the device connected to the second information input of the multiplexer corresponding a discharge shift register, the first inverted input of which is connected to the corresponding input set of boundary data in the vectors of the third operand of the device, the second inverse input element PROHIBITION of the q-th bit shift register connected to the first negative input element PROHIBITION (q - 1)-th digit shift register (where q = 2, 3, ..., N), direct input element BAN r-th digit shift register connected to the output of the flip-flop (r - 2)-th digit shift register (where r = 3, 4, ..., N), the control inputs of multiplexers of all bits of the shift register combined and connected to the first input control loading vectors third operands in the first block of memory devices, input synchronization triggers all bits of the shift register and the input of the delay elements combined and connected to the second input control loading vectors third operands in the first block of the memory device, the output of each multiplexer discharge shift register is connected with the information input trigger of the discharge shift register, the output of which is connected to the information input of the first flip-flop of the last cell of the corresponding column of matrix multiplication, the output of the first flip-flop the j-th cell of each column of the matrix multiplying soedinevol first synchronization triggers all cells of the matrix multiplication combined and connected to the output of the delay element, the inputs of the second synchronization triggers all cells of the matrix multiplication combined and connected to the input of the relay control matrix third operands from the first memory block to the second block of the memory device, the second information input of the differential formation of partial discharge works of the i-th cell of the q-th column of the matrix multiplication is connected with the output element of the PROHIBITION of the i-th cell (q - 1)-th column of matrix multiplication (where i = 1, 2, ..., N/2 and q = 2, 3, ..., N), second input of the one-bit adder of the j-th cell of each column of the matrix multiplication is connected to the output of the sum of one-bit adder (j - 1)-th cell of the same column of the matrix multiplication (where j = 2, 3, ..., N/2), the third input one-bit adder of the j-th cell of the q-th column of the matrix multiplication is connected to the output of the multiplexer (j - 1)-th cell (q - 1-)th column of the matrix multiplication (where j = 2, 3, ..., N/2 and q = 2, 3, ..., N), the third input one-bit adder of the j-th cell of the first column of the matrix multiplication is connected with the third output (j - 1) th decoder bits of the multiplier where (j = 2, 3, ..., N/2), the output amount of the one-bit adder of the last cell of each column of the matrix multiplication is the output of the corresponding order of the vector components of the results of the device, the output multiplexer of the last mesh is istwa (where q = 2, 3, ..., N), the first bit of the second vector components of results which is connected to the third output (N/2) th decoder digits of the multiplier, the second inverse and direct inputs of the element PROHIBITION of the first level and direct entry element PROHIBITION of the second discharge shift register, the second information inputs of the circuits forming the partial discharge works of all cells in the first column of matrix multiplication, the third single-bit inputs of the adders of the first cells of all columns of the matrix multiplication and the direct input of the first element PROHIBITION combined and connected to the bus logic zero, and in each cell of the matrix multiplying the output of the first flip-flop is connected to the information input of the second trigger, the output of which is connected to the direct input element PROHIBITION and the first information input of the differential formation of partial discharge works, the third control input of which is connected with the second information input of the multiplexer, the first information input connected to the output transfer one-bit adder of the same cell of the matrix multiplication.8. The adder containing formation transfers, and each of N of its digits is a half-adder and the logical EXCLUSIVE OR element, and the input of each PAA connected respectively to first and second inputs of the half-adder corresponding digit adder, output the sum of which is connected to the first input of the EXCLUSIVE OR element of the same category adder whose output is the output of the corresponding order of the vector sums of the adder, the second input of the EXCLUSIVE OR element or q-th bit of the adder is connected to the output of the transfer in the q-th bit of shaping circuit transfers (where q = 2, 3, ..., N), the input of the initial transfer and the second input of the EXCLUSIVE OR element of the first digit of the adder connected to the bus logic zero, characterized in that each digit is entered the first and second logical elements PROHIBITION, the sum of each digit half-adder adder is connected to the direct input of the first element PROHIBITION of the discharge of the adder, the output of which is connected to the input distribution transfer through appropriate discharge shaping circuit transfers the output of the transfer of each digit half-adder adder is connected to the direct input of the second element of the PROHIBITION of the discharge of the adder, the output of which is connected to the input of the generation of the transfer in the appropriate category of schemes for the formation of hyphens, inverted inputs of the first and second elements BAN each digit adder United and connected to the appropriate input set is

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The invention relates to computing and is designed for optimal digital synthesis and playback pictures, audio and other perceptions writable media or display

The adder codes "1 of n" // 2129730

The invention relates to digital communications, automation and computer engineering and can be used when implementing parallel highlighters channel digital signals, alarms and devices for counting the number of ones in the binary combination

The method of addition-subtraction of numbers encoded signals, and a device for its implementation // 2109325

The invention relates to automation and computer engineering and can be used in discrete slots for adding - subtracting numbers, three-level encoded signals on orthogonal components functions Popov

Digital adder // 2099776

The invention relates to communication technology and can be used for byte summation of the signals received at the analog-to-digital PCM conversion with kompaktirovaniem

Parallel asynchronous adder // 2097826

The invention relates to computer technology and can be used in high-speed digital devices

Summing device // 2092891

The invention relates to the field of automation and computer engineering and can be used in information processing systems during the implementation of technical means

Device for adding // 2090925

The invention relates to computing and can be used to summarize both analog and digital values

Summing device // 2059286

The adder // 2049346

The invention relates to computing, and in particular to devices on CMDP-transistors for the arithmetic and logical processing of digital information

Multiple-input single-bit adder // 2047216

The invention relates to computing and microelectronics, and is intended to build arithmetic-logical unit processors

The processor element // 2089936

The invention relates to computing and can be used to build computational tools that require high-performance data processing systems, for example, digital processing of visual information