Device for quality control of discrete communication channels

 

(57) Abstract:

Device for quality control of discrete communication channels relates to techniques for telecommunication and can be used in adaptive data transmission systems for monitoring the status of discrete communication channels. The technical result consists in reducing the number of false positives when determining the state of a discrete communication channel. This technical result is achieved that the device containing the sensor signals reset, connected in series block matching, the input of which is the input of the block error detection and counter single errors introduced additional delay elements, three blocks of code compares two meter, inverter, trigger and two logical element I. This device increases the efficiency of the data transfer process, which is achieved by introducing a delay of a decision on the transition of the channel state from one state to another. 2 Il.

The invention relates to telecommunication and can be used to analyze the state of the communication channel affected by interference, leading to errors.

A device for quality control decryptdata, block error detection and counter single error, a second input connected to the output of the sensor signals reset [1].

It is known device [2], providing higher accuracy assessment of the condition of the channel by introducing two elements of the delay element And the element OR counter related errors and new links.

The common disadvantage of the device [1, 2] is a multiple change of the decision on the state of the channel at moments of transition from one state to another, as well as false positives (Fig. 1,b). This is because the number of errors k (the number of malformed code combinations) in a controlled sample of size N (the total number of code combinations on the observation interval) has a random character and the reliability of the decisions taken on a comparison of k values with a threshold value of kthen.is determined by the value N and is always finite.

There are two types of variation k near the threshold kthen.(Fig. 1,a):

- type A, when the channel does not change its state v, and the random emission values of k lead to false positives device;

- type B, when the channel changes from one state to another; in this situation, possible unstable solutions when ve the EAN data transfer Protocol. Therefore, multiple changes of decisions that arise during the transition of the channel from one state to another, significantly reduce the efficiency of transmission.

To address the discussed disadvantage is invited to decide on the status of the channel with some delay. The delay can be chosen based on the specified probability of completion of the ejection of the value k in accordance with the recommendations outlined in [3, 4].

As a prototype of the proposed technical solution that implements the procedure (1) to(4), the selected device [1].

The objective of the proposed solutions to the present invention is to reduce the number of false positives when determining the state of the discrete channel.

To obtain a technical result in the device for quality control of discrete coordination of communication channels, containing the sensor signals reset, connected in series block matching, the input of which is the input of the block error detection and counter single error introduced delay element, three blocks of code compares two meter, inverter, trigger and two logical element And the sensor output signal reset is connected through a delay element to the second the second input is a second input device, and the output connected to the first input of the first logic element And, via inverter connected to the first input of the second logic element And a second input connected to the second input of the first logic element And to the output of the sensor signals, reset; output of the first element And connected to the first input of the first counter and the second input of the second counter, a first input connected to the output of the second logic element And a second input of the first counter, the output of which is connected to the first input of the first unit of comparison code, a second input connected to the third input device and the second input of the second block of comparison codes the first input of which is connected to the output of the second counter and the output to the first input of the trigger, a second input connected to the output of the first unit of comparison codes, and the output is the output device.

The proposed technical solution the device for quality control of discrete communication channels characterized by the fact that virtually eliminates false alarms due to random emission, and multiple alarms during the transition of the channel from one state to another, which is achieved by the introduction of delay elements, the three schemes sravneniy effect namely, the almost complete exclusion of multiple switches channel, and hence the efficiency of the data transfer process is achieved due to delay a decision on the transition of the channel from one state to another. The simulation results show that the use of delay almost completely eliminate false positives (Fig. 1B).

Structural diagram of the device shown in Fig. 2.

Device for quality control of discrete communication channels, containing the sensor signals reset 1, connected in series block matching 2, the inlet of which is the input of the block error detection 3 and counter single error 4, and delay element 5, the blocks comparison codes 6, 7, 8, inverter 9, logic gates, And 10, 11, counters 12, 13 and a trigger 14, and the sensor output signals reset 1 is connected via a delay element 5 with the second counter input single error 4, the output of which is connected to the first input of the comparison codes 6, the second input is a second input device, and the output connected to the first input of the logical element and 10, And through an inverter 9 is connected to the first input of the logical element And 11, the second input is connected with a second photoscheck 13, first input connected to the output of logic element 11 And the second input of the counter 12, the output of which is connected to the first input of the comparison codes 7, a second input connected to the third input device and the second input unit of comparison codes 8, the first input of which is connected to the output of the counter 13 and the output to the first input of the trigger 14, a second input connected to the output of the Comparer codes 7, and the output is the output device.

The device operates as follows.

Code combination of discrete communication channel through the block 1 is supplied to the unit 2, which detects errors. If an error is detected at the output of unit 2, you receive a pulse input to the counter 4, counting these pulses.

Sensor 1 produces pulses with a period T equal to the interval of the monitoring channel and appearing in moments the end of the controlled sample.

Formed in the counter 4 by the end of the sample the number of errors k is compared with a threshold value of Kthen.at block comparison codes 6. If k > kthen.at the output of the Comparer code 6 is set to logic "1", opening the logical element And 10 and through the closing Inverto the chick 13.

The counter 12 with a block of code compares 7 provides a delay decision-making in the detection of the transition of the channel from the state 0with error probability p0in the state of1with error probability p1and the counter 13 with the block comparison codes 8 provides a delay in the detection of the transition of the channel from the state1with error probability p1in the state of0c probability of error p0. Recorded in the counter 12 number comparing unit comparing codes 7 with a given delay , supplied to the second input of this block. If the counter will be consecutive pulses, the output of the Comparer code 7 appears logical "1", sets the trigger 14 in one state, which means the transition channel status1with error probability p1.

In the situation when k>kthen., a logical zero from the output of the Comparer codes 6 through the inverter 9 opens the logical element And 11. Thus the pulses from the sensor 1 are at the counting input of the counter 13, zeroing the meter 10. If the counter 13 will be held consecutive pulses, the counter produces a number that is equal to the amount of delay and at the output of the Comparer codes 13 appears logical "1", setting the trigger the p0.

The device does not react on emissions, duration of which exceeds the amount of delay since the transition value of k over the threshold kthen.is zeroing "zapomnivshegosya" counter. For example, if delay = 7, and the situation k>kthen.preserved within1= 5 cycles of control and then received k<kit will be counter 12 and will begin to consider the counter 13.

Units of comparison codes can be implemented on the basis of the digital Comparators LSP or IP, and the memory block on the chip RT (5,6) [5].

Literature

1. N 269976 (USSR), CL H 04 L 1/10, 1968 (prototype).

2. A. S. N 658753 (USSR), CL H 04 B 3/46, 1979.

3. Tikhonov Century. And. Emissions of random processes. - M.: Nauka, 1970, 392 S.

4. Gavrilov, A. N., Novikov, A., Pilchin A. N. Method of reducing the number of spurious solutions in the identification procedures of quasi-stationary States of a discrete communication channel// Meiwes. collection of Mathematical and software of computing systems. - Ryazan, RGRTA, 1998. - 146 C.

5. Zeldin E. A. Digital integrated circuits in information-measuring equipment. - L.: Energoatomizdat. Leningrad. Department, 1986, 150 C.

Device for the block matching, which input is the input of the block error detection and counter single errors, characterized in that the added delay element, three blocks of code compares two meter, inverter, trigger and two logical element And the sensor output signal reset is connected through a delay element with a second counter input single error, the output of which is connected to the first input of the first block of code compares the second input is a second input device, and the output connected to the first input of the first logic element And, via inverter connected to the first input of the second logic element, And the second input is connected to a second input of the first logic element And to the output of the sensor signals reset, the output of the first element And connected to the first input of the first counter and the second input of the second counter, a first input connected to the output of the second logic element And a second input of the first counter, the output of which is connected to the first input of the first unit of comparison code, a second input connected to the third input device and the second input of the second block of code compares the first input of which is connected to the output of the second counter, and the return to the PE the output device.

 

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