Semiconductor storage device and method of manufacturing

 

(57) Abstract:

The device includes multiple memory cells formed by alternately applying the cell capacitor of the store type and the cell capacitor of the combined shop-slotted type in the directions of row and column. Each electrode of the storage capacitor of the memory cell extends to overlap with the electrode of the storage capacitor of the adjacent memory cell. The combined condenser-store-slotted type formed in the substrate to increase the storing capacity that allows storing capacitor store type to increase through the expansion of the storage electrode of the capacitor. Due to the alternating arrangement of the capacitor store-slotted type and capacitor store type is warned stepping overlap, leakage current and transient errors capacitor shop-slotted type. 2 C. and 15 C.p. f-crystals, 3 ill.

The present invention relates to a semiconductor memory device and method of manufacturing the specified device, in particular for highly integrated semiconductor memory device and method of manufacturing the specified device, in which the effective plomari technology.

In the areas of technology, semiconductor memories have been made competing efforts to increase the number of memory cells in the chip. To achieve this goal, it is important to minimize the size of the matrix of memory cells, in which many memory cells is formed within a limited surface of the chip.

In the implementation of the minimum area of the memory cell is well known DRAM /Dynamic Random-Access Memory/ in which individual cell has a single transistor and a single capacitor. As in the aforementioned memory cell is a large part of the area occupied by the capacitor, with the development of higher-density packaging of a highly integrated semiconductor memory device becomes more important to increase the capacity of the capacitor along with the minimization of the square semiconductor occupied by the capacitor so as to facilitate information discovery and to reduce transient errors caused by alpha particles.

In order to minimize the area occupied by the capacitor, and to maximize the capacitance of the capacitor of the memory, as described above, was proposed structure of cells distributed stacked capacitors /indicated below SSC/what I memory, having a cell structure with SSC, described on pages 31-34 of International conference on electronics 1989

In previous technologies mentioned above, the first electrode of the capacitor form stretched to areas adjacent memory cells by exposing the area of the source of each memory cell on the semiconductor silicon substrate in which transistors are formed. 64 Mbit DRAM can be achieved in the above cell structure with SSC. However, there is a limitation to achieve sufficient holding surface of the capacitor required for a 256 Mbit DRAM, because the first capacitor must be formed between the second capacitors, which are formed later. That is because the size of each capacitor of the first memory cells is limited by each capacitor of the second memory cells, the expansion of the second capacitors of the memory cells that extend to the left and right should be limited in order to maintain a balance with the size of each capacitor of the first memory cells. Accordingly, each capacitor of the second memory cells could not be fully expanded to the capacitor of the first memory cells along the side of the second memory cells to cover the maximum area of undergone balance with those of the capacitors of the first memory cells, and also to expand completely each capacitor of the second memory cells to the capacitor adjacent the first memory cells. However, as in the traditional structure of cells with SSC the size of each capacitor of the first memory cells is limited by the capacitor of the second memory cells, this structure does not meet the goal of achieving effective area of the capacitor required for a 256 Mbit DRAM, the cell size which is smaller than the cell size 64 Mbit DRAM.

A brief statement of the substance of the invention.

Therefore, the present invention is to develop a DRAM, in which to solve the above problems of conventional technologies matrix of memory cells is formed by alternating the location of the cell capacitor of the store type and the cell capacitor of the combined shop-slotted type adjacent to each other.

Another objective of the present invention is to develop a manufacturing method that efficiently produces DRAM having the above structure.

To solve the above problems, the matrix of memory cells in accordance with the present invention runs as a highly integrated semiconductor memory device, kolorowanki substrate, and the capacitor store, located on a switching transistor, the storage electrode of each capacitor store the type of the first memory cells among the memory cells expanded to the areas of the second memory cells adjacent to the first memory cells and the storage electrode of each capacitor store the type of the second memory cells expanded to areas adjacent first memory cells so that the extended storage electrodes of the second memory cells are located next to the first memory cells, partially overlapping each other with extended storage electrodes of the first memory cells, in which each capacitor of the first memory cells includes a capacitor store type and the capacitor slotted type, formed in the area of the source of the switching transistor in the semiconductor substrate in such a way that the respective first and second memory cells are arranged alternately and adjacent to each other in the direction of the row and in the column direction.

The present method for the manufacture of a matrix of memory cells having the above structure includes a first process of delineating the active regions increasing spatial oxide layers on semiconductor padlock memory on the active regions and forming a first insulating layer over the resulting structure; a third process of forming the bit wires to connect to each area of the drain of the transistor and forming a second insulating layer over the resulting structure; a fourth process of forming a first window for exposing predetermined areas of the regions of origin for the formation of the first memory cells having a capacitor combo store-slotted type; a fifth process of forming cracks in the semiconductor substrate by using the first window; a sixth process of forming a capacitor on the inner surface of the slit, and on the second insulating layer and then forming a third insulating layer on the resulting structure; a seventh process of forming a second window through the display areas of the source transistors, primasius to the first memory cells in the direction of the row or column direction; and a ninth process of forming the capacitor store type through the second window.

A brief description of the drawings.

The present invention will be described in the form of embodiments with reference present invention;

Fig. 2A through 2G show one variant of the process for the manufacture of a matrix of memory cells in accordance with the present invention and

Fig. 3A to 3E show another variant of the implementation processes for the manufacture of a matrix of memory cells in accordance with the present invention.

Detailed description of preferred embodiments.

In the matrix of memory cells of the present invention, as shown in Fig. 1, memory cells M1 and M3, which includes the combined store-slotted type capacitors 11, 12 and 13, are arranged alternately and adjacent to the memory cell M2 with capacitors 20, 21 and 22 store type. In the memory cells, the electrodes 11 storage /first electrodes of the capacitors/ the first and third cells M1 and M3 memory expanded to the adjacent area of the second memory cells, and the electrode 20 of the second storage cell M2 memory expanded to the areas of the first and third cells M1 and M3 memory. Although the matrix of memory cells shown in Fig. 1, is illustrated as having memory cells adjacent to each other in the direction of the row matrix of memory cells in the column direction also has a memory cell having a capacitor combo store-slotted type, and memory cells, illustrious one variant of the implementation processes for the manufacture of a matrix of memory cells in accordance with the present invention.

Fig. 2A illustrates a process for forming transistors and bit lines 5 on the semiconductor substrate 100 in which the active region is first outline through the increase in spatial oxide layer 101, the semiconductor substrate 100 with the first conductivity type using selective oxidation. Doped with the first impurity layers of polycrystalline silicon, which must be electrodes 1 gate formed on the active regions by the introduction of the oxide layers of the shutter and at the same time, the first conductive layers 4 of the transistors, for example doped with impurity of the first layers of polycrystalline silicon, are formed on predetermined areas of spatial oxide layer 101 so that they are connected to gate electrodes of the memory cell adjacent to the spatial oxide layers. Area 2 source and drain region 3 are formed on each side of the electrodes 1 of the shutter in the surface of a semiconductor substrate through ion implantation, and then the first insulating layer 11, such as an HTO layer /high-temperature oxide/ or the LTO layer /low temperature oxide/, having a thickness that is formed over the whole surface of the above-mentioned structures. Since that time, the metal layers Ura Fig. 2A includes first, second and third memory cells M1, M2 and M3.

Fig. 2B illustrates the process of forming the second insulating layer 12 and the first Windows OP1, in which, after the process shown in Fig. 2A, placed second insulating layer 12 having a thickness of about, for example, the HTO layer, and using the second insulating layer pattern mask to form the first window OP1 for the display areas 2 a source of the first and third cells M1 and M3 memory.

Fig. 2C illustrates the process for forming the slits 10 and second conductive layers 11, which function as the first electrodes of the capacitors. Through the first window OP1 semiconductor substrate 100 is etched to form slits 10, this time with the second conductive layers 11 serving as the first electrodes of the capacitors, for example doped with impurity of the second layers of polycrystalline silicon, having a thickness of the order placed on the walls of the slots 10 and the second insulating layers 12, forming by this figure of the electrode, as shown in Fig. 2C. Here the depth of the slit 10 can be installed within about 0.5 μm - 10 μm in accordance with the specified capacity.

Fig. 2D illustrates the process for forming the dielectric film 12 and the third conductive layers 13, having a thickness of the order , sequentially formed, thereby completing the first cells M1 and M3 memory, respectively with capacitors combined store-slotted type. Here, the dielectric film 12 has a structure of the oxide layer, such as an HTO layer or a layer of LTO, or the structure of oxide/nitride/oxide, i.e., the ONO structure, or the structure of the nitride/oxide, i.e., NO structure. Here instead of the combined shop-gap capacitor can be formed external capacitor gap type in which a charge is stored in the outer region of the slit in the semiconductor substrate.

Fig. 2E illustrates the process for forming the third insulating layer 13 and the second window OR. After the process shown in Fig. 2D, put the third insulating layer 13 having a thickness of about, for example, the HTO layer, and then forming a second window OR for the display region 2 and source of the second cell M2 memory. Here after the application of BPSG (borophosphate silicon glass) layer having a thickness that can be formed in the third insulating layer by planarization through the process of fusion.

Fig. 2F illustrates the process for forming the fourth conductive layer 20 serving as the first electra. After performing the process shown in Fig. 2E, for the formation of the electrode pattern as illustrated in Fig. 2F, put the fourth conductive layer 20 having a thickness which serves as a first electrode of the capacitor, for example doped with impurity of the fourth polycrystalline silicon layer. From this moment over the fourth conductive layer 20 are sequentially formed dielectric film 21 and the fifth conductive layer 22 having a thickness which functions as the second electrode of the capacitor, thereby completing the second cell M2 memory having a capacitor store type. Here, the dielectric film 21 has a structure of an oxide layer such as a layer of ito or the LTO layer, the ONO structure or NO structure.

Fig. 2G illustrates a process for forming planarizing layer 30 and the metal electrode 31, in which, after the process shown in Fig. 2F, for planarization is applied planariidae layer 30, for example BPSG layer, and then forming a metal electrode 31, thereby completing a DRAM having a cell capacitor shop-slotted type, and the cell capacitor store type.

Fig. 3A to 3E show others taneem.

The manufacturing process prior to the process of Fig. 3A, is identical to the process described in connection with Fig. 2A, and therefore, omitted.

Fig. 3A illustrates the process for forming the second insulating layer 12, the nitride layer N and the fourth insulating layer 14. After the process illustrated in Fig. 2A, forming sequentially a second insulating layer 12 having a thickness of about, for example, the HTO layer, the nitride layer N, having a thickness of the order and the fourth insulating layer 14 having a thickness of about, for example, the HTO layer.

Fig. 3B illustrates the process for forming the second conductive layers 11 serving as the first electrodes of the capacitors, and mutually planarizing layer 32, in which by applying pattern mask on the fourth insulating layer 14 form a first window so as to expose the region 2 and source of the first and third cells M1 and M3 memory. The semiconductor substrate is etched to form slots 10 through the first window, and from that moment for the formation of the electrode pattern is applied to the second conductive layers 11 having a thickness of about which serve as electrodes of the capacitors, for example doped with impurity of the second polycrystalline silicon layers. For PNA planariidae layer may be formed from a layer, folded from a SOG layer and the HTO layer, or a layer composed of the BPSG layer. Here the depth of the slit 10 can be installed within about 0.5 μm - 10 μm in accordance with the desired capacity value.

Fig. 3C illustrates the process for forming the second window and the fourth conductive layer 20, which functions as a first electrode of the capacitor. After the formation of mutually planarizing layer 32 form a second window for the display region 2 and source of the second cell M2 memory. From that moment on both surfaces of the second window and mutually planariidae layer 32 is applied to the fourth conductive layer 20 having a thickness which functions as a first electrode of the capacitor, for example doped with impurity of the fourth polycrystalline silicon layer to form an electrode pattern, as shown in Fig. 3C.

Fig. 3D illustrates the process for removing the fourth insulating layer and mutually planarizing layer, in which by using the nitride layer as a layer that blocks the etching, wet etching removes the fourth insulating layer and mutually planariidae layer which is located between the second conductive layer 11 and che the each memory cell.

Fig. 3E illustrates the process for forming the dielectric film 33 and the sixth conductive layer 34 serving as the second electrode of the capacitor. After the process shown in Fig. 3D, the dielectric film 33 are simultaneously formed on the second conductive layer 11 and the fourth conductive layer 20, and then put the sixth conductive layer 34 serving as the second electrode of the capacitor having the thickness of about, for example doped impurity sixth polycrystalline silicon layer, thereby completing the first and third cells M1 and M3 memory and the second cell M2 memory. Here, the dielectric film 33 has a structure of the oxide layer or an ONO structure, such as an HTO layer or a layer of LTO.

After executing the process illustrated in Fig. 3E, planariidae layer, such as BPSG layer, is applied for planarization, and then form the metal electrodes, thereby completing a DRAM having a cell capacitor shop-slotted type, and the cell capacitor store type.

As described above, as a capacitor in accordance with the present invention uses a capacitor combo store-slotted type as perver traditional patterns with SSC. Accordingly, when manufacturing a capacitor of a combined store-slotted type /or slotted type/ sufficient holding surface of each capacitor can be obtained without limiting its distance between the second capacitors, i.e. capacitors store type. In addition, during the formation of the second condenser /capacitor store type/ first capacitor, i.e., the capacitor combo store-slotted type /slot/ can greatly reduce the problem of stepping overlap compared with the traditional first capacitor, i.e., the capacitor store type, so that the process is easy to perform.

In addition, in the matrix of memory cells of the present invention, since the first memory cells having capacitors combined store-slotted type /or slotted type/, and the second memory cells having capacitors store type, come close to each other in the direction of the row and in the column direction, are formed alternately memory cell having a gap. The result is the advantage that the leakage current between the memory cells with slit and occasional errors caused by alpha-particles, can be eliminated. In addition to the common first electrode in the capacitor of the second variant of implementation of the present invention, surface of the upper section, the side section and the bottom portion of the conducting layer is used as the first electrode of the capacitor, so that the holding surface of the capacitor can be maximized. Therefore, the decrease in capacity caused by the increased density of highly integrated semiconductor memory device, can be compensated by means of the structural approach.

1. Semiconductor memory device containing a first set of memory cells, each cell of which contains a capacitor store-slotted type, the second set of memory cells, each cell of which contains a capacitor store types, while the cells of the first and second sets are located on a semiconductor substrate in a row, alternating with each other, characterized in that the part of the capacitors store-slotted type overlaps with the capacitors store type on either side of each cell of the first set.

2. Semiconductor storage device according to p. 1, characterized in that the cells of the first and second sets are interleaved with each other and in the direction perpendicular to the direction of the series.

3. Semiconductor saponi is adowanie capacitor shop-slotted type, is 0.5 - 10 μm.

4. A method of manufacturing a semiconductor memory device, comprising the steps of contouring active regions increasing spatial oxide layers on the semiconductor substrate of the first conductivity type, forming memory cells on the active regions and forming a first insulating layer on the resulting structure, forming a second insulating layer on the resulting structure, characterized in that it envisages the creation of the first window by opening certain areas stokovyh areas for forming the first memory cells having capacitors store-slotted type, the formation of cracks in the semiconductor substrate using the first window forming capacitors on the surface of the slits and the second insulating layers, and forming a third insulating layer on the resulting structure, forming a second window to open stokovyh areas located in adjacency to the first memory cells and in the direction of the row and in the column direction for formation of the second memory cells having capacitors store type second Windows.

5. The method according to p. 4, characterized in that the step of forming the second izolirujushchego.

6. The method according to p. 5, characterized in that the step of forming capacitors and the third insulating layer comprises forming the conductive layer serving as a first electrode of the capacitor on the surface of the slit, and the second oxide layer and then applying mutually planarizing layer on the resulting structure.

7. The method according to p. 6, characterized in that the step of forming capacitors store type consists of forming the conductive layer serving as a first electrode of the capacitor store type, through the second window.

8. The method according to p. 4, wherein the first oxide layer and second oxide layer is a layer of high temperature oxide (ito).

9. The method according to p. 6, characterized in that mutually planariidae layer is a layer of spin on glass (SOG).

10. The method according to p. 6, characterized in that mutually planariidae layer is a stacked layer formed of SOG layer and a layer of ito.

11. The method according to p. 6, characterized in that mutually planariidae layer is a stacked layer formed of ito layer and layer borophosphate silicon glass (BPSG).

12. The method according to p. 6, otlichalis zimno planariidae layer, formed on the nitride layer.

13. The method according to p. 12, wherein the second oxide layer and mutually planariidae layer is removed through the wet etching.

14. The method according to p. 12, wherein after the step of etching the oxide layer and mutually planarizing layer dielectric film is simultaneously formed on the exposed full surface conductive layers.

15. The method according to p. 14, wherein the dielectric film is formed through a step of forming a first oxide layer over the surface of the exposed conductive layer, forming a nitride layer over the first oxide layer and forming a second oxide layer over the nitride layer.

16. The method according to p. 4, characterized in that the first, second and third insulating layers is a layer of high temperature oxide (ito).

17. The method according to p. 4, wherein the third insulating layer is formed by applying and melting BPSC layer having thickness of the order after the step of forming the capacitor of the first memory cell.

 

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