Video ram and the output serial data

G11C7 - Arrangements for writing information into, or reading information out from, a digital store (G11C0005000000 takes precedence;auxiliary circuits for stores using semiconductor devices G11C0011406300, G11C0011413000, G11C0011419300)

(57) Abstract:

The invention relates to videooperation storage devices and can be used as a dual port memory. The technical result is to increase speed. The first video RAM contains multiplexers, line serial I/o data gates of the column and the read amplifiers. In the second video RAM contains the means of fixation and fixation means and output. According to the method of transmitting data, which is synchronized with the even and odd addresses, synchronize them with subsequent recorded data synchronization with the serial clock pulse. 3 c.p. f-crystals, 4 Il.

The present invention relates to a video RAM (random access memory), is made as a dual port memory, and, more specifically, to a video RAM, which is adaptable to high-speed system clock signal, and to output serial data from it.

With the increasing number of portable computers, such as portable computers (laptops), video RAM is now very widely used in computers. Video RAM is a dual port memory, which can b the th speed in the normal function of the dynamic RAM. Video RAM and the method of its operation are disclosed in U.S. patent N 4498155, entitled "Semiconductor memory device in an integrated circuit with a serial matrix and a matrix with random sampling" and filed February 5, 1985, the video RAM is designed to be able to connect port dynamic RAM to the CPU (Central processing unit) and port high-speed RAM to the periphery, such as CRT (cathode ray tube) or a video camera, so it has a wide scope. In order to diversify its function and store more information, developed video RAM with a high degree of integration.

High-quality graphics from each device you want to work in response to a high frequency in order to effectively perform a graphical coordination between the computer and its user. Thus, the internal circuitry in the video RAM should also work in response to high-speed system clock signal supplied from the system. It depends on whether the data transmitted through the line input/output (1/0) data in the video RAM, to respond to the system clock.

The closest to the invention is IU itexnicheski systems". M., High school, 1988, page 30.

The aim of the present invention is the provision of video RAM, which is capable of transmitting data at high speed from the data register to an external device display.

Another objective of the present invention is the provision of video RAM, which is able to minimize cycle times, certain serial clock signal.

Another objective of the present invention is the provision of video RAM, which is able to reduce the period of each successive clock pulse. Another additional objective of the present invention is the provision of video RAM, which is able to minimize the time cycle through the display data stored in the data register when the pre-charge line serial I/o related to the following data.

Another additional objective of this invention is the provision of a method of outputting serial data from the video RAM, which outputs the data stored in the data register when the pre-charge line serial I/o related to the following data.

The invention illustrated by the drawings.

In Fig. 1, the valve 4 columns for data transfer functions between the data register 2 and the line SIOO (serial input/output). Sequential valve 4 column has four sequential valve column, usually controlled by line SCSLi the serial column, and four consecutive gate of the column, usually controlled by line SCSLj the serial column. Line serial I/o consists of four lines for receiving data transmitted from the four consecutive gates of the column in response to a single signal resolution of the serial column. Data line SIO serial input/output are multiplexed through the multiplexer 6 and amplified through the amplifier 8 are read. The output of the read amplifier is fed to the fixing block 10 (latch), which is controlled by control signal PSOT, and the output unit 10 fixation is associated with the fixation block 12 and the output is controlled by control signal SOT and then outputs the data to the output. The process of operation is illustrated in Fig. 2. The serial address is incremented on the falling front of the serial text signal SC. The corresponding line of the serial column is unlocked in the register 2 data displayed on the serial line I/o, and the amplifier 8 is read thereby generates an amplified signal SDO. As shown in Fig. 2, the signal SDO generated on the falling front of the n-th successive clock pulse C, is fixed on the falling edge (n+1)-th successive clock pulse by means of the control signal, and then outputted as valid data at the rising edge (n+2)-th successive clock pulse SC.

In accordance with the present invention a video RAM having a data register that outputs serial data in response to the input serial address is synchronized with the serial clock pulse, contains the first line of the input/output data are synchronized with an even serial addresses and then removed from the data register, and a second line input/output data are synchronized with odd serial addresses and then removed from the data register.

In addition, in accordance with the present invention, the output serial data video OSUV having a data register that outputs serial data in response to the input of polpredy data which is synchronized with an even serial address and then removed from the data register to the first line of the input/output data, the second operation data, which is synchronized with odd serial address and then removed from the register on a second line input/output data, the third synchronization operation and latching the data transferred from the first operation with an even serial address, the fourth synchronization operation and latching the data transferred from the second operation with odd serial address, and a fifth synchronization operation serial data, fixed in the third and fourth sequential clock pulse, and then issuing the synchronized serial data to an external device.

The circuit according to Fig. 3 contains the register 2 data line SIO serial I/o with 8 lines for transferring data read from register 2 data, four valve 4A of the column is formed between the line SIO serial I/o register 2 data and switchable lines SCSLOdd the serial column, which are selected odd-numbered address data register 2 data on four lines pogledi SIO serial I/o register 2 data and switchable lines SCSLeven the serial column selected even-numbered address data register 2 data for four lines of serial I/o, the selected even-numbered address, the multiplexers 14 and 16 for multiplexing eight lines of the serial input/output, responsive to the logic state (low/high) CA8, amplifier S/A 18 reading lines of input/output gain of the output signal from the output of the multiplexer 14, which is connected to the four lines of the serial I/o, the selected even-numbered address, and amplifier S/A 20-read-line input/output for amplifying the output signal from the multiplexer 16, which input is connected to the four lines of the serial I/o, the selected odd address even the fixation block 22 for fixing the output signal SDOeven amplifier S/A 18 reading lines of input/output under the control of the signal PSOTeven; the odd unit 24 fixing for fixing the output signal S OOdd amplifier S/A 20-read-line input/output under the control of the signal PSOTodd and the block 26 of the fixing and output for latching and outputting respective output signals of even-numbered block 22 fixing the odd unit 24 fixing the external device in response to the control signal SOT. As shown in Fig. 3, line SIT posledovatel 8. Two of the four lines of the serial input/output the selected address 8, and two of the other four lines of serial input/output the selected address 8, are fed to the multiplexer 14 is even, and the remaining four lines SIO serial input/output data are fed to the multiplexer 16 is odd. In Fig. 3 only register 2 data has two independent lines of serial I/o, which are selected by different addresses. Because of its selective operation of the operating cycle time can be reduced, and this will be described below.

In Fig. 4 shows a timing diagram showing the time relationships between the respective control signals of the circuit of Fig. 3. With reference to Fig. 4 will now be described the operation of the circuit of Fig. 3. Video RAM according to the present invention is capable of synchronized high-speed serial clock signal, bringing such serial data by performing independent random read operations, respectively, for the odd-numbered and even-numbered address data. As shown in Fig. 3 and 4, even the fixation block 22 and the odd unit 24 of the fixing respectively controlled by signals PSOTeven and PSOTodd, which in turn excited ka is OK 26 fixing and output in response to control signals from PSOTeven and PSOTodd. With excitation control signal that is synchronized to rising edge of each period serial clock pulse SC, the data is output from the block 26 of the fixing and output to an external device. On the basis of such work, when four of the eight lines SIO serial input/output perform read actions for data output to the periphery, the remaining four lines SIO serial I/o pre-charge and equalization, and when the other four lines SIO serial input/output perform read actions for data output to the periphery, the first four lines perform the pre-charge and equalization. The result may be synchronized with the serial clock pulse SC each period and then output the serial data.

The output serial data according to the present invention will now be described in comparison with the traditional way. As can be seen from Fig. 2, in each cycle line SCSL select consecutive columns must be charged and aligned for a single consecutive addresses, as the corresponding serial line I/o is selected each cycle. However, the resultant or an odd address, the corresponding line SIO serial I/o pre-charge and equalize line SCSL select consecutive columns only in the corresponding cycle. In Fig. 2 line SCSL choice serial column must be controlled by its own momentum to perform a pre-charge and equalization, however, in Fig. 4 line SCSL select the serial column is converted only by address. The multiplexers 14 and 16 operate to connect a corresponding line of the serial input/output to the read amplifiers line input/output, depending on the logical state of the serial address CA8. All control signals corresponding to odd numbers work when CA8 is in logic state "low", and all control signals corresponding to odd numbers work when CA8 is in logic state "high".

As described above, the video RAM according to the present invention are independent of the path output serial data respectively to the even-numbered addresses and odd addresses, the findings, thus, serial data every period of the serial clock signal. Consequently, it is possible in which nishith period of time between the respective periods of the system clock pulse.

1. Video RAM data register to output serial data in response to the input serial address, which is synchronized with the serial clock pulse, which includes a line of serial data I/o data that is synchronized with the serial address and then removed from the data register, the gate of the column to synchronize data stored in the data register, serial address and then the data line input/output data, a multiplexer for multiplexing data line SiO serial input/output data in response to address input column, and then transmitting multiplexed data to the read amplifier I/o to fetch the data line of the serial input/output data, when the received serial address, characterized in that it contains the second line of the serial input/output data, which is selectively synchronized with only odd or only even-numbered sequential address, and then removed from the data register, the second valve column to synchronize data stored in the data register, only odd or only even-numbered sequential AI serial input/output data, the output of which is connected to the second amplifier of the read input/data, which is selectively synchronized with only odd or only even-numbered sequential address.

2. Video RAM data register to output serial data in response to the input serial address, which is synchronized with the serial clock pulse, which includes the line of the serial input/output data, the gate of the column data, derived from register data line of the serial input/output data signal lines of the serial column, which is excited in response to the serial input of the address multiplexer connected to an input line of the serial input/output data, the read amplifier line serial data I/o, connected to the output of the multiplexer, means for fixing, supplied control signal, which is excited in response to the serial input address and the output of the amplifier readout line serial I/o fixation device and output to synchronize the respective output signals fixation means with input serial clock pulse, and then turn the data for data transmission, which selectively synchronized with only odd or only even-numbered sequential address, and then removed from the data register, the second valve column data output from the data register, the second line of the serial input/output data signal of the serial column, which is excited in response to input only even or odd consecutive addresses, the second multiplexer fed by the second line of the serial input/data output which is connected to the second amplifier of the read I/o data that is selectively synchronized with only odd or only even-numbered sequential address, the second fixation device, supplied as a control signal, which is excited in response to input only even or only odd consecutive addresses, for latching the output signal of the second amplifier readout line of the serial input/output data, the second fixation device and output to synchronize the respective output signals of the first and second fixation devices with serial input clock pulse, and then output the synchronized signals.

3. The output serial Manresa, which is synchronized with the serial clock pulse, providing for the transfer of data that is synchronized with the serial address register data line of the serial input/output data, multiplexing the data and then transmitting multiplexed data to the read amplifier input/output data, capture data before it is fed to the peripheral device, wherein the transmit data, which is synchronized with an even serial address and then removed from the data register to the first line of the serial input/output data, transmit data, which is synchronized with odd serial address and then removed from the data register to the second line of the serial input/output data, synchronize data transmitted from the even-numbered sequential address, and then fix the synchronized data, synchronize data transmitted from the odd-numbered sequential address, and then fix the synchronized data, synchronize recorded serial data serial clock pulse and then write the synchronized serial data to a peripheral device.

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