The unit diagnostic communication equipment

 

(57) Abstract:

The invention relates to radio engineering. Device diagnostics allows to evaluate the technical condition of the communication equipment operating in the simplex mode, due to the conservation of the pseudo-random test sequence in the memory element at the time of passage of the pseudo-random sequence according to the transmission path and outputting it to the reception path after the transfer. The device includes a pseudo-random sequence generator (1), delay (2), block error reporting (3), block error count (4), the block control signals (5), the switching unit connections (6), attenuator (7), the noise generator (8), block matching (9), managed by the divisor (10), the first (11) and second (12) bandpass filters, digital-to-analogue Converter (13), analog-to-digital Converter (14), a storage unit (15). Using (15) signals are pseudo-random sequence, the last on the transmission path diagnostic communication equipment, is stored until the transfer is finished, the entire sequence. After the pseudo-random sequence of (15) is fed to the receive path of the communication apparatus and transmitted in the opposite direction. Compared with it: increase the reliability of diagnosing the state of the communication apparatus operating in simplex mode. 3 C.p. f-crystals, 8 ill.

The invention relates to the field of radio, namely to control the technical state of equipment of communication, in particular the claimed device diagnostic communication equipment is intended to improve the reliability of diagnostic communication equipment operating in the simplex mode, not staying in touch.

The known device diagnostics - see the invention of the Device for controlling the operability of the radio. (51)4 H 04 B 17/00, published 22.02.90, issue No. 134; the invention of "Automated control system" (51)5 H 04 B 17/00 // H 04 B 3/46 published 30.06.94, Bulletin No. 12. They contain device-forming pseudo-random test sequence (SRP), the comparator test sequence error counter. These devices allow you to diagnose a communication system according to the coefficient of the error.

The General lack of analogues is the low reliability of diagnostic communication equipment operating in the simplex mode, since the control simplex communication equipment necessary to use the second communication equipment, and this reduces the reliability of diannah devices closest to the claimed device (prototype) in its technical essence is a diagnostic device based on the measured error rate, described in the invention "Device diagnostic equipment digital transmission systems" (51)5 H 04 B 3/46 published 15.05.92, Bulletin N 018. The device prototype consists of controlled communication apparatus of a pseudorandom sequence generator, the delay line block check error, block error count, the switching unit connections, block control signals, noise generator, attenuator.

Thus the output of a pseudorandom sequence generator connected to the first input of the delay line and the second input of the switching unit connections, the first output and the fourth input is connected to the corresponding input and output of the transmission path, the third output unit switching connection is connected to the input of the attenuator, the output of which the output of the noise generator connected to the first input of the switching unit connections, the fourth output and the third input of which is connected respectively to the input and output of the reception path, the group of outputs of the block control signals connected to the group of inputs of the switching unit connections, the second output of which is connected to the second input of the block check errors the output of which is connected to the input of block error count, the output of the delay line podci with analogues because diagnosing the communication equipment according to the error rate when passing test case, a pseudo-random sequence through a controlled apparatus, increased accuracy and reduced time costs due to the change of the ratio signal/noise.

However, this device does not provide sufficient reliability of the diagnosis, because when checking the transmission path controlled communication apparatus as a receiving path, you must use the reception path of the second communication apparatus and when checking the receive path controlled communication equipment as a transmitter path, you must use the transmission path of the second communication equipment.

The aim of the present invention is to develop a device diagnostic communication equipment, providing increased reliability of diagnosing the state of the communication equipment operating in simplex mode.

This objective is achieved in that known device diagnostics based on measurements of the coefficient of the error-containing pseudo-random sequence generator, a delay line, the block check error, block error count, the control unit sagledavali connected to the delay line, the output of which is connected to the input of block check error. The output of block check errors connected to the input of block error count. The first output block control signals connected to the control input of the switching unit connections, the output of which is connected to the attenuator and to the input of the noise generator. Added the following elements: block matching, controlled divider, first and second bandpass filters, digital-analog and analog-to-digital converters, memory block. While the output and input of the block matching are low-frequency output and input devices. The output of the attenuator is connected to the input of the second bandpass filter, the output of which is connected to the input of analog-to-digital Converter. The output of the analog-to-digital Converter connected to the input of the storage unit, the output of which is connected to the input of a digital to analogue Converter. The output of the digital to analogue Converter connected to the input of the first bandpass filter, the output of which is connected to the information input of the control of the divider, the output of which is connected to the input of the switching unit connections. The output switch and a high-frequency input/output which are the output and input devices. Second, Allaudin inputs of block matching, managed divider, digital-to-analog converters, memory devices, analog-to-digital Converter. Data bus block control signals connected to the data inputs of a pseudorandom sequence generator, the registration unit error, unit agreement, unit switching connection of the controlled divider.

Unit switching connection consists of a D flip-flop transistor, a relay, a power splitter. When this high-frequency input/output connected to the first contact of the first group of relay contacts and to the input of the power splitter. The output of the power splitter connected to the first contact of the second group of relay contacts. The second contact of the second group of contacts of the relay is the output of the block. The second contact of the first group of relay contacts is the entrance of the block. The third group of contacts of the relay with one contact connected to the output switching unit, and the other contact to the chassis. The data bus is connected to the information input of D-flip-flop. The synchronization input of which is a control input unit. The output of D-flip-flop is connected to the base of the transistor. The emitter of which is connected to the housing and the collector is connected to the control relay coil. The other end of which is, D-flip-flop, the element OR NOT, the first and the second level Converter. At this low frequency the input unit is connected to the input of the second inverter level. The output of which is connected to the input of the element OR NOT. The output of which is connected to the information input dual amplifier-shaper. To the data input of which is connected to the data bus device. To double the amplifier-shaper connected to the control input of the transmission and a control input receiving the block. Control input transmission in parallel connected to the synchronization input of D-flip-flop. Information the input of which is connected to the information output dual power amplifier-shaper. The output of D-flip-flop connected to the input of the first level Converter. The output of which is low-frequency output of the block.

Managed the divider consists of a buffer amplifier-shaper of the parallel register, d / a Converter, radio frequency amplifier with automatic gain control. Thus the input and output of radio frequency amplifier are, respectively, the information input and information output controlled divider. Data bus devices connected to the inputs of buffer condition is t to the inputs of the digital to analogue Converter. The output of which is connected to the input of the automatic gain control amplifier radio frequency. The control input of the considered block is connected to the synchronization input of the parallel register and the enable input of buffer amplifier-shaper.

The proposed device allows to determine the technical condition of the communication equipment operating in simplex mode. Due to the fact that it introduced new units (managed divider, digital-analog and analog-to-digital converters, memory block), the opportunity of remembering pseudorandom test sequence, which took place on the transmission path of the controlled communication apparatus on the transmission time of the whole sequence. After the transmission of the reception order reception path and compare with the original to determine the technical condition on the error rate. This increases the reliability of the diagnosis by excluding the second (additional) communication equipment.

The analysis of the level of technology has allowed to establish that the analogues, characterized by a set of characteristics is identical for all features of the claimed technical solution, no that yasooka known solutions in this and related areas of technology with the purpose of revealing of signs, match the distinctive features of the prototype of the features of the declared object, showed that they do not follow explicitly from the prior art. The prior art also revealed no known effect provided the essential features of the claimed invention transformations on the achievement of the technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

The claimed device is illustrated by drawings, showing:

- Fig. 1 - structural diagram of the claimed device diagnostic communication equipment;

- Fig. 2 is a structural block circuit switching connection;

- Fig. 3 is a structural diagram of a block matching;

- Fig. 4 is a structural diagram of the controlled divider;

- Fig. 5 is a structural diagram of a bandpass filter;

- Fig. 6 is a structural diagram of a system for digital signal processing;

- Fig. 7 - algorithm digital signal processing;

- Fig. 8 - assessment of the effectiveness of the claimed device.

The unit diagnostic communication equipment, is shown in Fig.1, consists of a pseudorandom sequence generator 1, the delay line 2, batteryfor 7, the noise generator 8, a block matching 9, the controlled divider 10, the first 11 and second 12 bandpass filters, digital-to-analogue 13 and analog-to-digital converters 14, a storage unit 15. The output of a pseudorandom sequence generator 1 is connected to the delay line 2, the output of which is connected to the input of block check error 3. The output of which is connected to the input of block error count 4. The first output block control signal 5 is connected to the control input of the switching unit connections 6. To the output of the switching unit connection 6 is connected to the attenuator 7 and to the input-noise generator 8. The output and input of the block matching 9 are low-frequency output and an input of the claimed device. The output of the attenuator 7 is connected to the input of the second bandpass filter 12, the output of which is connected to the input of analog-to-digital Converter 14. The output of the analog-to-digital Converter 14 is connected to the input of the storage unit 15, the output of which is connected to the input of a digital to analogue Converter 13. The output of the digital to analogue Converter 13 is connected to the input of the first bandpass filter 11, the output of which is connected to the information input of the control of the divider 10. Information output controlled divider 10 is connected Wetstone outputs and input devices. The second, third, fourth, fifth, sixth and seventh outputs of block control signals 5 are connected respectively to the control inputs of the block matching 9, the controlled divider 10, digital to analog Converter 13, a storage device 15, an analog-to-digital Converter 14. Data bus block control signal 5 is connected to the data inputs of a pseudorandom sequence generator 1, a block check error 3, the switching unit connections 6, block matching 9, the controlled divider 10.

Switching unit connections 6, shown in Fig. 2, consists of a D-flip-flop D6, transistor VT6, relay P6, divider power (voltage) R6.1, R6.2. High-frequency input/output of the claimed device connected to the first contact of the first group of relay contacts P6 and to the input of the power divider R6.1, R6.2. The output of which is connected to the first contact of the second group of relay contacts P6. The second contact of the second group of relay contacts P6 is output to block BL.7, and the second contact of the first group of contacts is the entrance block from BC.8, BL.10. The third group of contacts of the relay P6 one contact connected to the output of the switching device, and the other contact to the chassis. The input data bus from BC. 5 is connected to informacao switching connections 6. The output of D-flip-flop D6 is connected to the base of transistor VT6, the emitter of which is connected to the housing and the collector is connected to the control winding of relay P6. The second end of the winding of the relay P6 is connected to the supply voltage UPete.

Unit switching connection is:

a) to connect the high-frequency input/output device to the input of the attenuator when working on the transmission or to the outputs of the controlled divider and oscillator noise to accept;

b) to switch the controlled apparatus from the receive mode to the transfer mode and back.

D-flip-flop D6 is designed to preserve bits of information that defines the mode of the device (transmitting or receiving) at the time of passage of the test case. Transistor VT6 is designed to connect the supply voltage to the control winding of the relay. Power divider R6.1, R6.2 is designed to reduce high-frequency signal during operation of the controlled equipment to transfer up to the amount guaranteeing the normal operation of the switch.

Switching unit connections 6, shown in Fig. 2, can be implemented on the following hardware components:

D-flip-flop D6 - schemes known in the particular case can be Rea is Prokhorenko, Centuries Of Salima. - Mn. Belarus, 1991. - pages 104-112 (Fig. 2.46);

transistor VT6 - known element that operates in the mode key can be implemented on the transistor (as shown in Fig. 2) or on the chip type KN (CT). Chosen based on the switched current, voltage and switching time, see: Guide developer and designer REE./ M. Y. Maslennikov, E. A. Sobolev, L. F. Soloveichik and others - M.: LLP Device, 1993, book 2, pages 247-275; see: Digital and analog integrated circuits: Directory./C. C. Jakubowski, L. N. Nisselson, C. I. Kuleshov and others - M.: Radio and communication, 1989. - pages 447-455;

relay P6 - construction scheme is known, is based on the mode switching frequency dial signal, see: Guide developer and designer REA. / M. Y. Maslennikov, E. A. Sobolev, L. F. Soloveichik and others - M.: LLP Device, 1993, book 1, pp. 36-46;

power divider (voltage) R6.1 and R6.2 - scheme of the known, in the particular case can be implemented with resistors, taking into account the strength of the signal supplied to its input, see: Guide developer and designer REA. / M. Y. Maslennikov, E. A. Sobolev, L. F. Soloveichik and others - M.: LLP Device, 1993, book 2, pages 219-223.

The block matching 9, shown in Fig. 3, consists of a double increase the frequency input of the claimed device is a low-frequency input block matching 9 and is connected to the input of the second D9.5 the level Converter. The output of the second D9.5 the level Converter connected to the input of the element OR NOT D9.3, the output of which is connected to the information input In dual amplifier-shaper DD9.1. To the input data Wo dual amplifier-shaper DD9.1 connected to the data bus from BC. 5 of the claimed device. To the control inputs SA and SV dual amplifier-shaper DD9.1 is connected to the control input of transmission from Nl.5 and a control input receiving from Nl.5. The control input of transmission from Nl.5 parallel connected to the synchronization input (input C) D-flip-flop D9.2, the information input D which is connected to the information output AO dual amplifier-shaper DD9.1. The output of D-flip-flop D9.2 is connected to the input of the first D9.4 the level Converter, the output of which is low-frequency output unit and the claimed device.

The block matching 9 is intended to align the data bus with low-frequency output and the input of the controlled communication equipment.

Dual amplifier-shaper DD9.1 is intended to create and enhance digital signals when communicating device agreement with the data bus system digital signal processing. D-flip-flop D9.2 is intended to preserve the value of the bit, per acen for inversion signal, which is necessary because of the connection of low-frequency input to the inverted input of the dual amplifier-shaper. Level transducers D9.4, D9.5 are designed to align the device level diagnostic communication equipment with low-frequency input and output of the controlled equipment, if their element base are different. If the low-frequency input and output of the controlled devices are transistor-transistor logic, level transducers in the block matching is not needed.

The block matching 9 (see Fig.3) can be implemented on the following hardware components:

dual amplifier-shaper DD9.1 - the buffer element, the scheme of the well-known, in particular, can be implemented on-chip PA, see : Digital integrated circuits: a Handbook./ M. I. Bogdanov, I. N. Grell, C. A. Prokhorenko, V. C., Salima. - Mn. Belarus, 1991. - pages 125-130 (Fig. 2.59);

D-flip-flop D9.2 - scheme of the known, in the particular case can be implemented on the chip type TM, see: Digital integrated circuits: a Handbook. / M. I. Bogdanov, I. N. Grell, C. A. Prokhorenko, V. C., Salima. - Mn. Belarus, 1991. - pages 104-112 (Fig. 2.46);

the element OR NOT D9.3 - chip type LES, see: Digital integration-66 (Fig. 2.15);

the first D9.4 and the second D9.5 level transducers - scheme of known, selected depending on the type of electrical matching, in the particular case can be implemented on the chip type PU, see: Digital integrated circuits: a Handbook./ M. I. Bogdanov, I. N. Grell, C. A. Prokhorenko, V. C., Salima. - Mn. Belarus, 1991. - pages 362-366 (Fig. 3.88).

Managed divider 10 shown in Fig. 4, consists of a buffer amplifier-shaper DD10.1, the parallel register DD10.2, the digital to analogue Converter DD10.3, the radio frequency amplifier DD10.4 with automatic gain control. The input and output of radio frequency amplifier DD10.4 are respectively the information input from the Nl.11 and information access to BC. 6 block. Data bus from BC.5 is connected to the input of buffer amplifier-shaper DD10.1, the outputs of which are connected to the parallel inputs of the register DD10.2. The parallel outputs of the register DD10.2 are connected to the inputs of the digital to analogue Converter DD10.3, the output of which is connected to the input of the automatic gain control amplifier radio frequency DD10.4. Control input from Nl.5 unit connected to the enable input of buffer amplifier-shaper DD10.1 and to the input of synchronistical at the receiver input is proportional to the level of the output signal of the transmitter.

The buffer amplifier-shaper DD10.1 is intended to enhance the code combination received from the data bus, and outputting it to the parallel input of the register with the arrival of the control signal. The parallel register DD10.2 is designed to store code and outputting it to the input of digital to analog Converter receiving the control signal. D / a Converter DD10.3 is designed for converting digital code to an analog signal, which is input to the control system of the automatic gain control amplifier radio frequency. The radio frequency amplifier with automatic gain control DD10.4 is intended to set the level of a high frequency signal is proportional to the level of a high frequency signal received from the transmission path.

Managed divider 10 shown in Fig. 4, can be implemented on the following hardware components:

the buffer amplifier-shaper DD10.1 - the buffer element, the scheme of the well-known, in particular, can be implemented on-chip PA, see: Digital integrated circuits: a Handbook./ M. I. Bogdanov, I. N. Grell, C. A. Prokhorenko, V. C., Salima. - Mn. Belarus, 1991. - pages 125-130 (Fig. 2.61);

parallel what would be the case), see: Digital integrated circuits: a Handbook./ M. I. Bogdanov, I. N. Grell, C. A. Prokhorenko, V. C., Salima. - Mn. Belarus, 1991. - pages 366-377 (Fig. 3.96);

d / a Converter DD10.3 - scheme of the well-known, in particular, can be implemented on the chip type PA, see: Digital and analog circuits: the manual./ C. C. Jakubowski, L. I., Nisselson, C. I. Kuleshov and others - M.: Radio and communication, 1989. page 422 (Fig. 5.130);

the radio frequency amplifier DD10.4 with automatic gain control scheme of the building is known, see: Chips and their applications: a reference manual./ C. N. Veniaminov, O. N. Lebedev, A. I. Miroshnichenko. - M.: Radio and communication, 1989. page 71 (Fig.2.29).

The pseudo-random sequence generator 1 is designed to generate a pseudo-random sequence of a given length determined by the transmission speed is controlled communication equipment. The delay line 2 is designed to delay elements of the pseudorandom sequence to the time required for transmission elements of the pseudorandom sequence. Block check error 3 is intended for comparing transmitted and received elements of pseudo-random sequences, detection of errors and reports them to the block error count. Block error count 4 predn to generate signals, control the operating modes of the device and delivery of elements of the pseudo-random sequence in the data bus. D / a Converter 13 is designed to convert digital signal to analog issuance in the reception path of the controlled communication equipment. Analog-to-digital Converter 14 is designed to convert analog signal to digital, while ensuring retention of the information signal in a storage unit. The storage unit 15 is designed to store the information signal in digital form within the time required to transfer all pseudo-random test sequence.

The pseudo-random sequence generator 1, the delay line 2, block check error 3, block error count 4, the block control signals 5, d / a Converter 13, an analog-to-digital Converter 14, a storage unit 15 is technically possible to implement in the form of systems digital signal processing (DSP) 16 on the basis of the microprocessor. Thus the pseudo-random sequence generator 1, the delay line 2, block check error 3, block error count 4 are implemented in software using a persistent storage device (ROM privatelist, which command system CSO loaded in the system. The storage unit 15 is implemented using random access memory (RAM data) system CSO (see Fig. 6). Increased requirements for analog-to-digital Converter 14, which should be high-speed transmission pseudo-random sequence and the frequency range in which to operate controlled communications equipment. Modern element base allows this, for example chip MAX100 works up to 125 MHz (see Catalog company MAXIM 1996, NEW RELEASES DATA BOOK-Volume V section 7 page 9). Requirements for digital-to-analogue Converter 13 is less high. It can be implemented, for example on a chip MAX 555 (see Catalog company MAXIM 1996, NEW RELEASES DATA BOOK-Volume V section 9 page 82).

The principle of operation of the CSO system is described in many sources: see Reference. S. T. Horsetail, N. N. Verlinsky, E. A. Popov, "Microprocessors and microcomputers in automatic control systems", pages 394-410. The closest in technical essence is a system of digital signal processing, described in the book by A. A. Lane "Digital processing of signals TMS 32010 and its application," published by the Military Academy of communications, Leningrad, 1990, p. the execution of digital signal processing will give the block diagram of the implemented their algorithm, for example, in the form shown in Fig. 7, inside the rectangle representing the digital signal processing. Through p-P3 denoted by controlling the inputs-outputs of a microprocessor system through V0-V1 - output and input for transmission and reception of information signals. Such information about the block enough to implement it, because in this case shows the block diagram can be produced programming known system CSO using known methods.

The attenuator 7 is designed to reduce the power level at the input of a bandpass filter, and is a known device (see "Measurements in electronics: a Handbook. C. A. Kuznetsov, V. A. Dolgov and others - M.: Energoatomizdat, 1987, pp. 353-355). Depending on the input power can be used attenuators of various types. When input power up to 3 Watt advisable to use resistive stepped attenuators, up to 10 Watts - ultimate attenuators, based on the phenomenon of attenuation of electromagnetic energy beyond the waveguide.

The noise generator 8 is designed to generate radio noise signals to provide the desired ratio of signal to noise on exploitatie, reliable communications and automated systems". Ch. I./HP Century The Polish. - M.: Military publishing house, 1992, page 261, Fig. 113(a). The noise generator is based on the use of the shot effect in the temperature-saturated vacuum diode with direct heat. In the anode current of this diode is the variable component. The effective value of current of the diode in the saturation mode is determined by the Schottky formula

< / BR>
where e is the electron charge;

I0- the anode current of the diode

f is the noise bandwidth.

Vacuum diodes V (for example, type DS) allow to generate a noise signal in the range from 1 to 600 MHz. Based on this created diode noise generator G2-32, see : Measurements in electronics: Directory./C. A. Kuznetsov, V. A. Dolgov and others - M. : Energoatomizdat, 1987, pp. 423-425. He is a coaxial line with the diode operating in saturation mode.

The first 11 and second 12 bandpass filters are designed to allocate the bandwidth of the signal at the input of the storage device and the controlled divider. Consist of an operational amplifier and a set of discrete elements, the nominal values of which depend on the bandwidth that you want to filter. Diagram of the bandpass filter is presented on the bandwidth of the filters depends on the speed of information transfer and is determined by the ratio

.

To select the value of the items you must set the values of quality factor Q and the gain K. Then, assuming C1=C2=C, obtain the analytical expressions for calculation

< / BR>
The center frequency of the filter settings can be modified independently with R1 or R2, but this will change the transfer ratio K

The device operates as follows.

Signals are pseudo-random sequence through the block matching 9 go to low-frequency input diagnostic communication equipment, is a control signal output switching means in the transmission mode. After the transmission path of the high-frequency output communication equipment, high-frequency signal at the RF input of the device in the switching unit connection 6, which converts the level of this signal. High-frequency signal is transmitted through the attenuator 7 and the second band-pass filter 12 to the input of analog-to-digital Converter 14, the output of which the signal in digital form is supplied in a storage unit 15 that stores until the end of transmission of all pseudo-random sequence. To reduce the memory storage unit 15 is used de is Iraida of conditions

< / BR>
where fd- sampling rate;

finthe upper frequency spectrum of the signal, a band-limited filter;

fnthe lower frequency spectrum of the signal, a band-limited filter;

n is the decimation factor, n=1,2,3....

By reducing fdthe number of reports that you want to remember is reduced n times, however, it lost the information about the signal level, which leads to the necessity of storing in the storage unit 15 (in RAM digital signal processing) values Umax (amplitude signal) and playback multiple parts using a controlled divider 10. After completing the transfer of all pseudo-random sequence diagnosed communications equipment by means of the control signal from the output switching unit switching connection 6 is transferred into the receive mode. From the block memory 15 signal in digital form is fed to the input digital to analogue Converter 13 and through the first band-pass filter 11, a high-frequency signal given to the desired level in a controlled divider 10, is mixed with the signal noise noise generator 8. The received signal from the high-frequency input/output device is supplied to the high-frequency shoelacing sequence through a low pass input device, proceed to block registration error 3, where is the comparison of the sent and received pseudo-random sequence. In block error count 4 calculates the error rate on the basis of which a conclusion is made about the technical condition of the communications equipment.

Algorithm pseudo-random sequence generator 1, the delay line 2, block check error 3, block error count 4, block control signals 5, d / a Converter 13, an analog-to-digital Converter 14, a storage unit 15 can be implemented based on the algorithm of digital signal processing 16, which is represented within the rectangle in Fig. 7. The blocks algorithm 16.1 on 16.13 shows the control device in the transfer mode, and 16.14 16.29 on in receive mode. The algorithm works as follows. To start diagnosing the output P2 of the control unit switching connection is served enable signal to write information on the operation mode, and D0 of the data bus is supplied value information that specifies the transfer mode system digital signal processing Nl. 16.1. Sets the value of the transmitted bit pseudo-random sequence n, starting with the first (n=1) Nl.16.2. Reading the n-th bit pseudo-random Poslednij occurs when applying the enabling signal on the output P1 of the control interface block BL.16.3. Set the initial value of the amplitude of the input signal Umax(Umax= 0) for the implementation of the analog-to-digital conversion Nl.16.4. The next step is to set the initial value of the current sample number amplitude signal (option a), starting with the first BL.16.5. The next step is comparing the time of transmission of one information pulse t with sampling period t, which is analog-to-digital conversion of the input signal BL.16.6. At t = at are analog-to-digital conversion of the signal received at the input V1, and write the obtained value in the memory BL.16.7. Otherwise, the cycle is repeated to achieve this equality. The next step compares the current value of the amplitude of the signal U with a predefined maximum value of the amplitude of the signal UmaxBL.16.8. If U>Umaxthen remembered the new maximum value of the amplitude of the signal BL.16.9, if not, that is not remembered. In both cases, the next count, a increase of this parameter on the unit BL. 16.10. Then check the complete transmission of the information pulse a>b (comparison with the number of samples during PEREDAChI next pseudorandom bit sequence (n= n+1) BL.16.12. Otherwise, is the following reference this information pulse. The next step checks the termination condition of the transmission pseudo-random test sequence - comparison of the current value of the number of transmitted bits pseudo-random sequence with the total number of m bits transmitted during the transmission of BL.16.13. If n<m, then transfer the next pseudo-random pulse sequence. If n>m, then by the transfer device in receive mode by issuing an enabling signal on the output P2 of the control unit switching connection and D0 data bus values of information that defines the receive mode BL.16.14. Setting the desired division ratio of the controlled divider is implemented by issuing the enabling signal on the output P3 of control managed by a divider, and the D0-D3 data bus is the division factor Nl.16.15. The initial value of the number of errors z arising from the reception pseudo-random sequence is assumed to be zero (z= 0) Nl.16.16. For the next two steps occur set the initial values of the parameter n (number of received bits n= n+1 pseudorandom sequence), setting the initial values of which are reading the values of the a-th frame, and d / a conversion frequency of the output signal V0 BL.16.19, BL.16.20. This operation occurs until then, until you have transferred all the samples of the current element of the pseudorandom sequence BL. 16.21. After checking the conditions of ending the transmission of the information pulse BL. 16.22 reading the values of the n-th bit of the pseudorandom sequence with the D0 data bus with the advent of the enabling signal on the output p management unit approval Nl.16.23. Read the values of the n-th bit from the memory and compares the values of the received bits and read from the memory BL.16.24, Nl.16.25. If the values are different, then the number of errors z increases by one the value of BL.16.27. If the values are equal, the value of the parameter z remains unchanged, and is the next pseudorandom bit sequence BL.16.26. Upon satisfaction of the conditions to the completion of acceptance pseudo-random sequence (n>m) BC. 16.28 outputs the number of errors z Nl.16.29, and the algorithm is fully implemented.

Switching unit connections 6 operates as follows. On the data bus from BC.5 information on the input D flip-flop (D) signal that determines the transmission mode, the synchronization input of D-flip-flop (entrance C) D6 control signal from Nl. 5, R is, ensure the opening of the transistor VT6. Thereby connecting the power source UPeteto control the relay coil P6 that their contacts of the second and third groups respectively connects the output of the power divider R1, R2 to the base Camp.7, and the case - to the exit switch. The first group of contacts is opened, thereby disabling the receive path of the device diagnosis. To ensure reception mode by the data bus signal from Nl. 5, defines the receive mode, the synchronization input of D-flip-flop (entrance C) D6 control signal from Nl.5 with the control input unit allowing entry of the information signal in the D-flip-flop D6, the result at the output of D-flip-flop D6 signal is present, transistor VT6 is closed, the control relay coil P6 de-energized, the second and the third working group of contacts are open, the first group of contacts is closed, and through it the high-frequency signal is from Nl.8, BL.10 on the high-frequency output unit.

The block matching 9 operates as follows. To transfer control pseudo-random sequence at a low frequency output unit via the data bus from BC. 5 enter the elements of the pseudo-random sequence, to the input data dual celebates DD9.1 control signal, allows switching of input data Wo dual amplifier-shaper with information output Ao dual amplifier-shaper. The elements of the pseudorandom sequence output Ao dual amplifier-shaper DD9.1 serves for information input (D input) D-flip-flop D9.2 and with the arrival of the control signal on the trigger input (input C) D-flip-flop D9.2 is transmitted through the first level Converter D9.4 on the low-frequency output. For receiving the control pseudo-random sequence with the input management technique from Nl.5 on the control input CB dual amplifier-shaper DD9.1 is transmitted to the control signal, allowing the connection information input In dual amplifier-shaper DD9.1 to the input data Wo dual amplifier-shaper DD9.1. Low input elements of the pseudo-random sequence through the second level Converter DD9.5 and the element OR NOT DD9.3 act on the information input In dual amplifier-shaper DD9.1 and data bus.

Managed divider 10 operates as follows. To the input of radio frequency amplifier DD10.4 receives the signal from the output of the first bandpass filter from Nl.11. With the data bus enters informainformation through the buffer amplifier-shaper DD10.1 is written in the parallel register DD10.2. This information is stored during the time of the reception pseudo-random sequence. D / a Converter DD10.3, is connected to the parallel outputs of the register DD10.2, produces a constant level by an automatic gain control amplifier radio frequency DD10.4 in accordance with the value of a number written in binary code in the parallel register DD10.2.

Evaluation of the effectiveness of the claimed technical solution.

1. A distinctive feature of the simplex communication is the fact that some of the elements used in the transmission mode and the reception mode. Conventionally, they can be represented as shown in Fig. 8.

Calculate the total error in the determination of the technical condition Qwhen diagnosing the condition of the communication equipment using prototype and claimed device. In the first case, assuming the error in the determination of the technical condition made both means of communication are the same, we obtain (Fig.8,a):

Qtrans.= Q1+ Q3+ Q3+ Q2;

QAve= Q2+ Q3+ Q3+ Q1;

Q= = 2Q1+ 2Q2+ 4Q3= 2(Q1+ Q2+ 2Q3)

where Q1- the mA;

Q3the error introduced by the General elements of the transmission path and reception.

In the second case, when using the proposed device will provide (Fig. 8,b):

Q= = Q1+ Q2+ 2Q3.

Thus, the total error is reduced by half when using the claimed device.

2. Reduces the time of diagnosis due to the introduction of noise generator according to the method laid down in the prototype.

1. The unit diagnostic communication equipment, containing the pseudo-random sequence generator, a delay line, the registration unit error, unit control signals, the switching unit connections, attenuator, noise generator, and the output of a pseudorandom sequence generator connected to the delay line, the output of which is connected to the input of block registration errors, the output of which is connected to the input of block error count, the first output block control signals connected to the control input of the switching unit connections, the output of which is connected to the attenuator and to the input - noise generator, characterized in that it further introduced the block matching, a controlled divider, first and second bandpass filters, digital is Vlada subwoofer output and input devices, the output of the attenuator is connected to the input of the second bandpass filter, the output of which is connected to the input of analog-to-digital Converter, the output of which is connected to the input of the storage unit, the output of which is connected to the input of a digital to analogue Converter, the output of which is connected to the input of the first bandpass filter, the output of which is connected to the information input of the control of the divider, the output of which is connected to the input of the switching unit connections, high-frequency input-output and output "Switches" which are the outputs and the input of the diagnostic communication equipment, second, third, fourth, fifth, the sixth and seventh outputs of block control signals connected respectively to the input control supply and control input receiving unit coordination, control inputs of the controlled divider, digital to analogue Converter, storage devices, analog-to-digital Converter, a data bus block control signals connected to the data inputs of a pseudorandom sequence generator, the registration unit error, unit agreement, unit switching connection of the controlled divider.

2. The device under item 1, characterized in that the block is d-output unit connected to the first contact of the first group of relay contacts and to the input of the power splitter, the output of which is connected to the first contact of the second relay contact, a second contact which is the output of the block, and the second contact of the first group of contacts is the entrance block, the third group of contacts of the relay with one contact connected to the output of the Switch and the other contact to the housing, the data bus is connected to the information input of the D flip-flop synchronization input of which is a control input unit, the output of D-flip-flop is connected to the base of the transistor, the emitter of which is connected to the housing and the collector is connected to the control relay coil, the other end of which is connected to the power source.

3. The device under item 1, characterized in that the block matching consists of a dual amplifier-shaper, D-trigger, element, OR IS NOT, first and second level converters, and low-frequency input unit connected to the second input of the level Converter, the output of which is connected to the input of the element OR NOT, the output of which is connected to the information input dual amplifier-shaper, to the data input of which is connected to the data bus device, to the control inputs of the dual amplifier-shaper connected to the control input of the transmission is connected parallel the m ilitary amplifier-shaper, the output of D-flip-flop connected to the input of the first level Converter, the output of which is low-frequency output of the block.

4. The device under item 1, characterized in that the controlled divider consists of a buffer amplifier-shaper of the parallel register, d / a Converter, radio frequency amplifier with automatic gain control, and the input and output of radio frequency amplifier are, respectively, the information input and information output unit, the data bus is connected to the input of buffer amplifier-shaper, the outputs of which are connected to the parallel inputs of the register whose outputs are connected to the inputs of the digital to analogue Converter, the output of which is connected to the input of automatic gain control of radio frequency, the control input unit is connected to the synchronization input of the parallel register and the enable input of buffer amplifier-shaper.

 

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