A controllable oscillator with a preset frequency

 

(57) Abstract:

The invention relates to the field of radio electronics and can be used in devices for various purposes, such as managed lo or sensors discrete set of frequencies. The problem to be solved by the proposed device is to improve its performance through the use of the divider with variable division factor (DPCD), which computes the absolute value of the detuning relative to the nominal value and determines its sign. A controllable oscillator with a preset frequency contains the oscillator G electrical oscillation, the pulse shaper, the frequency divider with variable division factor, m-shadowy gray code Converter in a positional binary code (MPC), the element hi OR NOT, the adder MAC, register MAC, functional inverter, buffer register MAC, the code Converter MAC in the gray code, the schema subtraction, detector front trigger pulse, four delay elements frequency divider with a fixed division ratio, the inverter, the first RS-flip-flop, a second RS-trigger and the element ELI IS NOT inverted logic. 4 Il., table 1.

The invention relates to electronics, is the th equivalent external control code, and can be used in devices for various purposes, such as managed lo or sensors discrete set of frequencies.

Similar to the proposed device can serve as a synth preset UG [1] containing the input bus fogthe frequency of the reference oscillator, the output bus frequency of the controlled oscillator, a divider with a fixed division factor (DFCD) frequency fogthe phase detector D, a lowpass filter (LPF), an analog adder (CM) voltage eupand voltage PE eupdriven generator (UG), the divider with variable division factor (DPCD) frequency fugthe decoder (LH) code N preset, digital to analog Converter (DAC) that generates eupand the code bus (Code N).

The tuning range of HUGO is divided into a number of sub-bands, and pre-installation of the fugis fed to the second input Cm voltage eupwith the DAC output. The exact setting fugis the system IFPC with voltage eupgenerated by the phase detector D and LPF.

Closest to the technical essence and the presence of significant uenzeinstellung a Oszillators, Fig1 and 2) [2] , containing 1 oscillator (UG), managed by 8 input voltage Uroutput 2 bus signal with frequency fx, valve 3 circuit containing four 9, 10, 11, 12 JK-flip-flop, three 13, 14, 15 dvuhtumbovyh valve, two 16 element OR two 17, 18 of the inverter, the first 4 counter counting time oscillations with frequency fxsecond reversible 6 meter with 6a parallel outputs connected to the inputs 6b register 7 of the code Converter-voltage (PKN), which forms a voltage Urcontrolling the frequency fxfor example, using varicap (Kapazitatdiode).

The selected prototype ring-locked loop frequency to the nominal value operates on the principle of electron-counting frequency (ESC), when the number of oscillations with a period 1/fxis counted by the first counter during time T0equal to the nominal duration of the measuring interval (Soll-Zeitintervall), while comparing with the corresponding to this interval nominal number of oscillations (Soll-Schwingungzahl). While the number of oscillations, non-rated, taking into account the sign of the detuning, comes to V - or R-input reversible 6 meter, and the managed account is converted to a regulating voltage Urnear the duration of the transition process from the start of the measuring interval (or change the division ratio of the first 4 meter), after which the frequency fxapproaching par with precision.

The discrete frequency f on the unit of account ESC-limiting instrumental accuracy is determined by a given duration T0the measuring interval and does not depend on the nominal value of the measured frequency f = 1/To(Hz), where T0in (C), which determines the information capacity N countable structure that specifies the number n of its binary digits nlog2N, where N=T0fhmax.

To the technical complexity of these prototype affecting the duration of the transition process when determining the value of the frequency detuning relative to the nominal value, can be attributed to the use of two counting schemes with reversing 6 meter final result, switching of the invoice Raman valve 3 schema.

In addition to the above, the prototype using counters positional binary code (MPC), the inherent restrictions limiting value frequency account due to possible failures in multi-digit scheme with intermediate switching of the invoice.

The problem to be solved by the proposed device is to improve its performance while in the education specialized DPCD, computes the absolute value of its detuning relative to the nominal value and determines the sign of the error when counting a given number of periods of the oscillation range of the oscillator.

To solve the following technical means:

- offer DPKG based on multi-bit synchronous counter pulses in the gray code parallel preset initial data, the final state which, after counting the current number of vibrations is converted into a control on customizability elements of the resonator when locked loop frequency generator up to par;

to specify the duration of T0the measuring interval in the product introduced its own DFCD, clocked by the pulses of the external oscillator reference frequency by increments of 1/f0and for accurate filling of the measuring interval increments of 1/fxthe analyzed frequency fxapplied managing RS-trigger simultaneously opening inputs DFCD and DPKG output pulses with a duration of T0;

- to accelerate the occurrence of the generator in synchronism after the write control code generation frequency fxbefore enabling its measurement, with a valid pre-tichina from a set of items into a cavity.

At a constant duration T0the measuring interval, the number of Nxperiods of oscillations counted during the measurement, in proportion to the generation frequency fx:

Nx=T0fx; Nhmax=T0fmax; NHmin=T0fHmin; Nx= Nmax-Nmin.

The tuning range of the frequency F = fmax-fminwith a margin at the edges and a natural instability corresponds to the difference N = Nmax-Nmin..

After counting during the measurement of the actual number of oscillations with a period 1/fxiorder (n-1)-(m-l) JK-flip-flops high-order bits DPKG pass into the state of a logical zero, the n-th JK flip-flop is in the state of the logical unit, and JK-triggers least significant bits from the first to the (m-l)-th register of the residual to the gray code, a numeric value corresponding to the natural instability frequency generator is used to convert the control actions on the parameters of the resonator of the oscillator.

The absolute value of the information capacity of the m-l named JK-flip-flops of the counter pulses in the 2m-l-1 units of account corresponds to the decimal equivalent of the code, the maximum value of the natural detuning hour the national scheme operated generator with a preset frequency; in Fig. 2 detailed functional diagram DPCD (element 19 of Fig. 1), and Fig. 3 detailed functional diagram DPKG (element 4 of Fig. 1), and Fig. 4 temporal correlation, explaining the process control podstrony frequency oscillator G (element 1 of Fig. 1), and Fig. 1a - slice temporal relation that explains the formation of the pulse at the output DPCD in the moment "reflections" account in the pulse counter when the current value of fxithe oscillation frequency exceeds the nominal fHN.

The device (Fig. 1) contains, United in ring 1, the oscillator G electrical oscillations with p-input accumulating 1.1 bus discrete commands and 1.2 analog input signal 2 output bus fxthe frequency of oscillations connected to the input 3 of the driver pulses with a period 1/fxwhose output is connected to the C input of the synchronization divider 4 with variable division factor (DPCD), the element hi OR NOT 6 with m-vchodove 5 gray code Converter in a positional binary code (MPC), which has m outputs bitwise connected to the m inputs of Bj-group input m-bit adder 7 MPC, m outputs which bitwise connected to the m inputs of the m-bit 8 register MAC, which l outputs high-order bits bitwise connected the La, and m-l output least significant bits of the m-bit register MAC bitwise connected to m-l inputs 9.2 Converter MAC-voltage, which is the second element of functional Converter 9, p output element which is connected to the inputs p input accumulating 1.1 bus discrete commands 1 oscillator G electrical oscillations, analog 1.2 input connected to the output 9.2 Converter MAC-voltage, and n Diinputs preset DPKG bitwise connected to n outputs 12 Converter MAC in the gray code, n inputs which bitwise connected to n outputs of the buffer 11 of the register and with n inputs ANDigroup inputs 13 schema subtraction, in which m code outputs the difference between Aiminus Bibitwise connected to the m inputs of Aj-group input m-bit adder 7 MPC, and n inputs Bi-group input schema subtraction bitwise connected to the corresponding outputs n-bit 14 bus reverse MPC boundary fminthe oscillation frequency and C0 is the carry-in input schema subtraction connected to the bus logic unit, and outputs n-bit 10 bus Manager MAC bitwise connected to the respective n inputs buffer register from which the output of the first discharge MAC connected to the input of improvisatie buffer register connected to the output of the detector 16 of the front trigger pulse, whose input is connected to the bus 15, "Start", the output of the detector front trigger pulse is also connected to the input of the first 17 of delay elements, the output of which is connected to PE-input supised and with the second input 18 of the delay elements, the output of which is connected with R-reset input 19 of the divider with a fixed division factor (DPCD) and third input 22 of the delay elements, the output of which is connected to the input set of the first 23 RS-flip-flop, a second input set 24 RS-flip-flop and the first input 26 of the element ELI IS NOT inverted logic the output of which is connected with C-synchronization input m-bit register MAC, and the second input is connected to the fourth output 25 of the delay element, the input of which is connected to the reset input DFCD and to the output of the first reset 23 RS-flip-flop, and C-sync-DFCD connected to the output of the inverter 20, the inlet of which is connected to the signal bus 21 pulses f0the reference frequency, while, according to the invention, DPCD (Fig. 2) made in the form of r-bit synchronous counter pulses in the gray code, which JK-entry permit account DFCD connected to the J - and K-inputs of zero 2.3.0 JK-flip-flop, a direct output of which is connected to the second input of the first 2.5.1 element 2I IS NOT inverted logic miratransas with the .1 JK-flip-flop, direct the output of which is connected to the j - and k-inputs of the second 2.3.2 JK-flip-flop and the first input of the second 2.5.2 element 2I IS NOT inverted logic miratransas communication and first 2.4.1 element 2I IS NOT inverted logic end-to-end transfer, a second input connected to the direct output of the second 2.3.2 JK-flip-flop and the output to the first input of the third 2.5.3 element 2I miratransas connection, the output of which is connected to the J - and K-inputs of the fourth 2.3.4 JK-flip-flop and the second input - direct 2.3.3 third JK flip-flop J - and K-inputs of which are connected with the output of the second 2.5.2 element 2I IS NOT inverted logic miratransas connection, the second input is connected to the inverse output of the second 2.3.2 JK-flip-flop, and direct the fourth 2.3.4 JK-flip-flop is connected to the J - and K-inputs of the fifth 2.3.5 JK-flip-flop and the inverted output is connected to the first inputs of the second 2.4.2 element 2I through migration and fourth 2.5.4 element 2I miratransas connection, the output of which is connected to the J - and K-inputs of the sixth 2.3.6 JK-flip-flop, and the second input is connected to the direct output of the fifth 2.3.5 JK-flip-flop inverted output of which is connected to the second input of the second 2.4.2 element 2I end-to-end transfer, the output of which is connected with the first inputs of the fifth 2.5.5 element 2I miratransas communication and third 2.4.3 element vertigo element 2I through migration,..., and output (r-5)-th 2.4. r-5 element 2I through transfer connected to the first input (r-2)-th 2.5.r-2 element 2I miratransas connection, a second input connected to the direct output (r-1)-th 2.3.r-1 JK-flip-flop, and the output connected to the J - and K-inputs of the r-th 2.3.r JK-flip-flop, C-inputs synchronization zero 2.3.0 JK-flip-flop and the first 2.3.1 JK-flip-flop connected to the output of the logical 2.1 inverter, whose input is connected to the C input synchronization DFCD, with the first input of the first 2.2.1 element 2I IS NOT inverted logic and to the first input of the second 2.2.2 element 2I IS NOT inverted logic, the output of which is connected to the C inputs of the synchronization r-4 JK-flip-flops from the fifth 2.3.5 JK-flip-flop on the r-th JK flip-flop and a second input connected to the output of 2.6 element 4I, the first input of which is connected to the direct output of the zero 2.3.0 JK-flip-flop, and the second, third and fourth inputs respectively connected to the inverted outputs of the first 2.3.1, the second 2.3.2 and 2.3.3 third JK-flip-flops, the second input of the first element 2I IS NOT inverted logic connected to the inverse logic is connected to an inverted yield zero 2.2.0 JK-flip-flop and the output of the C-inputs of the synchronization of the second 2.3.2, 2.3.3 third and fourth 2.3.4 JK-flip-flops, and the output of the (r-1)-Vodolaga 2.7 decoder connected to the first input 2.9 element 2I and to the first input pen is slowage equivalent to Kjthe division factor that is connected to the direct output of the i-th JK-flip-flop when the values of Kj= 2i-1(1+4j), where j=1,2,..., or to invert the output of the i-th JK-flip-flop when the values of Kj=2i-1(3+4j), where j=0,1,2,..., and the inputs (r-1)-Vodolaga decoder connected to direct or inverted outputs of the remaining r-1 JK-flip-flops in accordance with bitwise written gray code, the numeric equivalent of which is equal to an integer equivalent to Kjthe division factor, and the first input of the second group of inputs 2I element hi OR NOT connected to the R input of the reset DFCD, and the output element hi OR NOT connected to the reset inputs r+1 JK-flip-flops with zero 2.3.0 JK-flip-flop on the r-th 2.3.r JK flip-flop and the output 2.9 element 2I IS NOT connected to the output of the reset DFCD, which JK-entry permit account DFCD connected with JK-entry permit account DPKG (Fig. 3) and is connected to the direct output of the first 23 RS-flip-flop inverted output of which is connected to the input of account management DFCD and login account management DPKG, which is made in the form of n-bit synchronous counter pulses in the gray code, which JK-entry permit account DPKG connected to the J - and K-inputs of zero 3.3.0 JK-flip-flop, a direct output of which is connected to the second input of the first 3.5.1 item 2I-NO inverter is Yong J - and K-inputs of the first 3.3.1 JK-flip-flop, direct the output of which is connected to the J - and K-inputs of the second 3.3.2 JK-flip-flop, the first input of the second 3.5.2 element 2I IS NOT inverted logic miratransas communication and first 3.4.1 element 2I IS NOT inverted logic end-to-end transfer, a second input connected to the direct output 3.3.2 second JK-flip-flop and the output to the first input of the third 3.5.3 element 2I miratransas connection, the output of which is connected to the J - and K-inputs of the fourth 3.3.4 JK-flip-flop and the second input - direct 3.3.3 third JK flip-flop J - and K-inputs of which are connected with the output of the second 3.5.2 element 2I IS NOT inverted logic miratransas connection, the second input is connected to the inverse output of the second 3.3.2 JK-flip-flop, and direct the fourth JK-flip-flop is connected to the J - and K-inputs of the fifth 3.3.5 JK-flip-flop and the inverted output is connected to the first inputs of the second 3.4.2 element 2I through migration and fourth 3.5.4 element 2I miratransas connection, the output of which is connected to the J - and K-inputs of the sixth 3.3.6 JK-flip-flop, and the second input is connected to the direct output of the fifth 3.3.5 JK-flip-flop inverted output of which is connected to the second input of the second 3.4.2 element 2I end-to-end transfer, the output of which is connected with the first inputs of the fifth 3.5.5 element 2I miratransas communication and third 3.4.3 element 2I, squeo element 2I through migration. . ., and the output of the (n-5) th 3.4.n-5 element 2I through migration is connected with the first input of the (n-2)-th 3.5.n-2 element 2I miratransas connection, a second input connected to the direct output of the (n-1)-th 3.3.n-1 JK-flip-flop, and the output connected to the J - and K-inputs of the n-th 3.3.n JK-flip-flop, C-inputs synchronization zero 3.3.0 JK-flip-flop and the first 2.3.1 JK-flip-flop connected to the output of the logical 3.1 inverter, whose input is connected to the C input synchronization DPCD, with the first input of the first 3.2.1 element 2I IS NOT inverted logic and to the first input of the second 3.2.2 element 2I IS NOT inverted logic, the output of which is connected to the C inputs of the synchronization n-4 JK-flip-flops from the fifth 3.3.5 JK-flip-flop n-th 3.3. n JK flip-flop and a second input connected to the output of the second 3.6.2 element 4I, the first input of which is connected to the direct output of the zero 3.3.0 JK-flip-flop, a second input connected to the inverse output of the first 3.3.1 JK-flip-flop, a third input connected to the inverse output of the second 3.3.2 JK-flip-flop, the fourth input is connected to an inverted output of the third 3.3.3 JK-flip-flop and the third input of the first 3.6.1 element 4I, the output of which is connected to the output switching accounts DPCD, and the first input is connected to the second input of the second element 2 IS NOT inverted logic and with an inverted yield zero 3.3.0 JK-flip-flop, the second to the fourth output is connected to the output of the third 3.2.3 element 2I IS NOT inverted logic first input connected to the output of the third 3.8 element 4I, the second input - output (n-7)-Vodolaga 3.9 item AND IS NOT, in which n-3 input bit is connected to the inverted outputs n-4 JK-flip-flops from the fourth 3.3.4 JK-flip-flop (n-1)-th 3.3 n-1 JK flip-flop and direct access to the n-th 3.3.n JK-flip-flop DPCD, and PE-input recording DPKG connected to the first inputs of the elements 2I-n+1 3.7.0,...,3.7.n logical pairs of elements 2I, in which n direct signal outputs bitwise connected to the inputs installations n JK-flip-flops with zero 3.3.0 JK-flip-flop (n-1)-th 3.3.n-1 JK flip-flop, and n inverted signal outputs bitwise connected with their reset inputs in the named sequence, and the direct signal output of the n-th 3.7.n logical pairs of elements 2I-NOT connected to the reset input of the n-th 3.3.n JK-flip-flop and an inverted signal output connected to its input setup, and the signal input of the first element 2I IS NOT zero 3.7.0 logical pairs of elements 2I-NOT connected to the D0 input of the preset DPCD, and the signal inputs of the first elements 2I-n 3.7.1,...,3.7.n logical pairs of elements 2I-NOT bitwise connected to respective Diinputs preset DPCD first to n-th, and the output of the first element 2I IS NOT inverted logic connected to the C output of the second synchronization 24 RS-flip-flop, inverted output of which is connected to a C0-carry-in input m-bit adder 7 MPC and to the first input of the first 2 groups of inputs 6 item he OR NOT, the second input of which is connected to the direct output of the m-th JK-flip-flop DPCD, and the first input of the second 2 groups of inputs of the element hi OR NOT connected to the direct output of the second 24 RS-flip-flop, a second input which is connected to an inverted output of the m-th JK-flip-flop DPCD, and the output element hi OR NOT connected to the input of the older m-th digit 5 of the gray code Converter MAC, m-1 inputs which bitwise connected to the corresponding inputs of the output signal 3.10 bus DPKG (Fig. 3), Q1-the output of which is connected to the direct output of the first 3.3.1 JK-flip-flop, Q2output-direct access 3.3.2 second JK-flip-flop,..., Qioutput-direct access to the i-th JK-flip-flop,..., Qm-1output-direct access (m-1)-th JK flip-flop and Qmoutput-direct access to m-th JK-flip-flop, and the output to its inverted output. Items 1, 3, 4, 5, 6, 7, 8 and 9 connected in a ring, ensure the lock to the nominal value of the oscillation frequency of the tuning range in accordance with the numerical equivalent of the control values for the signal 10 to the control bus.

The ring-locked loop is provided a device with the consumer and with external devices synchronization and control.

The interim discriminator performs n-bit DPCD, counting for time T0the number of Nx= To(fn-fxperiods of 1/fxfluctuations different from the face value of Nn= T0fnand defining in conjunction with the elements 24, 6 and 5 splat.

When describing the operation of the DEVICE (Fig. 1, 1a and 4) dealt with both cases compensate for the detuning:

fxi<fwhen the original numeric equivalent of Nnadded amendment Nxand fxi>fHNwhen it is subtracted from it.

The operation of the device (Fig. 1, 1a, 2, 3 and 4) is described on the example of the functional diagram (Fig. 1) with the 15-bit r=15 DFCD 19 and 15 bit n=15 DPCD 4, m-1, if m=13, the elements of which after the end of the current cycle of the invoice and prior to the next residual code number of oscillations differing from the nominal values, the numeric equivalent of which does not exceed 2m-l-1 units of account.

For this purpose, the tire 21 is continuously output pulses of the reference frequency with a period 1/f0on the bus 10 before each startup receives n-bit MAC nominal fHNthe values of the oscillation frequency from the range of fhmax-fHminrealignment and s which Nminless NHmin2m-l-1 units of account.

Before receipt of the first pulse start Ref.16 (Fig. 4.1) on the output bus 2 are continuous periodic oscillations with frequency fxinatural instability which corresponds to the numeric value of the residual code in m-l lower bits of the m-bit register 8 (Fig. 1), from which the number l senior level, depending on the information capacity of the 2n-1 DPCD and discrete adjustment f is from 2 to 8 units.

In this case n outputs of the elements 11 and 12, the m outputs of the elements 13 and 7, m outputs of the elements 4, 5, 7 and 8, the outputs of the elements 9.1, 23 and 24, r counting elements DFCD 19 are in an indeterminate state (a logical zero or one), C-inputs of the synchronization elements 4 and 19, the outputs of the elements 22 and 25 are in the state of the logical unit, and the output element 26 in the state of the logical zero.

The positive pulse Output.16 (Fig. 4.2), corresponding to the front first and then the subsequent pulse start Ref.16 (Fig. 4.1), when C-synchronization input buffer register 11, performs a bitwise write n-bit code of the oscillation frequency fHN, which, with its n Qioutputs bitwise goes on n inputs Aigr is setting PDCD with outputs n-bit Converter 12 MAC in the gray code B/G. The positive pulse Output.16, a detainee at time t1(O. 17, Fig. 4.4), with the output element 17, when the PE input recording DPCD, produces a parallel record of the original data into n+1 elements account DPCD, and delayed for a time t2(O. 18, Fig. 4.6) element 18 produces an initial count of pulses in the composition DFCD 19 preparing it for the exact calculation of the duration of T0dimensional interval with zero reference. The positive pulse from the output element 18 (O. 22, Fig. 4.8), a detainee at time t3doing with the output element 22 to the input of the installation of the first 23 RS-flip-flop, sets its status to "unit", allowing the counting of pulses with a period 1/f0elements DFCD and with the period 1/fxelements DPCD when their JK inputs with direct output of the first RS-flip-flop 23 has received a positive pulse T0the measuring interval, and the control inputs of the negative phase of T0with its inverted output, the duration of which is limited to the front negative pulse output. 19 Fig. 4.12 received at the reset input of RS flip-flop 23 from the output of the reset DFCD 19 in the end of the counting pulses of the reference frequency (Fig. 4.9-4.12).

The Pulse Output. 22, also received on the input set is law with period 1/fxiduring the measurement fxiwill be less than the nominal period of 1/fHNwhen fxi<f. This positive differential L/H with a direct output of the second RS flip-flop 24 is received at the first input element 6, and the negative H/L with inverted output of the received C0-input transfer element 7 and the third input element 6, after the termination of the account by the pulse output.19 Fig. 4.12 provide a summation of the m-bit values for the inputs Ajgroup of inputs of the element 7 with direct exposure to the inputs Bjgroup of inputs, the resulting podrazdelnoe conversion of residual gray code position code, the high level output DPKG 4 to the input of senior level element 5 through the second input group 2 element 6 with inversion at the output.

If the current number of pulses with a period 1/fxiwill be more than nominal, corresponding to complete filling of the counting cells DPCD, at the moment of transition from the direct account to reflected (Fig. 4.13, 4.14) at the output of the switching account negative pulse (Fig. 4.15) with duration of 1/fxi, the front of which switches the second 24 RS-trigger in an inverted ("zero") the state of the reset input, reconstructing the adder codes 7 on visitando, received after bitwise conversion of residual gray code position code with connections high level inverted output of the RS flip-flop 24 to the C0 input of the adder codes and to the third input element 6, and a low level of Qmoutput DPKG through the fourth input element 6, with subsequent inversion to the input of senior level item 5.

Parametric frequency control of the oscillator G1 is due to changes in the quantity equivalent to the capacity of its resonator.

The value of fminmatch CEQ.maxin almost constant values of LEQ.and REQ.in the tuning range.

Each nominal frequency fxigenerating an equivalent capacitance of the resonator CEQ.i=Cm+C* +Csubjectconsisting of: Cmthe distributed capacity of the installation, C* - focused capacity switchable elements, Csubjectparametric capacity of the managed element.

To obtain the necessary values of CEQ.icode combination high-order bits of register MAC 8, when l potential inputs of decoder 9.1, selects the appropriate command from the p set at its output, Ecevit initial offset frequency fxifrom fmin. Finally detuning fxicaused by natural instability elements of the oscillator G1, numeric equivalent of which does not exceed the capacity of m-l least significant bits of register MAC, bitwise connected with inputs of functional Converter B/U 9.2 compensated when locked loop, resulting in the bias voltage from the output element 9.2 adjusts the transfer capacity to the required values of Csubject.

At a known time increment adjustment fxand boundary frequency range, it is easy to get simple calculation of the ratio of CEQ.ifor each of the denominations of fxifrequency generation:

< / BR>
Nxi=fxiT0;

< / BR>
nlog2Nmax;

2n-1<N max<2 n-1;

Nmin=Nmax-(2m-1);

mlog2(Nmax-Nmin+1);

fxi= fmin+fi;

< / BR>
< / BR>
The actual numeric value of the error signal corresponding to the m-bit gray code for Q1,...,Qm-1and Qmthe outputs of the cells of the pulse counter DPKG 4 Fig. 1, is calculated after the initial data received his Diinputs, and calculating the actual number of periods to colemam cycle when switching RS-flip-flop 23 to the zero state. With the arrival of the pulse Output.17 Fig. 4.4 at the PE the entrance DPKG 4 Fig. 1, in the zero 3.3.0 JK flip-flop pulse counter records the state of the first discharge MPC fxiwith 1pBK output buffer register 11, and n 3.3.1...3.3.n JK-flip-flops, starting with the first 3.3.1, Di-inputs bitwise written addition to (2n-1) the numerical values of the n-bit gray code current value of the frequency fxithat is different from the original values coming from the n outputs of the Converter B/G 12 only inverted condition of the older n-th digit of the code.

The simplification of the recording is achieved by cross-input logical "zero" or "unit" or the inputs of the n-th 3.3.n JK-flip-flop pulse counter DPKG Fig. 3.

When occitanie to (2n-1) the required number of periods of oscillation 1/fxithere is a partial, if fxi<ffill the cells of the pulse counter DPKG 4 or the excess, if fxi>fHN(see table).

Numeric value (m-l) least significant bits XXX...X residual gray code corresponds to the absolute value of the error signal that is converted in the control action on the parameters of the resonator of the oscillator.

In the described generator (Fig. 1) through the proposed building D>ioscillator G1, simultaneous computation of the absolute value of the error signal, and determining the sign of the detuning, that with limited dimensional interval T0allows to improve the performance of the device by eliminating the additional computational operations.

References

1. Levin, A. A. and other frequency Synthesizers system IFAP. - M: Fig. 1989. S. 14, Fig. 1.3, UDC 621.396.662.

2. BRD, Int. Cl2H 03 B 3/04, (11) 2163971, (73) Siemens AG 1000 Berlin und 8000 Munchen, (54) Schaltung zur digitalen Frequenzeinstellung..., (72) Karl Schlosser, (Translation. cassette GOR 2/To 108).

A controllable oscillator with a preset frequency, containing United in the ring oscillator G electrical oscillations with p-input accumulating bus discrete commands and analog input, the signal output bus fxthe frequency of oscillations connected to the input of the shaper pulses with a period 1/fxwhose output is connected to the C input of the synchronization frequency divider with variable division factor (DPCD), 2 x 2I-OR-NOT with m-vchodove the gray code Converter in a positional binary code (MPC), which has m outputs bitwise connected to the m inputs of Bjgroup input m-bit adder MAC, m outputs which bitwise connected to vhodnogo decoder, which is the first element in the functioning of the Converter, and m - l output least significant bits of the m-bit register MAC bitwise connected to m - l inputs of the Converter MPC - voltage, which is the second element in the functioning of the Converter, p output element which is connected to the input p-input accumulating tires discrete commands oscillator G electrical oscillations, an analog input connected to the output of the Converter MPC - voltage, and n Diinputs preset DPKG bitwise connected to the outputs of the Converter MAC in the gray code, n inputs which bitwise connected to n outputs of the buffer register and with n inputs Aigroup inputs schema subtraction, in which m code outputs the difference between Aiminus Bibitwise connected to the m inputs of Ajgroup input m-bit adder MAC, and n inputs Bigroup inputs schema subtraction bitwise connected to the corresponding outputs n-bit bus reverse MPC boundary fminthe frequency of oscillations, and CO is the carry-in input schema subtraction connected to the bus logic unit, and outputs n-bit bus control MPC discharge connected to the respective n inputs buffer register from which you is sustained fashion is connected to the DO input of preset DPCD, and C-synchronization input buffer register connected to the output of the detector front trigger pulse, the input of which is connected to the bus "Start", the output of the detector front trigger pulse is also connected to the input of the first delay element, the output of which is connected to PE-input recording DPCD and with the input of the second delay element, the output of which is connected with R-reset input of the divider with a fixed division factor (DPCD) and to the input of the third delay element whose output is connected to the input set of the first RS-flip-flop, with the input set of the second RS-flip-flop and the first input element ILI IS NOT inverted logic, the output of which is connected with C-synchronization input m-bit register MAC, and the second input is connected to the output of the fourth delay element, the input of which is connected to the output of the reset DFCD and to the reset input of the first RS-flip-flop, and C-sync-DFCD connected to the output of the inverter, whose input is connected to the signal bus of pulses f0the reference frequency, wherein DFCD made in the form of r-bit synchronous counter pulses in the gray code, which JR-entry permit account DFCD connected to the J - and K-inputs of zero JK-flip-flop, a direct output of which is connected to the second input of the ia account DFCD, and the output connected to the J and K inputs of the first JK-flip-flop, and the outlet of which is connected to the J - and K-inputs of the second JK-flip-flop and the first input of the second element 2 IS NOT inverted logic miratransas connection and the first element 2I IS NOT inverted logic end-to-end transfer, a second input connected to the direct input of the second JK-flip-flop and the output to the first input of the third element 2I miratransas connection, the output of which is connected to the J - and K-inputs of the fourth JK-flip-flop, and the second input - direct the third JK flip-flop J - and K-inputs of which are connected with the output of the second element 2 IS NOT inverted logic miratransas connection, the second input is connected to the inverse output of the second JK-flip-flop, and direct the fourth JK-flip-flop is connected to the J - and K-inputs of the fifth JK-flip-flop and the inverted output is connected to the first inputs of the second element 2I through migration and the fourth element 2I miratransas connection, the output of which is connected to the J - and K-inputs of the sixth JK-flip-flop, and the second input is connected to the direct output of the fifth JK-flip-flop inverted output of which is connected to the second input of the second element 2, AND end-to-end transfer, the output of which is connected with the first inputs of the fifth element 2I miratransas communication and the third element 2I

buffer of net element 2I through migration, . . . and output (r - 5)-th element 2I through transfer connected to the first input (r - 2)-th element 2I miratransas connection, a second input connected to the direct output (r - 1)-th JK-flip-flop, and the output connected to the J - and K-inputs of the r-th JK-flip-flop, C-inputs synchronization zero JK-flip-flop and the first JK-flip-flop connected to the output of the logical inverter, whose input is connected to the C input synchronization DFCD, with the first input of the first element 2I IS NOT inverted logic and to the first input of the second element 2 IS NOT inverted logic, the output of which is connected to the C inputs of the synchronization r - 4 JK-flip-flops from the fifth JK flip-flop on the r-th JK flip-flop and a second input coupled to the output element 4I, the first input of which is connected to the direct output of the zero-JK-flip-flop, and the second, third and fourth inputs respectively connected to the inverted outputs of the first and second JK-flip-flops, the second output of the first element 2I IS NOT inverted logic connected to the inverse output of the zero-JK-flip-flop and the output of the C-inputs of the synchronization second, third and fourth JK-flip-flops, and the output of the (r - 1)-Vodolaga decoder connected to the first input element 2I and to the first input of the first group of inputs of the element 2I 2 2I-OR-NOT, the second input and the second input element 2 is trigger when the values of Kj= 2i-1(1 + 4j),

where j = 1, 2 ..., or to invert the output of the i-th JK-flip-flop when the values of Kj= 2i-1(3 + 4j), where j = 0, 1, 2 ..., and the inputs (r - 1)-Vodolaga decoder connected to direct or inverted outputs of the remaining r - 1 JK-flip-flops in accordance with bitwise written gray code, the numeric equivalent of which is equal to an integer equivalent to Kjthe division factor, the first input of the second group of inputs of the element 2 x 2I-OR-NOT connected to the R input of the reset DFCD, and the output element 2 x 2I-OR-NOT connected to the reset inputs r + 1 JK-flip-flops with zero JK-flip-flop on the r-th JK flip-flop, the output of the element 2I IS NOT connected to the output of the reset DFCD, which JK-entry permit account DFCD connected with JK-entry permit account DPCD and connected to the direct output of the first RS-flip-flop, inverted output of which is connected to the input of account management DFCD and login account management DPKG, which is made in the form of n-bit synchronous counter pulses in the gray code, which JK-entry permit account DPKG connected to the J - and K-inputs of zero JK-flip-flop, a direct output of which is connected to the second input of the first element 2I IS NOT inverted logic miratransas connection, the first input of which is connected to the input of the account management DPCD, and expressed, to the first inputs of the second element 2 IS NOT inverted logic miratransas connection and the first element 2I IS NOT inverted logic end-to-end transfer, a second input connected to the direct output of the second JK-flip-flop and the output to the first input of the third element 2I miratransas connection, the output of which

connected to the J - and K-inputs of the fourth JK-flip-flop and the second input - direct the third JK flip-flop J - and K-inputs of which are connected with the output of the second element 2 IS NOT inverted logic miratransas connection, the second input is connected to the inverse output of the second JK-flip-flop, direct fourth JK-flip-flop is connected to the J - and R-input of the fifth JK-flip-flop and the inverted output is connected to the first inputs of the second element 2I through migration and the fourth element 2I miratransas communication the output of which is connected to the J - and K-inputs of the sixth JK-flip-flop and the second input is connected to the direct output of the fifth JK-flip-flop inverted output of which is connected to the second input of the second element 2, AND end-to-end transfer, the output of which is connected with the first inputs of the fifth element 2I miratransas communication and the third element 2I end-to-end transfer, the output of which is connected with the first inputs of the sixth element 2I miratransas connection and the fourth of elelement 2I miratransas communication a second input connected to the direct output of the (n - 1)-th JK-flip-flop, and the output connected to the J - and K-inputs of the n-th JK-flip-flop, C-inputs synchronization zero JK-flip-flop and the first JK-flip-flop connected to the output of the logical inverter, whose input is connected to the C input synchronization DPCD, with the first input of the first element 2I IS NOT inverted logic and to the first input of the second element 2 IS NOT inverted logic the output of which is connected to the C inputs of the synchronization n - 4 JK-flip-flops from the fifth JK-flip-flop n-th JK flip-flop and a second input connected to the output of the second element 4I, the first input of which is connected to

direct zero-JK-flip-flop, a second input connected to the inverse output of the first JK-flip-flop, a third input connected to the inverse output of the second JK-flip-flop, the fourth input is connected to an inverted output of the third JK flip-flop and the third output of the first element 4I, the output of which is connected to the output switching accounts DPCD, and the first input is connected to the second input of the second element 2 IS NOT inverted logic and with the inverse of the zero output of the JK-flip-flop, the second input of the first element 4I IS NOT connected to the output of the first element 2I IS NOT inverted logic through migration, and the fourth input is connected to the output of the third element 2I-N 7)-Vodolaga element AND-NOT, have n - 3 input bit is connected to the inverted outputs n - 4 JK-flip-flops from the fourth JK-flip-flop (n - 1)-th JK flip-flop and direct access to the n-th JK-flip-flop DPCD, PE-input recording DPKG connected to the first United inputs n + 1 logical pairs of elements 2I, in which n direct signal outputs bitwise connected to the inputs of the set n JK-flip-flops with zero JK-flip-flop (n - 1)-th JK flip-flop and n inverted signal outputs bitwise connected with their reset inputs in the named sequence, direct the signal output of the n-th logical pairs of elements 2I-NOT connected to the reset input of the n-th JK-flip-flop and an inverted signal output is connected with its input set signal input of the first element 2I IS NOT logical zero pairs of elements 2I-NOT connected with DO-entrance preset DPCD, and the signal inputs of the first elements 2I-n logical pairs of elements 2I-NOT bitwise connected to respective Diinputs preset DPCD with first through n-th output of the first element 2I IS NOT inverted logic connected to the C inputs of the synchronization second, third and fourth JK-flip-flops, the output of the switching accounts DPKG connected to the reset input of the second RS flip-flop inverted output of which is connected to CO-carry-in input m-razran direct m-th JK-flip-flop DPCD, and the first input of the second 2 groups of input element 2 x 2I-OR-NOT connected to the direct output of the second RS-flip-flop, a second input which is connected to an inverted output of the m-th JK-flip-flop DPCD, the output element 2 x 2I-OR-NOT connected to the input of the older m-th bit of the gray code Converter in PKD, the remaining m - 1 inputs which bitwise connected to the corresponding m - 1 inputs the output signal bus DPCD, Q1-the output of which is connected to the direct output of the first JK-flip-flop, Q2output to the direct output of the second JK-flip-flop . . ., Qioutput-direct access to the i-th JK-flip-flop, Qm-1output-direct access (m-1)-th JK-flip-flop-output - direct access to m-th JK-flip-flop, and output-to its inverted output.

 

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The invention relates to electronics and can find application in devices for generating a voltage sine wave, for example, as local oscillators for frequency converters or frequency synthesizers kalogiratou and low-frequency ranges

Frequency divider // 2292630

FIELD: electrical and radio engineering; locked-mode sources for transceivers.

SUBSTANCE: proposed frequency divided has transformer, capacitor, inductance coil, semiconductor diode, transistor, integrating circuit, and bias circuit incorporating series-connected bias voltage supply and resistor.

EFFECT: extended operating frequency range toward higher frequencies, facilitated manufacture.

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FIELD: physics, radiotechnics.

SUBSTANCE: the synthesiser contains a frequency selection device, the outputs of which are connected to the first input of the first N-bit adder and the second input of the second N-bit adder, as well as a clock oscillator and a frequency halver connected in series, the outputs of which are connected to the third and second inputs of the first, second, and third shift registers, respectively. The output of the first register is connected to the first input of the second adder, the output of which is connected to the first input of the second register, to the first input of the third shift register, and the second input of the first adder, the output of which is connected to the first input of the first register. The output of the third register, through the first read-only memory (ROM) device, and the output of the second register, through the second ROM, are connected, respectively, to the first and second inputs of the multiplexer, the output of which is connected to a digital-to-analogue converter. The frequency halver output is connected to the third input of the multiplexer.

EFFECT: increase in maximum sine wave signal frequency by two.

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FIELD: measurement equipment.

SUBSTANCE: generator of a sinusoidal signal comprises an N-digit summator, N-digit phase accumulator, a permanent memory, a digital-analogue converter, a device to generate a code of frequency of a generated signal F with capacity (N+M), a clock pulse oscillator, a device for conversion of a code of frequency of a generated signal F into a code of phase increment Δφ and into a code of clock frequency K in accordance with specified mathematical ratios of parameters.

EFFECT: expansion of a frequency range with preservation of summator and phase accumulator capacity and volume of permanent memory.

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