Field-effect transistor

 

(57) Abstract:

Usage: field-effect transistors with threshold Fermi. The essence of the invention: an improved field-effect transistor Fermi with small diffusion capacitance and gate capacitance, in which the charge carriers can move inside the channel at a certain depth in the substrate under the gate, the semiconductor surface is not required to create an inversion layer. To create a field-effect transistor Fermi small containers it is desirable to use a pocket Fermi, having a certain depth, conductivity type which is opposite to the conductivity type of the substrate and of the same conductivity type diffusion regions for forming drain and source. The technical result of the invention is to provide an improved field-effect transistor with a threshold Fermi with reduced diffusion capacity and the gate capacitance. 11 C.p. f-crystals, 24 ill.

The technical field to which the invention relates

This invention relates to field effect transistors, and more particularly it relates to field-effect transistors with threshold Fermi with reduced gate and diffusion capacitance.

Art

Currently polyvisol integration (ULSI), as they are by their nature have a high impedance and provide a high packing density and low power consumption. However, the efforts of researchers and developers focus on further improving their performance and increasing packing density and to reduce the consumption of power.

Known for high-PT with the structure of a metal-oxide-semiconductor (MOS), the threshold voltage of which does not depend on the thickness of the insulating layer, the channel length, voltage, flow, substrate doping and temperature, allowing for high-speed field-effect transistor (see U.S. patents NN 4984043 and 4990974, issued in the name Albert W. Vinal, entitled "Field effect transistor with a threshold Fermi). Although created field-effect transistor with a threshold Fermi much better than standard MOSFETs, still in the structure of the field-effect transistor with a threshold Fermi desirable to reduce the capacity.

Known also operating in the depletion mode field-effect transistor, whose area between the source and drain region includes a depletion region of the same conductivity type, and area between the source and drain region includes an additional semiconductor region of the same type providemore

Achievable with the implementation of the present invention the technical result is the creation of an improved field-effect transistor with a threshold Fermi with reduced gate and diffusion capacitance.

This problem is solved due to the fact that the field-effect transistor-containing semiconductor substrate of the first conductivity type with the first surface, the pocket region of the second conductivity type in the substrate at the first surface, spaced areas of the source and drain of the second conductivity type in the area of the pocket at the first surface, the insulating layer of the gate on the substrate on the first surface between the spaced regions of the source and drain contacts and source, drain and gate for electrical contact areas of the source and drain and the insulation layer of the gate, respectively, according to the present invention further comprises a channel of the second conductivity type in the area of the pocket at the first surface between the spaced regions of the source and drain. The specified channel conductivity takes place on the first a certain depth from the first surface and the area of the pocket is held on the second certain depth from the channel. Region of origin is held on the third certain depth from PE

Perhaps the doping of the source impurity of the second conductivity type at a dopant concentration decreasing from the first surface to the third predetermined depth. In this case, it is preferable that the center of mass of the dopant is at a depth equal to half the first predetermined depth.

It is advisable to select at least one of the defined first and second depths so that the component of the electric field is perpendicular to the first surface, at first a certain depth was equal to zero.

It is preferable that at least one of the defined first and second depths are additionally selected so that the component of the electric field is perpendicular to the first surface, the first predetermined depth to the first surface by applying a threshold voltage to the contact stopper was equal to zero.

The second is a certain depth may be chosen to create such a threshold voltage of the field-effect transistor, which is equal to twice the Fermi potential of the semiconductor substrate.

It is also possible to select at least one of the defined first and second depths such that charge carriers vtorostepenny depth to the first surface for attachment to the contact of the gate voltage, above the threshold voltage of the FET.

At least one of the defined first and second depths can be selected such that charge carriers of the second conductivity type can move within the channel region of the source to drain under the first surface without creating an inversion layer in the channel.

It is also advisable to provide a substrate electrical contact. In this case, the contact shutter contains a layer of polycrystalline silicon of the first conductivity type and a gate electrode on the layer of polycrystalline silicon against the gate insulating layer, and at least one of the defined first and second depths are selected to establish a voltage on the first surface adjacent to the insulating layer of the gate that is equal and opposite in sign to the sum of the voltage between the contact substrate and the substrate and between the layer of polycrystalline silicon and the gate electrode.

Preferably, the substrate was provided with an electric contact, and at least one of the first and second specific depths selected to change the threshold voltage field-effect transistor is less than one dwadle also doping the substrate with a dopant concentration of the Ns. In this case, the substrate has its own concentration of charge carriers Niat temperature T degrees Kelvin and a permittivity es. Field-effect transistor includes an electrical contact of the substrate, and the channel it is on the first a certain depth Yffrom the first surface and the area of the pocket is held on the second certain depth Yofrom the canal. When this region of the channel legarrette with such a dopant concentration that is at times different from the Ns. Gate contact includes a layer of polycrystalline silicon of the first conductivity type, doped with a dopant concentration of the Np. When this first run certain depth Yfis determined from the following equation:

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where q equals 1,610-19The pendant, and K = 1,3810-23J/K.

When the doping of the substrate according to the above variant of execution of the invention it is also advisable to second certain depth Y0was equal

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where

fsequals 2Ff+ KT/q Ln and ffthe Fermi potential of the semiconductor substrate.

In accordance with the foregoing essence of the present invention, the technical is eaten charge can flow through the channel under the gate at a predetermined depth in the substrate, while on the surface of the semiconductor is not necessary to create an inversion layer that supports the flow of media. Accordingly, when calculating the gate capacitance at the average depth of the charge in the channel is required to take into account the dielectric constant of the substrate. Thus, the gate capacitance is reduced.

To create a field-effect transistor, it is desirable to use the area of the pocket Fermi predetermined depth, conductivity type which is opposite to the conductivity type of the substrate and coincides with the conductivity type of the diffusion regions for forming drain and source. Pocket Fermi is at a predetermined depth from the surface of the substrate, the diffusion region for a drain and a source formed in the pocket Fermi inside its borders.

Accordingly, the canal zone Fermi in advance with depth Yfand width Z passes between the diffusion regions for forming drain and source. The conductivity of the channel Fermi is regulated by the voltage applied to the electrode congestion. Therefore, the gate capacitance is primarily determined by the depth of the channel Fermi and distribution of charge carriers in the channel, and this capacity is relatively depends on the thickness of the oxide layer of the gate. Diffusion capacity back to the rd. The result is a field-effect transistor Fermi with small capacity. The preferred depth of the pocket Fermi equal to the sum of the depths of the channel Fermi Yfand impoverishment Yo.

Brief description of drawings

The invention is illustrated by drawings that show the following: Fig. 1 graphically depicts the doping of the substrate as a function of channel length to maintain the breakdown voltage is 8 volts;

in Fig. 2 graphically depicts the capacity zone depletion at zero voltage on the drain as a function of channel length corresponding to the doping concentration, is shown in Fig. 1;

in Fig. 3 is a view in cross section of a typical field-effect transistor structure with advanced MOS N-channel;

in Fig. 4 is a view in cross section of a field-effect transistor Fermi;

in Fig. 5 is a view in cross section of high-speed field-effect transistor Fermi according to this invention;

in Fig. 6-10 species in the cross section of the electrical conductivity channel high speed FET Fermi in Fig. 5 with the increase of gate voltage;

in Fig. 11 graphically depicts the profile of the injection of excess charge carriers in function of the depth of the channel Fermi;

in Fig. 12A and 12B - is ransistor Fermi at the identical dimensions;

in Fig. 13A and 13B graphically illustrates the gate capacitance at high-speed field-effect transistor, p) with P channel-type field effect transistor of MOS structure with a channel of P-type, respectively;

in Fig. 14 is a graph of the relationship gate capacitance in field effect transistors of the MOS and the Fermi functions of the thickness of the oxide;

in Fig. 15 - distribution of electric field in high-speed FET, p) with N-type channel;

in Fig. 16 graphically depicts the depth of the channel Fermi as a function of concentration of dopants;

in Fig. 17 graphically shows the dependence of the depth of the pocket Fermi on the concentration of dopants;

in Fig. 18 graphically shows the dependence of threshold voltage on the concentration of dopants;

in Fig. 19 graphically shows the dependence of the Delta voltages flat areas on the concentration of dopants;

in Fig. 20 is a view in cross section of a zone of depletion, environmental diffusion under pocket Fermi;

in Fig. 21A-21G - graphs illustrating measurements of the influence of the substrate and the source of the standard MOS transistors and field-effect transistor Fermi;

in Fig. 22 shows the electric field distribution in a typical MOS transistor;

Fig is, confirming the possibility of carrying out the invention

Hereinafter the invention is described in more detail with reference to illustrative drawings depicting a preferred variant implementation of the invention. However, the invention can be realized in various forms and therefore presents a variant of the invention does not limit it, it is intended only for the more full and complete description of the invention, making it more understandable for specialists. Throughout the description the same reference designators refer to the same elements.

Here's the improved structure of a field-effect transistor Fermi, whose values of the diffusion capacitance and the gate capacitance is significantly lower than the corresponding values obtained in a typical MOS transistors and field-effect transistors Fermi, which is the prototype of the invention.

The proposed new structure field-effect transistor Fermi provides a flow of charge carriers in the channel at a predetermined depth in the substrate under the gate. The establishment of the new structure is the result of theoretical and experimental studies of a typical MOS structures and the known field-effect transistors fer what's electrical and physical conditions for the movement of charge carriers in the canal zone on the existing depth in the substrate under the oxide layer of the gate. Unlike new field-effect transistors, in a typical MOS devices for the movement of charge carriers requires the creation of an inversion layer at the semiconductor surface. Usually the depth of the inversion layer is 200 angstroms or less. Under such conditions, the gate capacitance is determined by the dielectric constant of the insulating layer of the gate divided by its depth. In other words, the charge in the channel is so close to the surface that influence the dielectric properties of the substrate on the gate capacitance can be neglected. The gate capacitance can be reduced only when the flow of charge carriers is limited to the area of the channel under the gate, where the average depth of the charge in the channel to calculate the gate capacitance requires consideration of the dielectric constant of the substrate. In the General case, the gate capacitance of high-speed field-effect transistor Fermi equation is:

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The coefficient of Yfis the depth of the channel conductivity, called channel Fermi, esis the dielectric constant of the substrate is a factor representing the average depth charge current under the surface in the channel Fermi. The ratio depends on the distribution profile along the depth of noormets Toxrepresents the thickness of the gate oxide layer, and eiis its dielectric constant.

In accordance with equation (1) the gate capacitance can be reduced in 2 times only one depth adjustment Yfchannel Fermi and profile injection source defined . In particular, the gate capacitance of the high speed transistor Fermi is 1/2 the size of the MOS transistor ei/Toxwhen

(2)

To fulfil this condition, the depth of the channel Fermi Yfmust exceed a certain value

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Usually Yf> 6Toxfor = 2.

Conditions conducive to the flow of charge carriers at considerable depths below the surface of the semiconductor unclear. To open these conditions it took considerable theoretical study, supported by experiment. Namely, you must meet two basic conditions.

1. When the flow of excess charge carriers in the channel region of a should not be perpendicular components of the electric field beyond what is formed by the excess charge carriers.

2. Injection barrier potential KT/q Ln(NdNc/N2i) the debtor is operating impurities inside the diffusion region forming the source as a function of depth should be reduced to a predetermined speed to maintain the correct depth profiles for induced injection of charge carriers into the channel.

Dynamic gate capacitance can be measured only on the real transistor structures, when the voltage of the drain is greater than zero. The area of the shutter is limited to the area between the inlet and the outlet. The usual method of measuring the gate capacitance of the MOS transistors is not possible to identify a valid dynamic gate capacitance at high-speed field-effect transistors Fermi due to parasitic side charges and lack injection profile. Measured on a real transistor, the gate capacitance is a tool for production control and is used as process froze.

The speed of digital circuits depends on the diffusion barrier capacity. Shallow diffusion barrier capacitance is incompatible with MOS transistors with short channel. This capacity is mainly determined as the ratio of the dielectric constant of the substrate to the total depth of the zone of depletion, environmental field diffusion in the formation of drain and source. The diffusion barrier capacitance consists of two main components associated with area and perimeter. Component associated with the area, marked at the bottom of the field diffusion. Component associated with the perimeter, known as Bogush impurities in the substrate near the areas of diffusion to obtain the areas of the limitations of the channel. In high-speed FET Fermi need in the areas of limitations is missing.

Lateral capacity is defined by the following expression:

Cdp= C*sw[2Ld+ Z]Xd. (4a)

Component capacity associated with the area, is defined by the following expression:

Cda= C*aLdZ , (4b)

where

Z - channel width;

Xdthe depth of diffusion;

Ldthe diffusion length.

The high-speed field-effect transistors Fermi

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where

esrepresents the dielectric constant of a semiconductor material, Yn+ Yprepresents the sum of the depth of the depletion surrounding area of diffusion of the drain or the source, Ytubis the depth of the pocket Fermi, Yo+ Ypis the depth of the depletion of the side wall, Xdthe depth of diffusion.

In MOS transistors, the depth of depletion is inversely proportional to the concentration of dopants in the substrate Ns. For example, in MOS transistors, there is a fundamental condition of breakdown, also known as puncture. Below is the alert condition puncture as the concentration of the alloying premise is described by the following expression:

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In Fig. 1 shows a graph of doping as a function of channel length to maintain a breakdown voltage equal to 8 Century.

In Fig. 2 shows how changing the capacity of the depletion region (f/cm2) when zero voltage on the drain as a function of channel length, which corresponds shown in Fig. 1 concentration of doping.

Requirements for the doping of the substrate is rapidly growing with the shortening of the channel length due to the need to cope with the mechanism of the breakdown. The MOS device with a channel length of 0.8 μm and less typical is the diffusion capacity of 0.5 to 10-7F/cm2. In the new high-speed FET Fermi specified value of the diffusion capacity of less than about 3 times. The elimination of the breakdown is achieved by a specific method of the pocket Fermi used in the manufacture of high-speed field-effect transistor. In field instruments Fermi typical substrate is the concentration of dopants 1E16.

In the construction of a new high-speed transistor Fermi simultaneously solved some fundamental problems inherent in field-effect transistors with short channel, the found solution allows obtaining low gate capacitance.

1. SS="ptx2">

3. There is a significant reduction components capacity related to area and perimeter.

4. The design of the pocket Fermi greatly simplifies the fabrication of devices with channel P-type.

5. A decrease of the saturation current for a given voltage at the gate, despite the decrease in the charge channel per unit gate voltage.

6. In devices with channel P - type and N-type are the same structural criteria.

7. The devices operate with a power supply of 5 volts.

8. Fixed the phenomenon of reduction induced barrier discharge, usually observed on devices with buried channel.

9. Fixed shift of the threshold voltage caused by the voltage difference of the flat areas between the contacts of the shutter and the substrate.

10. Essentially eliminated the problem of hot electrons.

11. There's no need in the areas of limitations of the channel.

12. It is possible to control the threshold voltage,

13. Provides extremely small effect of the substrate.

The discussion of the problem

Speed digital integrated circuits depends on six main parameters of the transistors, as well as from the influence of parasitaemia time delay in logic circuits. It can be shown that the delay time in the circuit of the multiple logical elements is determined by the following equation:

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The logical time delay and, ultimately, system speed control six basic transistor parameters.

1. Saturation current channel I*satn. This value determines the drain current that flows in the transistor with N-type channel whose width is equal to the length, and shutter maximum applied voltage.

2. The channel length Lo. It is an effective length of the conductive channel.

3. Diffusion capacity C*d, Farad/cm2.

4. The gate capacitance C*g, Farad/cm2.

5. The diffusion length Ld.

6. The ratio of the saturation current of the N-type channel to the saturation current of the P channel-type.

From equation (7) shows that the coefficient of the delay time depends on the square of the channel length Lo. The coefficient is also traced the inverse proportionality of the saturation current channel device with N-type channel in the circuits on CMOS transistors. This factor includes a factor . It defines the ratio of the saturation currents of the channel is N-type and P-type. Specified in equation (7) option introduction Utri expressions there are three capacitive member this diffusion capacitance C*dthe gate capacitance C*gand the connection capacity C*c. The coefficients and are used to account for various logic functions in a logical chain, here for example are the coefficients of Association for input and output.

To reduce the time delay in the logic circuit can be applied to different products. Usually try to reduce the length of the channel or increase the saturation current flow. However, reducing the size of transistors in order to obtain devices with shorter channel leads to undesirable increase in gate capacitance, and barrier capacitance. An example of this is shown in Fig. 2. Barrier capacitance is increased by increasing the density of dopants in the substrate to prevent puncture in devices with short channel. The gate capacitance increases in the proportional reduction of the thickness of the oxide layer of the gate Tox.

For example, in the technology of integrated circuits from gallium arsenide to reduce delays trying to increase the load capacity current. Unfortunately, the mobility of charges in the channel of the GaAs near a source close to the values inherent in the silicon,the second current to achieve speed in devices with N-type channel compared to CMOS transistors seems to be impractical in light of the application of silicon devices on the Schottky diodes.

The second and more practical approach to increase the speed of integrated circuits is to minimize capacitive members of C*dC*gand C*c. Their capacity is expressed in farads per centimeter2. If all these capacitive members will be equal to zero, the delay circuits may also be zero, regardless of the channel length L0or the saturation current of the I*satn. The key to reducing the diffusion capacity is a clear understanding of the mechanism of puncture and its elimination. In the design of high-speed field-effect transistors Fermi eliminated phenomenon puncture and reduce induced barrier runoff through the use of technology pocket Fermi surrounding area of diffusion and defines the scope channel Fermi. The use of the instrument with a special geometry allows 2.5 or more times to reduce the gate capacitance and diffusion capacitance. More about how in high-speed field-effect transistors Fermi reduced gate capacitance and diffusion capacitance, as stated in the section "Design of high-speed field-effect transistors Fermi".

To reduce the coupling capacitance C*cby increasing the thickness of oxide blithedale 10% of full load capacity. In other words, if it were possible to eliminate the gate capacitance and diffusion capacitance, the speed of the system increased to 10 or more times.

The key to high-speed digital systems is the marginal increase in the rate of increase of the output voltage, the relationship of the current in the channel to load capacity along with minimizing power. To minimize capacitive load (first gate and barrier) while maintaining or even increasing the excitation current is the only way to achieve high operating speeds with minimal power consumption. The principle of reducing the gate capacitance while maintaining the excitation current is closely related with the effect that the concentration of charge carriers in the channel has on the mobility of carriers. Since the drain current of the FET is considered the product of the gate voltage and capacitance or charge the shutter, the technology performance field-effect transistors Fermi allows to obtain the same or higher load capacity of the stream along with significantly less full charge, the current through the channel per unit current.

Design of high-speed field-effect transistors Fermi

A feature of the proposed design is customers. In accordance with this invention this addition reduces the gate capacitance and barrier capacitance. A visual representation of this change can be obtained by comparing the new structure of Fig. 5 with previously known structures in Fig. 3 and 4.

In Fig. 3 shows the basic technical solution in the form of a MOS transistor with channel P-type. This structure suffers from two major shortcomings. First, because of the puncture mechanism is the breakdown voltage. Secondly, there is the phenomenon of reduction induced barrier discharge, which seeks to translate the channel to the conducting state in the case of an application voltage to the discharge. Both problems arise from the separation of the induced charge in the depletion region of the substrate under the buried channel. To minimize these effects, it is necessary to apply heavy doping region of the substrate. However, the result is a sharp increase in diffusion capacity. The motivation to create a device with a slightly recessed channel was, apparently, the desire to improve the saturation current for a given voltage on the gate.

In Fig. 4 shows the structure of a field-effect transistor Fermi adopted for the prototype. In this constructability diffusion for forming drain and source. In this configuration, the doping of the substrate should not be very high and therefore it is possible to reduce the diffusion capacity of the runoff. However, the gate capacitance such patterns are only slightly smaller than the size of the MOS transistor, despite the depth of the channel Fermi.

When the first field-effect transistor Fermi was patented, that were still unknown to the conditions required to control the distribution of charge in the channel in case its conductivity. In Fig. 5 shows the basic structure of the high-speed field-effect transistor Fermi according to this invention.

The basic physical difference is that the area of the pocket Fermi marked on this figure. The conductivity type of the pocket Fermi coincides with the conductivity type of the diffusion regions of the drain and the source, and the depth of the pocket is equal to the sum of two factors, namely the depth of the channel Fermi Yfand the depth of the barrier Yo. These depths are subject to specific design criteria, described in more detail below. Thanks to this new design channel Fermi Yfcan provide a flow of charge carriers with a special concentration profile along its entire depth. The desired concentration profile can only be achieved by using s, the observance of which is required to obtain a low gate capacitance. As can be seen from Fig. 5, the depth of the diffusion regions Xdmust be greater than or equal to the depth of the channel Fermi Yfbut shall not exceed the sum of Yf+ Yo. The depth of the depletion of the substrate of Fig. 5 is designated as Yp. When the voltage on the gate is less than the threshold voltage, the channel Fermi Yfthere is no charge carriers. In these circumstances, the gate capacitance is quite small and has the following value:

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Diffusion capacitance per unit area is also small and is equal to

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The dependence of the conductivity of the channel from the gate voltage

In Fig. 6 - 10 presents the process of modeling the channel conductivity with increasing gate voltage. All drawings depicted the N-type channel. Devices with channel P-type are carried out similarly by replacing the material of the conductivity of N-type material with a conductivity of P-type and Vice versa. In Fig.6 shows the channel Fermi, where there is absolutely no charge carriers. In Fig.7 - 9 shows the ionized donors, naturalisatie from the bottom of the channel, resulting in a conductivity of the channel Fermi starts from the bottom. At a higher voltage on the gate of excess charge carriers injections at the source and imauditor charge carriers, the current in the channel region of, injections there from the source in the case of an application voltage to the source. The distribution of excess carriers in the profile depth of the channel is subject to the mechanism of the injection. The main injection of charge carriers is a consequence of the existence of the electric field between the gate electrode and the surface area of the diffusion source, facing the canal. Charge carriers injected from the drain end of the channel, should not feel constrained on the surface. The injection should be evenly distributed in the direction of depth of the channel Fermi. It is important that the doping profile in the field of diffusion of the source has been uneven, and preferably such that the concentration of impurities was about 2E19 at the surface, dropping to a depth of at least one decade between the top channel Fermi and his bottom. It is this gradient is required to achieve a useful distribution injection of excess charge carriers across the depth of the channel Fermi, thereby providing a significant reduction in gate capacitance. Ideally, it is desirable that the center of mass of excess carriers lying at half the depth of the channel Fermi. When the center of the charge lies on the half depth chipaway profile injection of excess charge carriers in function of the depth of the channel Fermi shown in Fig. 11.

The concentration of dopant at the top of the diffusion region is equal to 2E19, and at the bottom of the channel it is equal to 5E17. Pay attention to the inflection point in the curve profile. The mean position of the charge in this profile is approximately half the depth of the channel Fermi.

Current drain

There was considerable theoretical and experimental work in order to prove that in the high speed field instruments Fermi does not deteriorate the current flow in comparison with the MOS transistor, despite a significant decrease of charge in the channel per unit current. The reason is that the mobility of charge carriers is proportional to the total degradation. In other words, the carrier concentration decreases correspondingly increase their mobility. The energy in the channel field-effect transistor Fermi 1/2CgV2greduced in proportion to the reduction in gate capacitance together with the switching power of 1/2CgV2gf) at frequency f.

In Fig. 12A and 12B shows graphs of current drain for the MOSFET with a P-channel field-effect transistor Fermi, having identical dimensions, L = Z = 0.8 μm, and is identical to the thickness of the oxide layer 165A. The doping of the substrate DLNA, the transistor Fermi at a given voltage on the gate and the drain passes more current than MOS-transistor, despite the fact that the gate capacitance and barrier capacitance are respectively 47% and 30% of the values of the capacitances in the MOS transistor. As a result, the switching speed of logic circuits implemented on high-speed field-effect transistors Fermi, approximately 2.5 times higher than that of the same circuits implemented with MOS-transistors with the same operating capacity.

Metering gate capacitance

The literature provides a lot of information on the measurement of the capacitances in the MOS transistors. However, any information on the measurement gate capacitance using a real transistor structures no. The reason for this probably lies in the fact that the MOS transistors of the charge in the channel is very close to the surface and is approximately 200 angstroms or less. However, this reason is not valid for high-speed transistors Fermi, because they have the profile of injection is adjusted to obtain a greater depth of injection. Methods of measuring capacitances in the MOS transistors do not allow to identify the gate capacitance at high speed transistors Fermi. The MOSFETs injection in an ionized region paascu, facing the plot of diffusion. Injection occurs closer to the surface, where the barrier due to the inversion process, is omitted.

The measured gate capacitance for high-speed transistors Fermi conducted on real transistor structures. To address capacity created pads, it is necessary to carry out a differential measurement. This method is quite simple, it is used for process control. The area of the shutter shall be clearly defined as the product of width Zwithand length Lwithchannel. Transistor structure need to measure for the reason that the charge distribution and, therefore, the gate capacitance in the first place, is determined by the profile of injection at the source. Profile injection of charge carriers as a function of depth in istokpoga the end of the channel is almost constant in the interval between the inlet and the outlet during the time span. The reason is that in the channel Fermi there is no vertical component of the electric field beyond what is created by the charge carriers. The vertical component of the electric field on the transfer substrate-pocket Fermi equal to zero at the bottom of the channel Fermi, remaining equal to zero high-speed transistor Fermi channel P-type, in Fig.13B presents a similar graph for a MOS transistor with channel P-type.

It is evident from Fig.13A shows that, while the voltage on the gate below the threshold, the inversion charge is in the channel region of Fermi. In this area of the graph, the gate capacitance is described in the following equation:

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where

depth inversion.

When the voltage of the gate is near the threshold, the gate capacitance is quite small:

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When the voltage of the gate exceeds the threshold, the gate capacitance approaches the value described by the following equation:

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The value depends on the concentration gradient inside the area of diffusion of the source in the direction of depth. Usually equal to 2.

In Fig. 13B shows a graph of the dynamic gate capacitance measured on MOS transistor. Here, apparently, there is no difference between areas of inversion and accumulation. The minimum value of the capacitance in the MOS structure determines the depth of field ionization under the gate in the substrate. However, when the inversion capacitance increases dramatically up to typical values of ei/TOh.

When all capacity measurements using real transistors to the drain applied voltage to eliminate parasitic C is the thief in the MOSFET and transistor Fermi functions of the thickness of the oxide layer provided the depth of the channel Fermi is 1200 angstroms.

Analysis of high-speed field-effect transistors Fermi

Following implantation of the pocket and channel Fermi, which provide a correction voltage differential flat areas between the polycrystalline silicon gate and the contact substrate. The gate capacitance and the diffusion capacitance is reduced by controlling the depth and dose in the region of the pocket Fermi. In Fig. 15 shows the electric field distribution in high-speed FET, p) with N-type channel, where you can see the mutual impoverishment pocket, channel and substrate under the gate with the threshold conditions.

Beyond the x-axis component of the electric field in Fig.15 explains the depth of the channel Fermi Yfcreated at a depth of implantation of the pocket Fermi to minimize differential effects between the exposure gate and the contact substrate. The specified depth of the channel defines the area where the movement of charge carriers. Region channel Fermi has sufficient depth and therefore the center of mass of the charge lies at a considerable depth below the surface, provided the correct profile of the injection area of the diffusion channel. Perechi transistor Fermi is exactly twice the Fermi potential, if the difference between the contact potentials of the gate and the substrate is equal to zero. In practice, however, the concentration of dopant in the polycrystalline gate should be large to resolve difficulties with a rectifier contacts. Due to these contact potentials of the differential voltage is described by the equation

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where

Npthe concentration of dopant in the polycrystalline gate,

Nsthe concentration of dopant in the substrate.

Usually Delta stresses in flat areas is 200 millivolts. It is evident from Fig.15 shows that the potential of the triangular region above the x-axis is equal to

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If you set the potential f is equal to the difference of voltages flat zones fbthen you get the ratio to determine the depth of the channel Fermi

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where

= Nc/NsNcthe concentration of the compensating doping in the pocket Fermi, Nsthe concentration of dopant in the substrate in cm3.

The total depth of the pocket Fermi under the shutter equals Ytub= Yf+Yaboutwhere Yabout- depth of field depletion in the pocket due to Fermi contact with the substrate,

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Therefore, the depth of the Fermi equal is the depth of the depletion region in the substrate Ypis described by the following equation:

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Given these conditions, calculate the electric field E(O) and the potential fson the channel surface under the oxide layer of the gate with the threshold voltage. According Fig.15 field is described by the following equation:

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Since E is the gradient of the potential, calculate the potential as a function of the distance y and, particularly, on the surface, where y = 0.

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Determining (21) on the surface, receive

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Using the definitions for Yp, Yfand Yodefine the following terms:

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Leading members and making it easier to get the equation

F(O) = f - f (24)

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Thus, having a depth of implantation of the pocket Fermi equal to the sum of Yo+ Yf, surface potential appearing between the contacts of the polycrystalline gate and the substrate, is reduced exactly to the voltage difference of flat areas. In the result, the threshold voltage becomes equal to twice the Fermi potential. In other words, the depth Yfas part of the requirements for the depth of the pocket Fermi, eliminates the offset of the difference between the voltage on the flat areas due to the difference of potentials at the contacts of the shutter and the substrate. Another vosmogo voltage is below the double value of Fermi on the magnitude of the potential of the oxide layer at a threshold effect compensation of the flat zone. It should be noted that the direction of the electric field in the oxide layer must take charge carriers from the brink of partition oxide-silicon. This effect contributes to the reduction of the capacity. It turned out that the potential of the oxide layer is described by the following expression:

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Note: a member of the voltage of the oxide layer has a polarity opposite to the polarity on the substrate of the MOS transistor, and has a relatively small value.

The following is an expression for the threshold voltage of a high-speed transistor Fermi:

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where

Np- alloying impurity in the polycrystalline silicon,

Npo- alloying impurity in the polycrystalline silicon used in the manufacture of semiconductor wafers,

Nsthe concentration of dopant in the substrate.

The final estimated equation

To calculate the high-speed field-effect transistor Fermi uses the following equation:

the equation of the depth of the implantation pocket Fermi Ytub(18),

the equation of the depth of the channel Fermi Yf(16),

the equation Delta voltage flat zones (14),

the equation of the threshold voltage (26),

the voltage equation of the oxide layer (25 the La Fermi has the following maximum value:

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Diffusion to the side wall of the pocket Fermi Yois determined by the following equation:

< / BR>
In Fig. 16, the channel depth Fermi represented as a function of the concentration of dopant used to compensate for the depth of the implantation pocket Fermi order partial compensation conditions voltage flat areas arising from the difference between the real potentials of the contacts polysilicon gate and the substrate. In Fig.17 shows a graph of the depth of the pocket Fermi for the same conditions. In Fig.18 shows a graph of the threshold voltage for the same criteria. In all cases, the concentration of dopant in the substrate is equal E on cm3and = 1.

The most preferred procedure of the calculation is that primarily choose the desired threshold voltage. This selection determines the compensation of the dopant, and the value of the abscissa corresponds to the selected threshold voltage. For example, when the threshold voltage of 0.75 In the required compensation value E for dopant, which should be used to obtain the depth of the channel Fermi in 3300 angstroms. The depth of the Fermi for this threshold voltage is equal 1245 angstroms.

In Fig.19 preg.16-19, the actual level of dopant, used in the manufacture of chips equals A.

The diffusion barrier capacitance

In order to achieve high speed switching, it is necessary to reduce both components of the diffusion barrier capacity in comparison with the corresponding values from the MOSFETs. We are talking about the component associated with the area, and the lateral component. In Fig.20 shows the depletion region surrounding the areas of diffusion provided by the technology of pocket Fermi.

The reduction in component capacity associated with the area, is at a bottom region of diffusion and for all practical purposes is described by the following expression:

< / BR>
The lateral component is described by the expression

< / BR>
where

Xtub- the depth of the implanted pocket Fermi;

Xd- depth of field diffusion;

Z - width of the diffusion region;

Ld- the length of the diffusion region.

The total depth of the barrier Yo+ Yplarge enough to reduce or eliminate the need to use methods limitations of the channel, leading to high capacity. The restriction channel is typically used in MOS transistors, so that the surface inversion and leakage current not gone beyond the boundaries of what is possible in high-speed transistor Fermi large enough to the protective oxide layer sufficiently reached the limit values at the border of the depth of the depletion region Yabout+Yp. Surface inversion occurs when

< / BR>
Surface inversion occurs when the voltage is 11 volts higher than the ground potential at the 30oC.

Fox(Fox) = 8000 angstroms

ei= 3,45 E-13 f/cm

Na= 1E16 cm-3< / BR>
Ni= 1,5E10 cm-3< / BR>
The effect of crystalline solids

Understanding the threshold voltage and its dependence on voltage to the substrate or the source is of crucial importance for the correct simulation of circuits in General, and especially high-frequency. However, apparently, in the technique still exists some confusion with the definition and understanding of the threshold voltage, called gamma (), and how this member is associated with the effect of crystalline solids. For example, it is believed that gamma is directly proportional to the effect of crystalline solids. Usually this value is different from that required in equation source to match the measurement results. There are other difficulties with definitions . The effect of the crystal body with respect to the voltage on the source cannot Raschig. 21A and 21B shows the appearance of current flow from the voltage on the gate in the MOS transistor for different voltages on the substrate (0-> 5 (B) of Fig. 21A either the voltage source of Fig. 21B. From the drawings it is seen that the effect of crystalline solids relative to the voltage on the substrate dVt/dVsubless pronounced than the effect of the crystal body and the voltage at the drain d(Vt-Vs)/dVs.

The observed difference is described by a coefficient of 1.5. A similar phenomenon exists in high-speed transistors Fermi, although they both effect the crystalline body to 1/5 greater than that of the MOS transistor. Graphs in Fig. 21A-21G allow us to compare the effects of the crystal body to a voltage on the substrate and the voltage source when the channel is P-type for both technologies. By construction, the devices are similar. The small effect of the crystalline body is comparable and distinctive factor of the transistor Fermi, and as the shortening of the channel it becomes more pronounced. The most significant should be considered a small effect of the crystal body, caused by the applied voltage source.

Analysis of the effect of the crystal body MOSFET

According to the definition of the effect crystallizable voltage on the substrate, and not a private derivative of the potential of the oxide layer relative to the voltage on the substrate. The voltage of the substrate has an influence on the surface potential and the potential of the oxide layer. Member is merely a convenient means of simplifying the equations of the effect of crystalline solids. Usually expressed as:

< / BR>
where

Toxthe thickness of the oxide layer of the gate;

Nsthe doping of the substrate;

es- the dielectric constant of silicon;

ei- permittivity insulator.

Derive the equation of the effect of the crystal body to the MOSFETs. A similar conclusion for high-speed transistors Fermi much harder, and for the purposes of this invention it makes no sense to lead. We will present only the results. In Fig. 22 depicts the electric field of the MOS transistor for conditions existing under the oxide layer of the gate.

Let Yp- depth of field Association in the substrate under the oxide layer,

< / BR>
The factor K is related to a member of the voltage of the substrate takes into account the fact that the charge field of the Association comes from the inversion region, pseudoplastic N-type, and for a device with an N-channel ends in the area of P is g NsYp/esis described by the following expression:

< / BR>
Using the divergence theorem for the boundary surface of the oxide layer, obtained an expression for the potential of the oxide layer:

< / BR>
or through

< / BR>
Surface potential fs= qNsY2p/(2es)-Vsubhas the value

< / BR>
Therefore, the surface potential cannot be considered independent of the voltage on the substrate and therefore the effect of the crystalline body is not described as dVox/dVsub.

The expression of the threshold voltage of the MOS transistor

< / BR>
where

Vfb- the net value of the voltage of the flat area.

Taking private derived from equation (36) the voltage of the substrate receive the formula for the effect of the crystal body for the MOSFET:

< / BR>
Because the effect of the crystalline body is not negative, from equation (37) have the criteria for the zero voltage of the substrate and estimate the parameter K:

< / BR>
In Fig. 23 shows a graph of the threshold voltage (36) as a function of the voltage of the substrate, and Fig. 24 shows a graph of the effect of the crystalline body from the voltage of the substrate (37) for the case when Ns= 1e17, 2e17 and 3e17 when OK is Vtorov Fermi usually 0.05 B/B or less.

The expression for the effect of crystalline solids at high speed transistor Fermi below.

The threshold voltage is equal to the

Vt=Vfb+fs+Vox, (39)

where

< / BR>
< / BR>
< / BR>
where

the depth of the channel Fermi Yfequals

Yf= Yo( - 1). (43)

High-speed transistor Fermi factor > 1 (according to U.S. patents NN 4990974 and 4984043 requires 1).

The effect of crystalline solids at high speed transistor Fermi can be obtained by taking partial derivatives from (41) and (42) the voltage of the substrate and then summing them.

Conclusion

In high-speed FET Fermi there is a pocket Fermi certain depth, its conductivity type opposite to the conductivity type of the substrate and of the same type conductivity regions of diffusion of the drain and the source. Pocket Fermi passes at a certain depth from the surface of the substrate, and the diffusion of the drain and source are implanted in the region of the pocket Fermi inside its borders. The preferred depth of the pocket Fermi equal to the sum of the depth of the channel Fermi Ysand depth of Association Yabout. Region channel Fermi length Yfand width Z runs between ode shutter. The gate capacitance is primarily determined by the depth of the channel Fermi and charge distribution in the channel and relatively depends on the thickness of the oxide layer of the gate. The diffusion capacitance is inversely proportional to the difference between the sum of the depths of his pocket Fermi and area Association Yaboutin the substrate and the depth of the diffusion regions Xd. It is desirable that the depth of field diffusion was the same as the depth of the channel Fermi. At a deeper configurations depth of field diffusion must be less than the depth of the pocket Fermi Ytub. The concentration of dopant in the regions pocket Fermi preferably be chosen such that the depth of the channel Fermi exceeded three times the depth of the inversion layer in the MOS transistor.

The depth of the pocket Fermi is defined as follows:

< / BR>
where

= NfTub/Ns;

Nsthe concentration of dopant in the substrate;

Npthe concentration of compensating dopant;

Nftubthe concentration of dopant in pocket Fermi.

Depth of field Ytubpocket Fermi is determined by the equation

< / BR>
where

fs= 2Ff+ KT/qln(). (46)

Diffusion in the pocket Fermi at a distance of Yodefined above. The density profile of dopant depth for the entire area of diffusion of the drain and the source should fade from the surface level and at the bottom of the channel Fermi should be at least one order of magnitude. In high-speed transistors, p) with N-type channel is required doping of polysilicon gate P-type, and the transistors Fermi and the P channel-type requires doping of gate N-type.

In both cases, the dopant concentration must be equal to 5E19 or more. Preferably, high-speed transistors Fermi magnitude of the effect of the crystalline body from the substrate was less than 0.05 In/Century

The drawings and description have been disclosed preferred implementations of the invention, but, although they were used with specific concepts, they have a generic and descriptive sense and not serve the purpose of limiting the requested rights, because the scope of the invention is defined by the formula of the invention.

1. Field-effect transistor-containing semiconductor substrate of the first conductivity type with the first surface, the pocket region of the second conductivity type in the substrate at the first surface, spaced areas of the source and drain of the second conductivity type in the hay fields of the source and drain contacts and source, drain and gate for electrical contact areas of the source and drain and the insulation layer of the gate respectively, wherein the field-effect transistor includes a channel of the second conductivity type in the area of the pocket at the first surface between the spaced regions of the source and drain, and the channel is at first a certain depth from the first surface region of the pocket is held on the second certain depth from the channel region of the source is held on the third certain depth from the first surface, and a third depth greater than the first depth and less than the sum of the first and second depths.

2. The transistor under item 1, characterized in that the source legarrette impurity of the second conductivity type at a dopant concentration decreasing from the first surface to the third predetermined depth.

3. The transistor under item 2, characterized in that the center of mass of the dopant is at a depth equal to half the first predetermined depth.

4. The transistor under item 1, characterized in that at least one of the defined first and second depths is selected so that the component of the electric field is perpendicular to the first surface, the first specific pervoi and second depths are additionally selected so that what component of the electric field is perpendicular to the first surface, the first predetermined depth to the first surface at the position of the threshold voltage to a contact of the shutter is equal to zero.

6. The transistor under item 1, characterized in that the second a certain depth is chosen to create such a threshold voltage of the field-effect transistor, which is equal to twice the Fermi potential of the semiconductor substrate.

7. The transistor under item 1, characterized in that at least one of the defined first and second depths is chosen such that the charge carriers of the second conductivity type can flow from source to drain in the channel region of passing from the first to a certain depth below the first surface for attachment to the contact of the gate voltage exceeding the threshold voltage of the FET.

8. The transistor under item 1, characterized in that at least one of the defined first and second depths is chosen such that the charge carriers of the second conductivity type can move within the channel region of the source to drain under the first surface without creating an inversion layer in the channel.

9. The transistor under item 1, kristallicheskogo silicon of the first conductivity type and a gate electrode on the layer of polycrystalline silicon against the gate insulating layer, moreover, at least one of the defined first and second depths are selected to establish a voltage on the first surface adjacent to the insulating layer of the gate that is equal and opposite in sign to the sum of the voltage between the contact substrate and the substrate and between the layer of polycrystalline silicon and the gate electrode.

10. The transistor under item 1, characterized in that the substrate is provided with an electric contact, and at least one of the first and second specific depths selected to change the threshold voltage field-effect transistor is less than one-twentieth volts, when the voltage applied to the contact substrate is changed to one volt.

11. The transistor under item 1, characterized in that the substrate legarrette with a concentration of dopant of Nshas its own concentration of charge carriers Niat temperature T degrees Kelvin and a permittivity es, field-effect transistor includes an electrical contact of the substrate and the channel it is on the first a certain depth Yffrom the first surface, and the area of the pocket is held on the second certain depth Yofrom the channel, and the channel region legarrette with t the th polycrystalline silicon of the first conductivity type, doped with a dopant concentration of the Npand the first certain depth Yfequal

< / BR>
where q equals 1,610-19The pendant, and K = 1,3810-23J/K

12. The transistor on p. 11, characterized in that the second a certain depth Yoequal

< / BR>
where fsequals 2Ff+ KT/qLn, and ffthe Fermi potential of the semiconductor substrate.

 

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