The methods and devices of the processing of the set of transform coefficients, the methods and devices of the inverse orthogonal transform of the set of conversion factors, methods and devices for sealing and expansion signal of the moving image, the recording medium compressed signal representing the moving image

 

(57) Abstract:

The claimed methods and devices used in digital signal processing. In the local decoder device seals MPEG standard, as well as in the expansion unit MPEG standard errors of rounding. This is due to the lack of standard for rounding the results of type *. 5 (where *. is an integer), which are obtained when the set of transform coefficients, resulting seal is subjected to inverse orthogonal transform. The invention prevents errors, inconsistencies by pre-treatment of the set of conversion factors to their inverse orthogonal transformation, which is achievable technical result. The transform coefficients in the set are summed and evaluated the parity of the sum (odd or even). If it is determined that the checksum is even, then inverts the parity of one of the transform coefficients in the set to get the conversion factor from proinvestirovanno parity. This makes the checksum is odd. Then, if the set of transform coefficients, including the coefficient of preobrazovatelnaja orthogonal transformations will not have the value *.5. 12 C. and 38 C.p. f-crystals, 30 ill.

This invention relates to a method and apparatus for pre-processing of the transform coefficients, a method and apparatus for performing inverse orthogonal transformation, a method and apparatus for expanding compressed information signal and recording media. In particular, the invention relates to a method and apparatus for pre-processing of the transform coefficients, a method and apparatus for performing inverse orthogonal transformation, a method and apparatus for sealing an information signal, a method and apparatus for expanding compressed information signal and recording medium for a signal of the moving image.

Orthogonal transformations are used in a variety of systems digital signal processing for various applications. Orthogonal transformations allow you to perform the signal processing in the frequency domain. Widely known types of orthogonal transformation is a fast Fourier transform (FFT) and discrete cosine transformation DCT), etc., Orthogonal transformation analyzes, for example, a fragment of the signal in the time domain by the frequency of status is Opredelenie energy frequency) of the initial fragment of the signal in the time domain. By processing a variety of ways frequency components (usually referred to as conversion factors) resulting from the orthogonal transform portion of the signal can be reduced redundancy in the original fragment signal. In other words, by means of an orthogonal transformation of the original fragment of the signal and process the resulting transform coefficients, the initial fragment of the signal can be represented using fewer bits than were used in the submission of the initial fragment of the signal. In addition, through the inverse orthogonal transformation coefficients of the transformation can be restored to the initial fragment of the signal in the time domain.

Device to improve signal of the moving image and for expanding a compressed signal of the moving image are well-known examples of systems for processing digital signals using an orthogonal transformation.

It is known that the strength of the signals having a high correlation, is concentrated in the low frequency range the frequency domain. If the concentration of signal power in particular is, the signal can be sealed more effectively.

Because the signal of the moving image is usually strongly correlated in space and in time, to concentrate the signal power at a particular coordinate axis can be applied to orthogonal transformation, and the signal of the moving image can be condensed with high efficiency.

Up to the present time a large amount of information required to represent a moving image using, for example, the video signal of the NTSC (national Television system Committee systems, USA). Thanks for recording the moving image needed a recording medium with a very large information capacity, if the media was to ensure that the recording time is acceptable duration. In addition, the frequency information, in which such media is recorded and reproduced signal of the moving image, was very great. Therefore large magnetic tapes and optical disks are required to store the signals of the moving image.

If it is desirable to record the moving image on the more compact the recording medium with the playback time of the por is to reduce the amount of information want to store. In addition, the device must be able to extract the multiplexed signal of the moving image reproduced from a compact recording media.

To meet the described requirements have been proposed various sealing systems signal of the moving image, which uses the correlation between and within portions of the signal of the moving image representing the frames that comprise the signal of the moving image. For example, a well-known sealing system signal of the moving image proposed by the Expert Council of the Moving Images (MPEG). Because the MPEG system is described in detail in various printed publications, a detailed description of the MPEG system is not given here.

In the subsequent description will be frequently used, the term "image". As described herein, the method of signal processing refers to the processing of the moving image representing the moving image, it should be clear that the word "image" is usually used here, refers to the part of the signal of the moving image. In addition, the signal of the moving image may represent a frame of the moving image tx2">

First, the MPEG system determines the differences between the frames forming the signal of the moving image, to reduce the redundancy of the signal of the moving image in the time domain. Then the MPEG system reduces redundancy signal of the moving image in the spatial domain by applying an orthogonal transform to blocks of the interframe differences in the spatial domain. The system uses MPEG discrete cosine transformation (DCT) as the orthogonal transform. By reducing the redundancy in the time and in the spatial area, the moving image is sealed very effectively. Multiplexed signal of the moving image, which is the result of the process just described, the seal can then be recorded on a recording medium or transmitted via a suitable transmission channel.

When the multiplexed signal of the moving image is reproduced from the recording medium or received from a transmission channel, from a compressed signal of the moving image are allocated blocks of transform coefficients resulting from the DCT transform. The transform coefficients are processed by using reverse ortog the blocks I interframe differences in the process of reconstructing frames of the original signal of the moving image.

An example of the structure of the sealing device signal of the moving image based on the MPEG system, shown in Fig. 1. In the sealing device shown in Fig. 1, the digital signal of the moving image is supplied to the formatting scheme of the block 101, where it is converted from a standard video format, for example, from a standard video signal format NTSC, in block format for getting chunked signal of the moving image. Thus, each frame signal of the moving image is divided in the spatial domain, i.e., horizontally and vertically, on macroblocks, for example, 16 x 16 elements. The macroblocks are divided also into blocks of 8 x 8 elements.

The device shown in Fig. 1, compresses each frame signal of the moving image block by block, until you have processed all the blocks that make up the frame. The device then processes another frame signal of the moving image, which may or may not be the next frame in the sequence of frames forming the moving image. In the following description of the device shown in Fig. 1, there is disclosed a process of compression of one block of elements in a single frame. The block of elements to seal - this is given on the predictor motion 102. The predictor motion takes the current frame including the block of the current frame S1, block by block diagram of the calculation unit differences 103.

When the calculation scheme of block differences 103 obtains the current personnel from the predictor motion 102, it also receives the block mapping S2related to the current human resources unit of the predictor motion 102. Block matching is formed predictor 113 from the restored frames stored in the memory block frame 112. Calculation scheme of block differences 103 defines an element by element the difference between the current HR block S1and the corresponding block mapping S2. The resulting block differences, the differences in S3served in the scheme of orthogonal transformations 104.

Scheme of orthogonal transformations 104, which is usually the scheme discrete cosine transform (DCT), performs orthogonal transform block of the differences S3and delivers the resulting block of transform coefficients to the quantizer 105. The quantizer 105 discretetime block of transform coefficients to obtain a block discretized conversion factors. Encoder with variable word length 106 processes the block of the other words, such as Huffman coding or non coding, etc., the Resulting encoded block of transform coefficients is served then, for example, in channel digital transmission through the output buffer 107. The control signal indicating the number of bits stored in the output buffer 107, is fed back to the quantizer 105. The quantizer adjusts the sampling rate given control signal, preventing overflow or underflow in the output buffer. Increase or decrease the sampling rate, respectively reduces or increases the number of bits supplied to the output buffer.

Block discretized conversion is supplied from the quantizer 105 to inverse quantizer 108, which is part of a local decoder used in the sealing device for the formation of the discretized transform coefficients of the reconstructed frames used in the process of coding with prediction. The inverse quantizer 108 performs the inverse quantization unit discretized transform coefficients by performing processing, which is in addition to the sampling process performed by the quantizer 105 is La 109, where he is subjected to inverse orthogonal transformation such as the addition to the orthogonal transform performed by the scheme of the orthogonal Converter 104. The result of the restored block of the differences S4is supplied to the adder 110.

The adder 110 receives the block mapping S2for the current HR block S1from one of the memory devices of frames in the memory of the image 112, the selected predictor 113. The adder 110 performs an element by element summation of the restored block of the differences S4from the scheme of the inverse orthogonal transformation 109 and block mapping S2from memory image 112 to obtain the reconstructed block image S5. The reconstructed block image is delivered to one of the memory devices image 112A through 112D, selected by the selector III from where it is stored.

The reconstructed block image stored in the selected memory device of the image, where it forms one block (corresponding to the current block of the frame, the restored block by block from the blocks of the reconstructed image in the selected memory device of the image. Once reconstructed Itanium to seal the other frames of the signal of the moving image.

The predictor motion 102 determines, for each macroblock of the current frame, the motion vector between the macroblock of the current frame and the stored macroblocks differences other frames of the signal of the moving image. The predictor motion generates the sum of absolute values of differences (sum of absolute values of differences between the elements in each macroblock of the current frame and the other macroblocks of other frames. Each sum of absolute values of differences indicates the degree of coincidence between each macroblock of the current frame and the macroblock of the other frames. The predictor motion feeds each motion vector and the corresponding sum of absolute values of differences and schema definition mode prediction 115.

Definition schema mode prediction 115 uses the data received from the predictor motion 102, to determine the prediction mode used for encoding the prediction of the current frame associated with one or more other restored frames. The current frame may be encoded with the predictor by using any of the following prediction modes:

(1) intra-frame mode in which the frame is compressed with) the direct Mode prediction, when the prediction is performed by referring to the reconstructed frame, which appeared earlier in the moving image. The frame encoded in this way are called P-frame.

(3) the Mode of bidirectional prediction, which is the prediction block by block with reference to the reference block obtained from the reconstructed frame, which appeared earlier in the moving image, the reconstructed frame, later appearing in a moving image or by performing a linear operation element by element (for example, calculation of average values) between the previously reconstructed frame and the frame, the reconstructed later. The frame encoded in this manner is called a B-frame.

In other words, an I-frame is a frame in which is intra-frame coding. P-frame is predicted from the reconstructed I-frame or P-frame that appeared earlier in the moving image. B-frame predicted block by block by using earlier or later reconstructed I-frame or P-frame, or by using a block obtained by performing a linear operation using the reconstructed I-Adra or P-frame, the wound is agenie.

Definition schema mode prediction 115 delivers the information about the prediction mode and the corresponding motion vector to the predictor generator 113 and the read address 114. Generator read address 114 generates the read address in the image memory 112 according to the motion vector, which causes each memory device of the image 112A through 112D to read a block of reconstructed frames stored in it. Place the read block in the reconstructed image is determined by the motion vector. Predictor 113 selects one of the read blocks of memory devices image 112A - 112D in response to the mode signal PM predictions obtained from the schema definition mode prediction 115. The selected read block is a block mapping S2for the current block S1. If the current block is part of the B-frame, the predictor performs linear operations on blocks read from the memory devices image 112A - 112D, to obtain the desired block mapping. The predictor takes the unit map S2in the block circuit diagram of the differences between 103 and the adder 110.

An example of the structure of the expansion unit aggregated signal of the moving image on the basis of sisterella seal or by playing with the recording media, served in the form of a bit stream in the input buffer 121, where it is temporarily stored. Multiplexed digital signal includes encoded blocks of transform coefficients (including the block of encoded transform coefficients representing the current block and information on the prediction mode, the sampling and the motion vector for each block.

Multiplexed signal of the moving image frame is read from the input buffer 121 and sent to the inverse encoder with variable word length (IVLC). Inverse encoder with variable word length 122 performs the reverse coding with variable word length of the compacted signal of the moving image and separates the multiplexed signal of the moving image component including the discretized blocks of transform coefficients, and information about a prediction mode, step size and a motion vector for each block.

Each block of encoded transform coefficients is served in the inverse quantizer 123, which uses information about the step size for the unit to perform inverse quantization unit discretized conversion factors to obtain a block of coefficients convert the W, usually IDCT-processing block of transform coefficients to obtain a restored block of differences. The inverse quantizer 123 and the scheme of the inverse orthogonal transform 124 respectively perform processing, which is in addition to the operations performed by the quantizer 105 and the scheme of orthogonal transformations 104 in the sealing device shown in figure 1.

Generator read address 130 delivers the read address in the memory device image 128A - 128D according to the motion vector for the current block is obtained from the inverse of the encoder with variable word length 122. In response to the address being read each of the memory devices image 128A - 128D reads the stored block of the reconstructed frame. The predictor 129 selects one of the read blocks of the memory device image 128A - 128D in response to the mode signal PM predictions, obtained from the inverse of the encoder with variable word length 122. The selected read block is a block mapping to reconstruct the current block. If the current block is part of the frame is encoded as a B-frame, the predictor performs such linear operations on the read blocks of the memory device image is 125.

The adder 125 performs an element by element addition of the restoring unit differences from the scheme of inverse transformation 124 and block mappings from the predictor 129 to reconstruct the current HR block of the current frame. The selector 126 delivers the reconstructed current block of the frame for storage in one of the memory devices image 128A - 128D, in which the current frame is reconstructed. The reconstructed current HR block is written in the selected memory device image in place of the current HR block in the reconstructed current frame. When all of the reconstructed current staffing blocks will be written to the selected memory device image 128A - 128D, the reconstructed current frame will be ready to read and to use as a reference frame for the reconstruction of other frames that appear earlier or later in the moving image.

The reconstructed frames stored in the memory devices image 128A - 128D are read in the form of an output signal of the moving image through the selector 126 in response to the read address generated by the address generator of the display 127. The scan Converter (not shown) converts the output signal dia video for example, NTSC. The resulting output signal of the moving image can then be displayed on a suitable display such as a cathode ray tube (CRT), etc., In this example, the clock generator 131 is synchronized from an external source clock and periodically generates personnel synchronization signal for delivery to the address generator of the display 127. The address generator of the display 127 generates read addresses synchronously with HR clock.

Schematic of an orthogonal transformation, for example, schemes DCT and IDCT used in the above control devices and extensions, perform the appropriate arithmetic operations on values and conversion factors, represent integers with a finite number of bits. Thus, the operation of the orthogonal transformation performed by the circuits orthogonal transformations, display the result with a rounded number of bits. For this reason, the difference in the accuracy of the operation of the orthogonal transformation using real numbers or the difference in the device of the scheme used to perform the operation of the orthogonal transformation may change the result of the operation of the orthogonal transformation. is total employment expansion, carrying out the expansion of the generic compressed signal.

For example, in the sealing device block differences, resulting from the signal of the moving image, is subjected to orthogonal transformation, and uses the specified processing to discretize the resulting conversion factors in the course of generating a compressed signal of the moving image. Then in the expansion unit, if the operating accuracy of representation of real numbers or the device schema inverse orthogonal transform does not correspond to similar features of the sealing device, you receive the likelihood that the output signal of the expansion unit will be different from the input signal in the sealing device. Therefore, the output signal expansion unit may depend on the precision and design of the device used for the extension.

Operating accuracy or structure of the inverse orthogonal transformation may vary depending on the device used to perform inverse orthogonal transformation. For example, the inverse transform block transform coefficients using two different konstrukce the difference in results is called the mismatch error of the inverse orthogonal transform ("mismatch error").

The MPEG system detects the operating accuracy, which must be performed DCT and IDCT, but does not specify how operations and configuration. This is due to the fact that circuits and methods for performing DCT and IDCT have been developed to establish standards MPEG.

As described above, in the MPEG system, the control device implements, for example, interframe coding with prediction and motion compensation signal of the moving image. In this system the signal of the moving image is divided into blocks, the block difference is constructed from the current staffing of the block and the block map obtained by applying motion compensation to the reconstructed frame; block differences is subjected to orthogonal transformation using the DCT-processing; the resulting transform coefficients sampled; discretized transform coefficients are subjected to encoding with variable word length, and encoded transform coefficients together with information about the prediction mode, the size of the sampling step and the motion vectors to obtain the o signal of the moving image.

The expansion unit inputs the discretization discretized to the transform coefficients, which are the inverse of encoding with variable-length words, and IDCT-processing the transform coefficients resulting from the inverse of the sampling rate. The result of the restored block of the difference is added to the block map obtained by applying motion compensation to the reconstructed frame according to the motion vector, the Resulting reconstructed HR block will be written in the form of a block of the reconstructed frame, which provides the output signal frame of the moving image and is also suitable for use as a reference frame.

The sealing device includes a local decoder that reproduces from discretized transform coefficients of the reconstructed frames for use when performing coding with prediction. The local decoder includes an inverse quantizer scheme and inverse orthogonal transformation.

If the IDCT circuit configuration in the local decoder sealing device differs from the IDCT circuit in the expansion unit will be occasions when the reconstructed frames generated by the local decoder in the sealing device will be otlichaetsa performance may cause problems if multiplexed signal of the moving image generated by the sealing device in accordance with the MPEG standard, recorded on the recording media such as an optical disk, etc. for mass distribution. If multiplexed signal of the moving image reproduced from an optical disc, is expanded by the expansion units produced by and sold by various manufacturers, the displayed image may differ from the original. In addition, differences may vary depending on your expansion unit. The incompatibility between the different expansion units can also occur when the multiplexed signal of the moving image is distributed such distribution systems, such as terrestrial or satellite substance, telephone systems, digital communication systems integrated services (ISDM), cable or optical distribution system, etc.

Mismatch errors are a particular problem if interframe coding with prediction. Interframe coding with prediction can be mesolevel coding or interframe coding. Interframe coding with prediction can calling is in the reconstructed frames.

When sealing the signal of the moving image according to the MPEG system, each video sequence is divided into groups of pictures (GOP), for example, eight or twelve frames. Each frame is classified as an I-frame, P-frame and B-frame, as described above. When performing motion prediction B-frame is not used as a reference frame. Therefore, the mismatch error appearing in B frame does not lead to errors in other frames.

If the mismatch error appears in the P-frame, the frame with the mismatch error is recorded in the memory image to use when performing coding with prediction. Accordingly, if interframe coding with prediction error in P frame stored in the memory of the image, partially covered in P-frames and B-frames are obtained from it by coding with prediction. The error accumulates until the frame is replaced by the I-frame or P-frame does not have this error.

Similarly, when the mismatch error appears in the I-frame, the reconstructed frame with the mismatch error is recorded in the memory image to use when performing coding with prediction. Accordingly, if the imp is aneesa in P-frames and B-frames, formed from it by coding with prediction. The error accumulates until the block is replaced with a new I-frame, no such error.

The accumulation of errors is shown in Fig. 3. In Fig. 3, if the mismatch error when decoding the I-frame is equal to E1and the mismatch error when decoding a P-frame to P1equal EP1the value in the reconstructed P-frame, R1will be equal to E1+ EP1. In addition, if the mismatch error when decoding a P-frame to P2equal EP2the value of the error in the reconstructed P-frame P2will E1+ EP1+ EP2. Even if the individual mismatch errors are small, gradual accumulation of these errors can lead to large error.

Mismatch errors obtained when IDCT-processing used in the MPEG decoders in the sealing device and the expansion device, can be classified into two separate types:

Type (1): Errors resulting from inadequate operational accuracy.

Type (2): Errors that result from systematic differences due to rounding.

The MPEG standard establishes the requirement for operational accuracy, However, this requirement does not what may appear between devices IDCT, whose precision satisfies the requirement of MPEG.

Outputs IDCT-processing are integers. Therefore, after it was made IDCT-processing using real numbers, the processing results must be rounded. In the General case, the processing results are rounded to the nearest integer. However, the problem arises, if the processing result is a *. 5, where * is any integer. The MPEG standard does not specify how to round the result *.5. Some devices IDCT round *.5. the top and other devices IDCT round *.5. bottom. In addition, there are cases when rounding the top or rounding bottom depend on the sign of the result processing. Mismatch errors arising due to the just described systematic rounding errors are errors of Type mismatch (2).

Error Type mismatch (1) differ from the error Type mismatch (2), so that errors of Type (1) appear randomly at the time, as errors of Type (2) systematically. Because errors of Type (1) are random, positive errors and negative errors appear with approximately equal probability. Therefore, in the long run Kadirova hand, because of the mismatch errors of Type (2) are systematic and inherent in the IDCT-processing, such errors have the same sign. Accordingly, in the long run coding with prediction mismatch error will accumulate in one direction. Although each error Type mismatch (2) is only +1 or -1 if a lot of errors in one direction, the accumulation of mismatch error will be large.

As the error Type mismatch (1), although they are formed, after some time disappear, error Type (1) do not represent a big problem. On the other hand, because of the error of Type mismatch (2) accumulate in one direction, these errors represent the problem. In this regard, it is desirable to prevent accumulating error Type mismatch (2).

In the MPEG system1it was proposed to perform processing before IDCT-processing, in order to prevent errors of Type mismatch (2). Processing sets the transform coefficients of all components of odd values, except for the conversion component (0.0) macroblock, with intra-frame coding frame (intra-macroblock"). In intra the education components of (0.1), (7.1), (2.3), (5.3), (1.5), (6.5), (3.7) and (4.7) initially all equal 568. Since this is an even number, pre-treatment sets for these factors is odd is, for example, 567. If IDCT-processing is applied to pre-processed transform coefficients, fractional results will never appear.

Since the DC component of intra-macroblock is very important for the emergence of a frame received from a compressed signal of the moving image, the accuracy of its representation is limited to only 8 bits. It is not subject to conversion to an odd value, as this impairs the accuracy of this important component. On the other hand, all the transform coefficients resulting from the conversion of the macroblock of the frame is encoded using interframe coding ("naintre-macroblock"), are subjected to processing similar to the processing of the transform coefficients of the components other than the DC component of the intra-macroblock, to restrict the values of transformation coefficients only odd numbers.

Processing in which the values of transformation coefficients subjected to IDCT-conversion, are all odd values, called aouste seal, and in the expansion unit will be rounded in accordance with the General rule. This will allow you to maintain the quality of shared frames between the various expansion devices.

However, despite the above-described processing for odd, the above accumulated error Type mismatch (2) will appear in the MPEG processors due to the fact that the IDCT-obrabotka may produce results of type *.5, where * means integer. Conditions that lead to the result *.5 will be described below in an example two-dimensional 8 x 8 IDCT used in the MPEG system.

Two-dimensional 8 x 8 IDCT is described by the following equation:

< / BR>
< / BR>
In the above equation F(U, V) indicates the DCT-coefficients corresponding two-dimensional IDCT. In equation (1) each IDCT output value is a real number, that is, a rational number or irrational number. Because *.5 rational number, making the output value IDCT irrational number, it is possible to prevent accumulated errors mismatch. On the other hand, if the output value is a rational number, there is a probability that the output value is *.5.

DCT-coefficients F(0,0), is, output value of the IDCT is a rational number. The output value IDCT in this case is determined by the following equation (2):

(X,Y) = 1/4F(0,0)

< / BR>
< / BR>
< / BR>
where

< / BR>
Thus, if only one particular DCT coefficients F(0,0), F (0,4), F(4,0), F(4,4) has a non-zero value that is divisible by 4 but not divisible by 8, the output value will be equal to *.5.

If four special DCT-coefficient are the only coefficients with non-zero value, the output value IDCT is defined by equation (3):

< / BR>
Changing combinations of X and Y, f(X,Y) in equation (3) can have the following values:

1/8 [F(0,0) + F(0,4) + F (4,0) + F (4,4)]

1/8 [F(0,0) - F(0,4) + F (4,0) - F (4,4)]

1/8 [F(0,0) - F(0,4) + F(4,0) - F(4,4)]

1/8 [F(0,0) - F(0,4) - F(4,0) + F(4,4)] (4)

Thus, when the values of four specific factors are such that any of the expressions presented in equation (4) is divisible by 4 but not divisible by 8, will receive the result *.5.

Thus, if four specific factor have nonzero values, the probability is high that the IDCT output value that is equal to *.5.

Various symmetric pairs of DCT coefficients with non-zero values other than just discussed four specific factors may value and this value is a multiple of 4, but not a multiple of 8; or

(2) if a pair of coefficients X(2n+1, 2n+1), X(8-2n-1, 8-2n-1) has the same nonzero value, and this value is divisible by 4 but not divisible by 8.

In the above equations X(i,j) is the conversion of one component of a two-dimensional 8 8 DCT.

If the current signal of the moving image is sealed by the sealing device according to the MPEG system, it is often formed of non-zero DCT-coefficients in the just-mentioned combinations, which can give IDCT output value that is equal to *.5. In addition, the values of four special coefficients are non-zero most of the time.

Since the most common reason for the appearance of the *.5 is a combination of DCT coefficients, in which the values of four special coefficients are non-zero, preventing mismatch errors due to four specific factors will substantially reduce the likelihood of mismatch errors.

A processing method by which intra-macroblock and naintre-macroblock subjected to inverse sample rate MPEG1shown on Fig. 5. In Fig. 5 QAC(i, j) is (i,j)-th DCT-coefficient, Wi(i,j) is (i,j)-th element of the matrix of weights, the mquant avlab processing written in the syntax of the C programming language. The syntax of this language is described in Herbert Schildt, Using Turbo C. Osborne McGraw Hill (1988), in particular, pages 83 - 87.

Sampled DCT-coefficients are subjected to inverse sampling and the resulting DCT-coefficients, and then subjected to IDCT-processing. However, in the MPEG1for DCT-coefficients having an even value is added by +1 or -1, to be sure that all DCT-coefficients are subjected to IDCT-processing will have odd values. The result of this operation, when, for example, only one of the four special factors F(0,0) has a nonzero value, because there is a mismatch error when F(0,0) is divisible by 4 but not divisible by 8, if the DCT-coefficients are processed so that they all have an odd value, the result, if the DCT-coefficient was subjected to IDCT-processing may not be equal *.5. Similarly, if only one of the other four special factors F(0,4), F(4,0), F(4,4) has a nonzero value, the mismatch error will not appear. However, if more of the four special factors have a non-zero value, as can be seen from figure 4, or if there is a pair of symmetrically built coefficients, as in cases (1) and (2) above, the assignment of all DCT-koeffizienten odd value>will not prevent the appearance of accumulated mismatch errors when two or more DCT coefficients have a non-zero value. In addition, handling is odd MPEG1twice reduces resolution discretized conversion, because the conversion factors with even values are not allowed. This degrades the image quality. If you want high quality images, this is a problem. Obviously it is desirable to have the best way to avoid accumulating errors, inconsistencies, than that proposed in the MPEG1.

Considering the above problems encountered in previous projects, the purpose of this invention to provide a method and device that effectively prevent accumulated errors, inconsistencies, when the transform coefficients are subjected to inverse orthogonal transform, and in which the resolution conversion is not affected.

In particular, the present invention is a method and device for inverse orthogonal transformation coefficients of the transformation, which is effectively the method and device for processing a block of transform coefficients to perform inverse orthogonal transform block of transform coefficients, so to prevent rounding errors, when a block of transform coefficients is subjected to the inverse transformation.

In addition, the purpose of this invention is to provide a sealing device of a signal of a moving image expansion unit compressed signal of a moving image and recording medium for aggregated signal of the moving image, which excludes mismatch errors, and providing measures to prevent the impact of errors, inconsistencies, so they do not worsen the quality of the image.

The purpose of this invention involves an efficient and simple error prevention inconsistencies that cannot be prevented by known methods.

Accordingly, the invention provides a method for processing a set of conversion factors to obtain immune to errors of the set of conversion factors for processing by the inverse orthogonal transformation. Immune to errors, a set of transform coefficients is free from rounding errors, if it is subjected to inverse orthogonal transform. In this method, the conversion factors sumo sum is even, inverts the parity of one of the transform coefficients with the inverted parity. The conversion factor with the inverted parity makes the checksum is odd. In the end, a set of transform coefficients including the conversion factor with the inverted parity, provides immune to errors set.

The invention also provides a device for pre-processing the set of conversion factors to obtain immune to errors of the set of conversion factors for processing by the inverse orthogonal transformation. Immune to errors, a set of transform coefficients is free from rounding errors, if it is subjected to inverse orthogonal transform. The device contains a drive. The drive receives each of the transform coefficients in the set and summarizes them. Assessment scheme parity receives this amount from the drive and evaluates the parity of the sum. Scheme invert parity works when the scheme of assessment of the parity sets that checksum is even, and inverts the parity of one of the transform coefficients to obtain a ratio control amount is odd. In the end, the scheme generates a set of transformation coefficients, including the conversion factor with the inverted parity, as immune to errors.

In addition, the invention provides a method of inverse orthogonal transform of the set of transform coefficients without rounding errors. Each of the transform coefficients is represented by the binary number. In this way evaluated the low-order bit of each of the transform coefficients in the set. In the set of calculated conversion factors with a single bit. The result of counting is evaluated to determine whether it is an even number. If the account is estimated as an even number, one of the transform coefficients is modified to obtain a modified conversion factor. Modified conversion factor makes the result of counting odd number. In the end, a set of transform coefficients comprising a modified conversion, is subjected to orthogonal transformation.

The invention also provides a device for inverse orthogonal transform of the set of coefficients pre the Finance to get the amount and the scheme of assessment parity, which evaluates the parity of the sum. Scheme of bringing the values sum to an odd works when the scheme of assessment of the parity sets that checksum is even, and converts the parity of one of the conversion factors used to obtain the conversion factor with the inverted parity. The conversion factor with the inverted parity makes the sum is odd. In the end, the scheme of the inverse orthogonal transformation receives a set of conversion factors, including the conversion factor with the inverted parity, from the device, the final value of sum is odd.

The invention also provides a device for inverse orthogonal transform of the set of transform coefficients without rounding errors. The device contains a scheme of assessment the least significant bit to estimate the value of the lowest bit of each conversion. The counting circuit performs counting of those conversion factors for which the estimate is the least significant bit set, they are set to the least significant bit equal to one. Assessment scheme of the account assesses whether the result of counting of the counting schemes even number. Thus, the couple sets, the result is an even number, to change one of the transform coefficients to obtain a modified conversion factor. Modified conversion factor makes the result of counting odd number. In the end, the scheme of the inverse orthogonal transformation receives a set of transform coefficients including a modified conversion factor from the scheme to bring the account to an odd value.

The invention also provides a device for sealing a signal of the moving image. The signal of the moving image includes frames, and each frame is divided into blocks. The device comprises a predictive encoder, which encodes the predictive blocks signal of a moving image by using a block matching reference frame for forming blocks of differences. The encoder block differences compacts blocks of the differences coming from a predictive encoder to form a multiplexed signal of a moving image. The encoder block differences include the schema orthogonal transform, which performs orthogonal transform block of the differences coming from a predictive encoder for receiving blocks haupauge scheme orthogonal transformation, to obtain the compacted signal blocks. Multiplexed signal of a moving image is formed from compacted signal blocks.

The device also includes a local decoder, which extends compacted signal blocks received from the encoder unit differences, to obtain the restored blocks of differences without rounding errors, when compacted signal blocks are subjected to inverse orthogonal transform. The local decoder includes an inverse quantizer which performs inverse quantization of compacted signal blocks received from the encoder block differences, to obtain blocks of reconstructed transform coefficients. Drive summarizes the restored transform coefficients in each block of transform coefficients received from the inverse quantizer for receiving the amount, the parity which is assessed by the scheme of assessment parity. Device for reduction amounts to an odd value works when the scheme of assessment of the parity sets that checksum even to invert the parity of one of the restored transform coefficients in the block to obtain the conversion factor from inv the project receives the restored block of transform coefficients, including the conversion factor with the inverted parity, from the device, the final value of sum is odd. The scheme of the inverse orthogonal transform provides the restored blocks of differences.

The device also includes a predictive decoder that decodes with the restored prediction blocks of the differences coming from the local decoder to reconstruct the HR blocks corresponding to the blocks of the signal of the moving image. Finally, the device includes an image memory that stores the reconstructed blocks of frames received from the predictive decoder, in the form of blocks of the reconstructed frame to use as a reference frame for predictive coding of other frames of the signal of the moving image.

In the just described device drive circuit evaluation parity and device for reduction amounts to an odd value in the local decoder can be replaced: the scheme of assessment the least significant bit, which evaluates the low-order bit of each of the restored transform coefficients; a counter that provides a count of the restored transform coefficients in each block which have isolated the ICA even number; and a scheme to bring the account to an odd value, which works when the assessment scheme of the account States that the account is an even number, to change one of the restored transform coefficients in the block to obtain a modified conversion factor, which makes the result of counting odd number.

The invention also provides a device for expanding a compressed signal of the moving image to produce an output signal of the moving image. O signal of the moving image includes portions of the signal, each of which represents the output signal frame of the moving image. Fragments include encoded signal (variable length words) compacted signal blocks. The device has an inverse coder with variable word length, which applies reverse coding with variable word length code (variable length words) condensed signal blocks to ensure the compacted signal blocks.

The decoder expands the condensed signal blocks from the inverse variable-length words to obtain the restored blocks of differences without p the Decoder includes an inverse quantizer, which performs the inverse quantization of each compressed signal block of the encoder unit of differences to obtain the restored block of transform coefficients. Drive summarizes the restored transform coefficients in the block of transform coefficients received from the inverse quantizer for receiving the amount, the parity which is assessed by the scheme of assessment parity. Device for reduction amounts to an odd value works when the scheme of assessment of the parity sets that checksum even to proinvestirovatj parity of one of the restored transform coefficients in the block to obtain the conversion factor with the inverted parity, which will make the checksum is odd. The scheme of the inverse orthogonal transform unit receives the recovered transform coefficients, including the conversion factor with the inverted parity, from the device, bringing the sum to an odd value, and provides the restored blocks of differences.

The device also includes a predictive decoder that decodes with the restored prediction blocks of the differences coming from the decoder, for resonse from predictive decoder, in blocks of the reconstructed frame. The reconstructed frame is used as a reference frame for predictive decoding of other frames of the signal of the moving image. Finally, the device includes a circuit that reads the output signal of the moving image from the memory image.

In the just described device expansion drive, the scheme of evaluation of parity and device for reduction amounts to an odd value in the decoder can be replaced by a scheme of assessment the least significant bit, which evaluates the value of the least significant bit of each of the restored transform coefficients; a counter that provides a count set of transform coefficients in each block with a single value low-order bit; the scheme of assessment of the account, which establishes whether the account is an even number; and a scheme to bring the account to an odd value, which works when the assessment scheme of the account States that the account is an even number, to change one of the set of transform coefficients in the block to obtain a modified conversion factor, which makes the result of counting odd numbers
Platonova signal of the moving image. In this way it blocks the signal of the moving image is applied predictive coding and orthogonal transform to obtain the blocks of transform coefficients, which is formed multiplexed signal of the moving image. The amount of blocks of transform coefficients are odd value, before applying the inverse orthogonal transform and predictive decoding to obtain the blocks of the reconstructed frame to use as a reference frame predictive coding of other frames of the signal of the moving image.

The image also provides a method of multiplexing signal of the moving image, providing a multiplexed signal of a moving image. In this way reveals the movement between the blocks of the frame signal of the moving image and the blocks of the reconstructed image signal serving as a reference signal and to a reference frame applies motion compensation in response to detection of the movement to form the blocks matching the reference frame. The blocks matching the reference frame used in predictive coding of blocks of signals of the moving image, to obtain a block ulitmately signal is formed from the blocks of transform coefficients by applying the sampling and coding with variable length words. Before applying inverse orthogonal transform to the blocks of transform coefficients to obtain blocks of restored differences, the sum of each block of transform coefficients is reduced to an odd value, to prevent rounding errors in the process of the inverse orthogonal transformation. And finally, the blocks of the restored difference is applied predictive decoding to obtain the blocks of the reconstructed frame to use as a reference frame when using predictive coding to other frames of the signal of the moving image.

Finally, the invention provides a recording medium on which is recorded multiplexed signal of a moving image representing the moving image. Multiplexed signal of a moving image is generated from the signal of the moving image through the use of predictive coding and orthogonal transform to the blocks of the signal of the moving image to obtain a block of transform coefficients, which is formed multiplexed signal of the moving image. The amount of blocks of transform coefficients are odd value to preobrazovaniya, to get the blocks of the reconstructed frame to use as a reference frame predictive coding of other frames of the signal of the moving image.

Now according to the invention will be described in a way that prevents the emergence of accumulating errors inconsistencies.

Analysis of equation (4) shows that the discrepancy appears when the expression in equation generate the (2n+1)/2, where n is any integer.

Equation (4) can be written as

f(X,Y)= 1/8 ACC,

where

ACC is the sum of all coefficients.

The most common type of non-conformities:

f(X,Y) = 1/8 ACC = (2n+1)/2 = 1/8 (4*(2n+1))

This shows that, if the ACC to make an odd number, the mismatch error will never appear.

Accordingly, the present invention uses a scheme involving inverse quantization of the DCT coefficients, and then to the IDCT processing, calculation of the amount of DCT coefficients. If the sum of the DCT coefficients is an even number (i.e., the checksum is even), changes the parity of one of the factors to make an odd amount DCT coefficients (i.e., to make the checksum is odd). It is enough to change the parity of the s parity ratio, which has the least influence on the output value of the IDCT. In other words, this invention, by checking the parity of the sum of the DCT coefficients to the IDCT processing and, if the checksum is even, by changing the parity of one of the DCT coefficients to adjust the amount of DCT coefficients to an odd value, effectively prevents errors inconsistencies.

It should be emphasized that according to the invention it is enough to change the parity of only one DCT coefficient to make the odd sum of DCT coefficients. MPEG1makes all odd DCT coefficients, which is twice reduces resolution DCT coefficients are subjected to IDCT processing. On the other hand, the procedure to prevent errors inconsistencies according to the present invention makes the sum of the DCT odd in such a way as to not significantly reduce the accuracy of providing input and output values IDCT. When applying the method according to the present invention, in the sealing device of the signal of the moving image, in the device extension of the compacted signal of a moving image or a device for transmitting a compressed signal of the moving image, the deterioration of image quality rudementary sampling rate may be equal to 1, in contrast to the known method, in which the minimum sampling rate was set to 2.

A brief description of the accompanying drawings

In Fig.1 presents a block diagram showing the structure of a known sealing device signal of the moving image according to the MPEG system.

In Fig.1 presents a block diagram showing the structure of the known device expansion signal of the moving image according to the MPEG system.

In Fig.3 shows the sequence of the seals signal of the moving image in the MPEG system.

In Fig.4 shows working examples of the values of the DCT coefficients.

In Fig.5 shows the processing steps used to perform a sample rate of intra-macroblocks and naintre-macroblocks in the known system MPEG1.

In Fig.6 presents a block diagram showing the structure of the first variant of the device of the seal of the signal of the moving image according to the invention.

Fig. 7 shows how to read the block of DCT coefficients using a zigzag scan.

Fig. 8 is a block diagram of a first practical option schemes odd cast to the sum of 14, shown in Fig.6.

In Fig. 10A shows a block diagram of the second option schemes odd cast to the amount shown in Fig.6.

Fig. 10B shows the change in the second option schemes odd cast to the amount shown in Fig.6.

In Fig. 11 shows a block diagram of the first variant of the inverter parity shown in Fig.8.

In Fig. 12 presents a block diagram illustrating a second variant of the above-mentioned inverter parity.

In Fig.13 shows a block diagram of a second variant of the above-mentioned inverter parity.

In Fig.14 presents a block diagram explaining the operation of the third variant of the above-mentioned inverter parity.

In Fig. 15 is a block diagram of a third variant of the above-mentioned inverter parity.

In Fig. 16 shows a block diagram for explaining a fourth variant of the above-mentioned inverter parity.

In Fig. 17 shows a block diagram of a fourth variant of the above-mentioned inverter parity.

In Fig. 18 presents a flowchart of the third option schemes odd cast to the amount shown in Fig.6.

In Fig.19 shows a block diagram of obreteniyu.

Fig.20 is a block diagram of the inverse quantizer and devices bring to the odd amount in the expansion unit of the compacted signal of the moving image shown in Fig.19.

In Fig. 21 presents a time chart explaining the operation of the above-mentioned inverse quantizer and devices bring to an odd amount.

In Fig.22 is a block diagram of the structure of the second variant of the device of the seal of the signal of the moving image according to the invention.

In Fig.23 shows the block diagram of the first variant of the scheme to bring the odd amount in the second embodiment of the sealing device signal of the moving image shown in Fig.22.

In Fig.24 shows a block diagram of a second variant of the scheme to bring the odd amount in the second embodiment of the sealing device signal of the moving image shown in Fig.22.

In Fig. 25 shows a block diagram of a third variant of the scheme to bring the odd amount in the second embodiment of the sealing device signal of the moving image shown in Fig.22.

Fig. 26 is a block diagram of a variant of the inverter parity schemes odd cast to the amount shown n the LASS="ptx2">

In Fig. 28 shows the second change in the inverter parity shown in Fig.26.

In Fig. 29 shows a third change in the inverter parity shown in Fig.26.

In Fig.30 shows a block diagram of the structure of the second variant of the device of the expansion of the compacted signal of a moving image according to the invention.

The best variant embodiment of the invention

Now with reference to the figure will be described preferred embodiments of the method of the inverse discrete cosine transform device inverse cosine transform, the sealing device signal of the moving image, the device extension of the compacted signal of the moving image, media recording and transmission device.

The invention is applicable to the hybrid system encoding which combines predictive coding with motion compensation and discrete cosine transform (DCT). This hybrid coding system described in the H. 261 of ISO-IEC/JTC1/SC2/WG11 (usually referred to as MPEG) CCITT (International Consultative Committee on Telegraphy and Telephony), which is the International Committee for publications, including h is stored on recording media. The basic configuration of the hybrid system with MPEG encoding is well known. Section WG11 includes a useful Glossary of used terms.

Predictive coding with motion compensation is a way to reduce the redundancy signal of a moving image by using the correlation signal of the moving image in the time domain. The prediction motion compensation of the current frame (i.e. frame, which is now encoded ) is performed using a different, already decoded frame of the moving image as a reference frame. Errors resulting from the prediction with motion compensation, are included in the multiplexed signal together with the motion vector, prediction mode, and so on, This significantly reduces the amount of information in a compressed signal of the moving image, are required to represent the current frame.

The error signal prediction with motion compensation is sealed by using the sealing device signal, which uses the spatial correlation of each frame forming the moving image. The sealing device signal differences usually includes a scheme of orthogonal pereobrazovat power signal into separate frequency components as a result of intra-frame (frame or field) two-dimensional correlation image. Thus, only the concentrated and distributed coefficients included in the multiplexed signal, either directly or after additional seals. It even reduces the amount of information in a compressed signal of the moving image, are required to represent the current frame.

Interframe predictive coding with motion compensation can be performed between frames of the signal of the moving image. Alternatively, if the signal of the moving image is thickened (interlaced) signal, predictive coding with motion compensation can be performed between the fields. In addition interframe predictive coding with motion compensation may be included between adaptive interframe coding and mesolevel encoding depending on the characteristics of the signal of the moving image.

I. a First variant embodiment of the invention

The draft version of the device configuration signal compaction of the moving image, in which the invention is applied, is shown in figure 6. In the apparatus shown in Fig.6, the signal of the moving image is divided into frames and compacted frame by frame. Each frame is divided into personnel units personnel unit is controlled by the unit frame, called the current frame.

The signal of the moving image, usually a video signal that is delivered to the first memory device frame 2, which is temporarily stored in the multiple frames of the signal of the moving image. The memory controller 3 controls the reading frame from the first memory device frame 2 and the second memory device frame 4. The memory controller 3 also delivers the start signal layer SS and signal the beginning of the macro BS to the counter/layer macroblock 5. The memory controller delivers these signals synchronously respectively to each layer and each macroblock of each frame (for example, the current frame) is read from the first memory device frame 2 for sealing. Layer is a horizontal line of blocks, showing the entire width of the frame.

Device motion prediction 6 performs the prediction of the movement by the block matching block of the current frame with many blocks of previous and subsequent frames stored in the first memory device frame 2. Mapping blocks is performed using blocks, for example, 16 x 16 elements. The signal indicating the reference frame motion prediction generated by the memory controller 3 selects the previous blocks or PEFC is. Device motion prediction 6 then delivers to the motion compensator 7, in the form of a motion vector MV, place a block in a previous or subsequent frames stored in the first memory device of frames for which the differences between the block and the current staffing unit, that is, the prediction error of the motion will be minimal.

In response to the motion vector MV of the motion compensator 7 causes the block to each of the reconstructed frames stored in the second memory device frame 4, to read as a potential block mapping. Place in the reconstructed frames from which the read potential blocks mapping is determined by the motion vector MV. The signal indicating the reference frame motion compensation from the memory controller 3 then selects one of the potential blocks mapping read from the second memory device frame 4 as the block mapping for the current block. The reconstructed frames stored in the second memory device 4 frames are frames that have been reconstructed through local decoding discretized DCT coefficients generated by the encoder unit differences 9, which will be described below.

Reconstructed cnia, depends on the prediction mode of the current frame. In direct mode prediction block mapping is selected from the previous reconstructed frame. In bidirectional mode prediction block mapping is selected from the previous reconstructed frame, the next reconstructed frame or may be formed by performing a linear operation (e.g., calculation of average values) over the blocks of the previous reconstructed frame or the next reconstructed frame. Finally, if the current frame is coded in the intraframe encoding mode, that is, the frame is encoded without prediction, as the block matching is used, the zero block in which the value of all elements set to zero. Blocks mapping read from the second memory device frame 4, adaptive change so that for each block of the signal of the moving image was chosen as the optimal block matching.

The motion compensator 7 selects a prediction mode for each frame by first calculating the sum of absolute values of differences between an element by element between the block of the current frame and potential blocks mapping, ponorogo this amount is minimal. The motion compensator signal mode prediction MM, which indicates the selected prediction mode to the encoder with variable word length 17 which will be described below. The motion compensator 7 causes the second memory device frame 4 to give the unit map S2for the selected prediction mode in a method of forming differences 8.

The scheme of formation differences 8 also receives the block of the current frame S1signal of the moving image read from the first memory device frame 2, and calculates an element by element the difference between the block of the current frame S1and the unit map S2. The scheme of formation differences produces the output block differences S2in the encoder block differences 9. The encoder block differences 9 seals the block differences S3to form a block discretized conversion factors SC. Block discretized conversion factor SC is supplied to the local decoder 10, where it is expanded to obtain the restored block of the differences S4. The local decoder 10 in the sealing device of the signal of the moving image has a structure similar to the device extension of the compacted signal of the moving image, culici 9 and the local decoder 10.

The encoder block differences 9 includes a circuit DCT quantizer 11 and 12, as shown in figure 6. The DCT scheme 11 applies DCT processing to perform the orthogonal transform block of the differences S3their shaping circuit block differences 8. The DCT scheme 11 is fed the output block of DCT coefficients to the quantizer 12. The quantizer 12 discretetime block DCT-coefficients to obtain block discretized DCT coefficients SC.

The local decoder 10 comprises an inverse quantizer 13, schemes odd cast to the sum of 14 and the IDCT circuit 15, as shown in figure 6. The inverse quantizer 13 uses a quantization table for the inverse of the sampling unit discretized DCT-coefficients SC from the quantizer 12. Scheme of bringing to an odd amount performs an operation of inverting the parity over the resulting block of DCT coefficients, if the sum of the DCT coefficients is not an odd number. This prevents mismatch errors when a block of DCT coefficients with the odd amount is subjected to inverse orthogonal transform. The IDCT circuit 15 performs inverse discrete cosine transformation (IDCT) on the block of DCT coefficients with the odd amount postupalsky described the process of sampling, performed by the quantizer 12. Each block of 8 8 DCT coefficients is sampled. Each block of the frame shear-mode intra-frame coding (I-frame) is called in the intraframe coding mode (I-frame) is called intra-macroblock. Each block, compacted mode interframe coding, called naintre-macroblock. When intra-macroblock is subjected to orthogonal transform, DCT-coefficient component (0,0) is the DC coefficient. DC-coefficient of the discretized by dividing rounding DC-coefficient 8, if the discretization is carried out with 8-bit precision; it is divisible by 4 if the discretization is carried out with 9-bit precision; is divisible by 2, if the discretization is carried out with 10-bit precision; and is divided into 1, if the discretization is carried out with 11-bit precision. The DC component of intra-macroblock is sampled according to the following equations, which are written in the syntax of the C programming language:

QDC = dc//8 (8 bits)

QDC = dc//4 (9 bits)

QDC = dc//2 (10 bits)

QDC = dc//1 (11 bits) (5)

where dc is the DC coefficient, and QDC-discretized DC coefficient.

DCT-coefficients, different from the DC-coefficient, which is the result of orthogonalisation ac-(i,j) by weighting the DCT coefficients ac(i,j) using the weighting matrix Wiaccording to the following equation:

ac-(i,j) = (16ac(i,j))//Wi(i,j) (6)

The coefficients of the weighting matrix Wilook as follows:

Wi=

8 16 19 22 26 27 29 34

16 16 22 24 27 29 34 37

19 22 26 27 29 34 34 38

22 22 26 27 29 34 37 40

22 26 27 29 32 35 40 48

26 27 29 32 35 40 48 58

26 27 29 34 38 46 56 69 (7)

Then by using the following equation coefficients sampling ac-(i, j) is discretized to determine the levels of discretization QAC(i,j) corresponding AC coefficients.

< / BR>
In the above equation, p and q are arbitrary integers constants, for example p = 3 and q = 4, and mquant-discretized factor.

DCT coefficients resulting from the orthogonal transform macroblock interframe coding (naintre-macroblock), is discretized by defining coefficients sampling ac-(i,j) by weighing all DCT coefficients obtained by converting "naintre macroblock, using the weighting matrix Wnaccording to the following equation:

ac-(i,j) = (16ac(i,j)//Wn(i,j) (9)

The coefficients of the matrix TOD is 20 21 22 23 24 25

19 20 21 22 23 24 26 27

20 21 22 23 25 26 27 28

21 22 23 24 26 27 28 30

22 23 24 26 27 28 30 31

23 24 25 27 28 30 31 33 (10)

Then, using the following equation, discretized coefficients sampling ac-(i, j) to determine the levels of discretization QAC(i,j) of the AC coefficients.

QCT(i,j)

= ac-(i,j)/(2mquant) if (mquant=odd);

= ac-(i,j)+1/(2mquant) if (mquant=even and ac-< 0);

= ac-(i,j)-1/(2mquant) if (mquant=even and ac->0) (11)

The resulting discretisation levels QCT(i,j) are fed to the encoder with variable word length 17 and the local decoder 10 in the form of the above block discretized DCT coefficients SC.

Encoder with variable word length 17 applies the encoding variable length words to block discretized DCT coefficients obtained by the sampling block of DCT coefficients. Encoder with variable word length 17 determines the difference between the discretized by the conversion factors in four blocks of luminance, forming each macroblock, and the DC coefficient of the corresponding intra-macroblock. Then the encoder with variable word length, uses a table of encoding with variable-length words for the application of encoding with variable-length words is AMI brightness, that means that the DC coefficients are essentially the same value. Encoder with variable word length 17 also determines the difference between the discretized coefficients of the two blocks of color differences and uses a table of encoding with variable-length words to do the encoding with variable word length of the resulting values of the differences. Table encoding with variable word length of the coefficients of the luminance and table for differences in color are different from each other.

Encoder with variable word length 17 applies the encoding variable length words to block discretized DCT coefficients by reading block discretized DCT coefficients in a zigzag scan order, starting with the DCT-coefficient component (0,0), as shown in figure 7. Block discretized DCT coefficients are read in zigzag scan order, because the non-zero DCT-coefficients resulting from the DCT-processing, usually concentrate with neighborhood component (0,0). Thus, the reading of the DCT coefficients in zigzag order improves coding efficiency with variable word length by increasing the number following each variable word length 17 reads the DCT-coefficients in the zigzag scan order and determines the value (in other words, level) of each non-zero DCT coefficient and the number (in other words, the number) of the previous zero DCT coefficients. This is done through a two-dimensional coding with variable word length of block DCT coefficients. After encoding the coefficients in the block are expressed through the value of the number and par levels. Encoder with variable word length add 2-bit code, EOW, which indicates a non-zero DCT coefficient, which is the last non-zero DCT-coefficient. Encoder with variable word length 17 delivers the address of the last non-zero coefficient in zigzag scan order to the inverter address (not shown). The Converter converts the address address in zigzag scan order to the address EOB-adrs in the raster scanning order. Encoder with variable word length gives the address EOB-adrs in the scheme of bringing to the odd $ 14.

Scheme of bringing to an odd amount of 14 stores the address EOB-adrs in the solution of the scanning order in the register 25, shown for example in Fig. 8, which will be described below.

Now will be described an inverse quantizer 13. The inverse quantizer 13 receives the block discretized DCT coefficients SC from the encoder is to teach a block of DCT coefficients. Practically, the inverse quotwater 113 performs inverse quantization of discretized DCT coefficients resulting from the orthogonal transform intra-macroblock using the processing defined in equation (12) to obtain the corresponding DCT-coefficients. The inverse quantizer 13 performs inverse quantization of AC coefficients resulting from the orthogonal transform intra-block, by using the processing defined in equation (13). Finally, the inverse quantizer 13 performs inverse quantization of all discretized coefficients resulting from the orthogonal transform naintre macroblock by using the processing defined in equation (14).

res (0,0) = 8QDC

res (0,0) = 4QDC (9 bits)

res (0,0) = 2QDC (10 bits)

res (0,0) = 1QDC (11 bits)

res (i,j) = (mquant2QAC(i,j)Wi(i,j))/16,

if (QAC(i,j)=0)

res (i,j) = 0,e,

if (QAC(i,j)>0)

res(i,j)=((2QAC(i,j)+1) mquantWi(i,j))/16,

if (QAC(i,j)<0)n(i,j))/16,

if (QAC(i,j)=0)

res (i,j)=0 (14)

The resulting block of DCT coefficients supplied from the inverse of katevatis 12 in the circuit of odd cast to the sum of 14, a practical example which is in the surrounding area 21 and the parity inverter 28. Drive 23A evaluates the sum of the DCT coefficients in the block of DCT coefficients received from the inverse quantizer 13. Assessment scheme parity 21 determines whether the sum of the DCT coefficients determined by the drive 23A, an odd or even number, i.e., even or odd checksum DCT coefficients. Only in the case when the scheme of assessment of the parity sets that checksum DCT-coefficientof is even, the parity inverter 28 changes the parity of at least one of the DCT coefficients in the block to do a checksum of the DCT-coefficientof odd, that is, converts the sum of the DCT-coefficientof to an odd value. This prevents mismatch errors when the block DCT-coefficientof converted with an odd amount of schemes odd cast to the amount of 14 is subjected to inverse orthogonal transformation by the IDCT circuit 15.

The counter 20 counts the number of DCT-coefficientof received from the inverse quantizer 13, and supplies the result of counting coeff-adrs in the scheme of assessment parity 21 and the selector memory 22.

Drive 23A consists of the adder 23 and the register 24. The adder 23 adds each DCT coefficient in the block DCT-coefficientof received from inverse the W after it was determined amount for each block of DCT coefficients. The resulting sum of the DCT coefficients supplied from the adder 23 in the register 24 and the scheme of assessment parity 21. The drive 23 need only the sum of the least significant bit of the DCT coefficients in the block, to get the result, suitable for assessment scheme, parity, to establish whether the checksum DCT coefficients is odd or even.

Assessment scheme parity 21 sets whether the checksum DCT coefficients in the block of DCT coefficients is odd or even, in response to the value of the account coeff-adrs received from the counter 20. If all coefficients in the block is delivered to the drive 23A value coeff-adrs indicates that the drive 32A determined the amount of all DCT coefficients in the block. In response to the value of the account coeff-adrs assessment scheme parity 21 sets whether the checksum DCT coefficients from the memory 23A is odd or even. For example, in the case of two-dimensional 8 8 DCT transform, the scheme of assessment particular 21 sets whether the checksum DCT coefficients from the drive 23A odd or even, when the value of coeff-adrs specifies that all 64 DCT-coefficient delivered in the memory 23A.

1the parity inverter 28 to force the parity inverter to perform an operation of inverting the parity. In response to the reset signal processing REQ1the parity inverter 28 changes the parity of at least one (i.e., an odd number) DCT coefficients to assign odd is the sum of the DCT coefficients. On the other hand LSB with a single value indicates that the checksum is odd. In this case, the scheme of assessment parity 21 does not generate a reset signal processing REQ1and the parity inverter 28 leaves the parity of all the DCT coefficients in the block unchanged.

In the shown practical scheme DCT-coefficients from the inverse quantizer 13 is written in the first memory 26 or the second memory 27 via the selector memory 22. The selector memory 22 operates depending on the value of the account coeff-adrs received from the counter 20. Thus, for example, if the selector memory 24 determines that all of the DCT-coefficients in the block is placed in the first memory 26, the selector allocates memory and the other the other DCT coefficients are placed alternately in the first memory 26 and the second memory 27. When all DCT-coefficients in the block are listed in either the first memory or the second memory 27, a memory in which are stored all DCT-coefficients in the block, sends a signal memory FULL1 or FULL2 in the parity inverter 28.

When the parity inverter 28 receives the signal memory FULL1 or signal memory FULL2, it sends a signal to enable reading RD-EN1 or RD-EN2 in the memory, the signal provided by the memory. This causes the flow of block DCT coefficients from the memory with the generated signal to the memory to the inverter parity. The parity inverter processes the block of DCT coefficients read from the memory in one of two ways depending on whether formed any scheme of evaluation parity 21 reset signal processing REQ1. When the parity inverter 28 receives the reset signal processing REQ1he inverts the LSB of one of the DCT coefficients in the block, for example, the last non-zero coefficient in zigzag scan order. The parity inverter identifies the DCT coefficient whose parity may be proinvestirovany with the address of the DCT coefficients whose parity may be proinvestirovany, which is stored in the register 25. For example, in Fig. 8 shows the example of the DCT coefficient, whose parity may be proinvestirovany is the last nonzero coefficient. If the parity inverter 28 preinventory parity DCT coefficient whose parity may be proinvestirovany, the checksum is non-zero coefficients in the block from first to last will be odd. The parity inverter 28 delivers all DCT coefficients other than the DCT coefficient with inverted LSB, to the IDCT circuit 15 with the same state of their LSB. The parity inverter 28 also carries the DCT coefficient whose parity may be proinvestirovany, in the IDCT circuit with the state of its LSB, depending on whether it received the inverter parity signal reset processing REQ1.

The parity inverter 28 may be provided with a computer or digital processor, running, for example, according to the block diagram shown in figure 9. In this example, the DCT coefficient whose parity is allowed to invert, is the last non-zero coefficient. In step S1the parity inverter 28 evaluates to the address EOB-adrs, whether processed DCT coefficient of the DCT coefficient whose parity is allowed to be inverted by inverting its LSB. If the result of step S1is YES, execution proceeds to step S2. Otherwise, when enosti 28 determines if the reset signal processing. If the result of step S2is YES, which indicates the receipt of the reset signal processing, execution proceeds to step S3. Otherwise, if you have not received a reset signal processing, execution proceeds to step S5.

In step S3the parity inverter 28 inverts the LSB of DCT coefficient whose parity is allowed to invert to invert its parity and, therefore, to change the parity of the sum of the DCT coefficients. Execution proceeds to step S4where DCT coefficient with proinvestirovanno parity is supplied to the IDCT circuit (figure 10A). Execution then returns to step S1, where it is processed next DCT coefficient.

Execution proceeds to step S5if processed DCT coefficient is not the DCT coefficient whose parity is allowed to invert, or if the DCT coefficient whose parity must be proinvestirovany should not have proinvestirovanno parity, that is, if you have not received the reset signal processing REQ1. In step S5The DCT coefficient is supplied to the IDCT circuit 15 without change. Then execution jumps to step 1, where it is processed next DCT coefficient.

If the DCT coefficients is Mr. code. On the other hand, if the DCT coefficients are represented by a sign and an absolute value above the LSB is represented by an absolute value.

The circuit configuration of the odd cast to the amount of 14 is not limited to what is represented on figure 8. For example, in the scheme of bringing to an odd amount, shown in figure 10A, the added detector 29, and the logical element "Exclusive OR" 30 replaces the adder 23 in the scheme of bringing to an odd amount on the figure 8. The circuit elements shown in figure 10A, corresponding to the circuit elements shown in figure 8, indicated by the same numeric references and re-described here will not be.

In Fig. 10A detector LSB 29 selects the LSB of each DCT coefficient in the block of DCT coefficients. The element of the "Exclusive OR" 30 performs an Exclusive OR operation with each DCT coefficient in the block and stored in the register 24 is exclusive logical sum LSB of DCT coefficients in the block that have already been processed. Thus, the element of Exclusive-OR 30 and the register 24 calculates an exclusive logical sum of the LSB of DCT coefficients in each block. Combining logic gate Exclusive-OR 30 and the register 24 can be considered as counting unit DCT coefficient OR 30 will indicate whether the result of calculation of DCT coefficients having a single LSB, even or odd. Then the scheme of assessment parity 21 outputs a signal REQ1if the result of the calculation of DCT coefficients having a single LSB is even.

In Fig. 10B shows an alternative structure, which can be replaced element "Exclusive OR" 30 and the register 24. In her LSB of each DCT coefficient received from the inverse quantizer 13, served from LSB detector 29 on the logical element "And" 88. Element "And" skips to the counter 89 only the LSB with a single value. At the beginning of each block of DCT coefficients, the counter is reset and counts each LSB with a single value which he has received. LSB of the account COUNT from the counter 89 is fed into the scheme of assessment parity 21. By the end of each block assessment scheme parity defines the parity LSB of the COUNT of the counter 89. If there is an odd COUNT value (i.e., the LSB of COUNT - unit), it means that the block is an odd number of DCT coefficients with a single LSB and that the checksum DCT coefficients is odd. On the other hand, if the result COUNT is even (that is, LSB COUNT is zero), it means that the checksum DCT coefficients in the block is even.

Heat and 28 in the scheme of bringing to an odd amount, shown in figure 8 and 10A. The parity inverter 28 consists of a counter reading 61, the address comparator 62, an inverter 63 LSB, logical elements "And" 64, 65, 67 and 68, the logical element "OR" 66 and 69, inverters 71 and 72.

The parity inverter 28 operates as follows. When the counter reading 61 receives the signal from the memory is FULL from the first memory 26 and the second memory 27, it delivers the signal of destruction read RD-EN in the first memory 26 or the second memory 27. The enable signal reading makes the corresponding memory sequentially to give the stored DCT coefficients in the block of DCT coefficients to the first element And 67 on the channel indicated by any .rdata.

Signal the memory is FULL causes the counter 61 to start the counting of the received DCT coefficients, and to submit to the comparator 62 the account showing the number of received DCT coefficients. The comparator 62 compares the invoice with the address obtained from the register 25 to determine whether the DCT coefficient from the first logical element And 67, the DCT coefficient whose parity is allowed to invert, that is, the DCT coefficient whose LSB is allowed to invert. In the example shown in figure 11, the DCT coefficient, e is the rotary address EOB-adrs, which is stored in the register 62. If the account is equal to the address of the DCT coefficient whose parity is allowed to invert, in this example, EOB-adrs, the comparator 62 determines that the DCT coefficient is the DCT coefficient whose parity is allowed to invert, and changes the state of its output from 0 to 1.

The output of the comparator 62 is applied directly on the second logical element And 68 and through an inverter 72 to the first logical element And 67. Thus, if the account is not equal to the address EOB-adrs, the first logical element And 67 is opened, and the second element And 68 is closed. Therefore, the DCT coefficients are without change through the logic element And 67 and the logical element "OR" 69 to the IDCT circuit 15.

On the other hand, if the DCT coefficient supplied to the parity inverter 28 is the DCT coefficient whose parity is allowed to invert, and the counter value is equal to the address of the coefficient whose parity is allowed to invert, in this example, EOB-adrs, the output of comparator 62 changes its state, as described above. This leads to the closure of the first logic element And 76 and the opening of the second logic element And 68. In the DCT coefficient with proinvest the economic element "OR" 69 in the IDCT circuit 15.

DCT coefficient with inverted LSB selectively delivered to the IDCT circuit 15 in response to the reset signal processing REQ1by submitting DCT coefficients obtained by any .rdata channel, the third logical element "And" 64 and the inverter 63 LSB. The reset signal processing REQ1served from evaluation schemes parity 21 directly on the fourth logical element "And" 65 and through an inverter 71 to the third logical element "And" 64. The inverter LSB 63 inverts the LSB of each DCT coefficient obtained by any .rdata channel, and delivers the resulting DCT coefficient with inverted LSB to the fourth logical element "And" 65.

The absence of the reset signal processing REQ1, i.e., the reset signal processing in the zero state, indicates that the DCT coefficient whose parity is allowed to invert must be delivered to the IDCT circuit without inverting its LSB. The reset signal processing with zero status opens the third logical element "And" 64 and closes the fourth logical element "And" 65. In the DCT coefficient whose parity is allowed to invert, with the same LSB is served from any .rdata channel to the IDCT circuit 15 via the third logical element "And" 64, the logical element "OR" 66, the second logic element And 68 and the logical element "OR"boundary condition, indicates that the DCT coefficient whose parity is allowed to invert must be delivered to the IDCT circuit with inverted LSB to change the parity of the sum of the DCT coefficients. The reset signal processing with single condition closes the third logical element "And" 64 and opens the fourth logical element "And" 65. In the DCT coefficient whose parity is allowed to invert, inverted LSB is supplied from the inverter 63 LSB to the IDCT circuit 15 through the fourth logical element And 65, the logical element "OR" 66, the second logic element And 68 and the logical element "OR" 69.

Now will be described with reference to Fig. 12 a second embodiment of the parity inverter 28. When the second variant of the parity inverter 28 receives the reset signal processing REQ1he changes the sum of the DCT coefficients in an odd value by adding 1 to the DCT coefficient whose parity is allowed to invert.

The second variant of the parity inverter 28 may be provided with a computer or digital processor that operates according to the flowchart shown in Fig. 12. The block diagram shown in Fig. 12, similar to the flowchart shown in Fig. 9, except that operations performed in step S3. In step S3verificando, whose parity is allowed to invert, instead of inverting the LSB of DCT coefficient whose parity is allowed to invert. The DCT coefficient whose parity is allowed to reverse, may be, for example, the last nonzero coefficient in the block, or DCT coefficient of the high-frequency component in the block.

Now will be described with reference to Fig. 13 practical structure of the second variant of the parity inverter, in which the unit is added to the DCT coefficient whose parity is allowed to invert to make the odd sum of DCT coefficients in the block of DCT coefficients. The second variant of the parity inverter shown in Fig. 13, similar to the first embodiment of the parity inverter 28, shown in Fig. 11. The elements in the circuit shown in Fig. 13, the corresponding elements in the circuit shown in Fig. 11, designated by the same numeric references and again not described here.

The parity inverter shown in Fig. 13, includes +1 adder 73 instead of the inverter 63 LSB shown in figure 11. +1 adder 73 adds one to each DCT coefficient read from the first memory 26 or the second memory 27 and received through the channel of any .rdata. One of the DCT coefficients appended with a unit selected in toofani inverter parity, it is shown in Fig. 13, similarly to the operation of the circuit shown in Fig. 11, except that the +1 adder 73 adds one to each DCT coefficient obtained by any .rdata channel. Also, if there is a reset signal processing REQ1and found DCT coefficient whose parity is allowed to invert DCT coefficient appended with a unit is fed from the +1 adder to the IDCT circuit 15 through the fourth logical element "And" 64, the logical element "OR" 66, the second logic element And 68 and the logical element "OR" 69.

Now with reference to Fig. 14 and 15 will be described a third embodiment of the parity inverter 28.

When the third variant of the parity inverter receives the reset signal processing REQ1he makes an odd amount of DCT coefficients in the block by replacing the DCT coefficient whose parity must be proinvestirovany, the DCT coefficient whose parity must be proinvestirovany and from which is subtracted the unit, if the sign of the DCT coefficient is positive and which added to the unit, if the sign of the DCT coefficient is negative. This treatment not only inverts the parity of the DCT coefficient whose parity must be proinvestirovany, but also reduces the value of this DCT coefficient that is used for DCT coefficient, whose parity must be proinvestirovany, is determined by the following equation:

if (res > 0)

res = res - 1

if (res < 0)

res = res + 1, (15)

where res is the DCT coefficient whose parity must be proinvestirovany.

The third variant of the parity inverter 28 may be used with a computer or digital processor that operates according to the flowchart shown in figure 14. In step S1the parity inverter 28 to the address EOB-adrs sets whether or not the DCT coefficient of the DCT coefficient whose parity is allowed to invert. For example, the inverter parity sets whether or not the DCT coefficient is the last non-zero DCT coefficient. If the result of step S1is "YES" and the DCT coefficient is the DCT coefficient whose parity is allowed to invert, execution proceeds to step S2. Otherwise, if the DCT coefficient is not the DCT coefficient whose parity is allowed to invert, execution proceeds to step S8.

In step S2the parity inverter 28 determines whether received or not the reset signal processing REQ1. If the result of step S2is "YES", indicating that the reset signal processing REQ1received, the implementation8. As a result of "YES" in step S2can only be displayed if the result is "YES" is obtained in step S1the result "YES" in step S2shows that the DCT coefficient is the DCT coefficient whose parity must be proinvestirovany.

In step S3the parity inverter 28 determines the sign of the DCT coefficient whose parity must be proinvestirovany. If the result at step S3is "YES", indicating that the sign of the DCT coefficient is positive, execution proceeds to step S4. Otherwise, the DCT coefficient is zero or negative, the execution proceeds to step S6.

In step S4the parity inverter 28 subtracts one from the DCT coefficient whose parity must be proinvestirovany (that is, adds -1), then execution proceeds to step S5where DCT coefficient with the inverted parity is supplied to the IDCT circuit 15 (Fig. 10A). Execution then returns to step S1, where it is processed next DCT coefficient.

Otherwise, in step S6the parity inverter 28 adds one to the DCT coefficient whose parity must be proinvestirovany, then execution proceeds to step S7where DCT CoE processed the next DCT coefficient.

Execution proceeds to step S8if the DCT coefficient is not the DCT coefficient whose parity is allowed to invert, or if the DCT coefficient whose parity is allowed to invert should not be inverted parity, that is, when the reset signal processing REQ1was not received. In step S8The DCT coefficient is supplied to the IDCT circuit 15 without change. Execution then returns to step S1, where it is processed next DCT coefficient.

In Fig. 15 shows a practical example of the structure of the third variant of the parity inverter 28, which invert the parity is to reduce the value of the DCT coefficient whose parity is inverted, that is, in order to make the DCT coefficient whose parity is inverted, closer to zero.

The parity inverter shown in Fig. 15, similar to the parity inverter 28, shown in Fig. 11. The elements in the circuit shown in Fig. 15, the corresponding elements in the circuit shown in Fig. 11, designated by the same numeric references and again not described here. The parity inverter shown in Fig. 15 differs from the parity inverter shown in Fig. 11 in that it includes a scheme of reduction of size (DCT coefft, received from the first memory 26 or the second memory 27 through the channel of any .rdata. If the sign of the DCT coefficient is positive, the scheme decrease subtracts one from the DCT coefficient, at the same time, if the polarity of the DCT coefficient is negative or it is equal to zero, add one to the DCT coefficient. Diagram of inverting the parity shown in Fig. 15, makes an odd amount of DCT coefficients in the block by selecting the DCT coefficient whose parity is inverted, from the scheme of reduction of size 80 and replacement DCT coefficient with a reduced size and proinvestirovanno parity DCT coefficient whose parity is to be reversed.

The scheme of reduction of size 80 consists of an evaluation scheme mark 81, which controls the fifth logic element "And" 84 directly, and the sixth logic element And 85 through an inverter 87. The scheme of reduction of size 80 also includes -1 myCitadel 82 and the +1 adder 83, which respectively subtract unit, or add one to each DCT coefficient obtained by any .rdata channel. In response to the output signal of the evaluation scheme mark 81, the fifth logic element And 84 or the sixth logic element "And" 85 selectable output -1 vicites 82 or the output of the +1 adder 83. Outputs a logical allicin to the fourth logical element "And" 65. If the parity of the sum of the DCT coefficients in the block you want to invert, the fourth logical element And selects the output with a reduced magnitude and inverted parity schemes reduce the value 80 for submission to the IDCT circuit 15 instead of the DCT coefficient whose parity is allowed to invert.

Assessment scheme mark 81 evaluates the sign of each DCT coefficient in the block of DCT coefficients received via any .rdata channel, and sets the state of its output to one or zero depending on whether the sign of the DCT coefficient is positive or negative. If the scheme of assessment of character sets that the sign of the DCT coefficient is positive, the output of the circuit evaluation mark opens the fifth logic element And 84 and closes the sixth logic element And 85. As a result, the output -1 vicites 82, that is, the DCT coefficient, from which is subtracted the unit served on the fourth logical element "And" 65 through fifth logic element And 84 and the logical element "OR" 86.

On the other hand, if the scheme of assessment mark 81 determines that the sign of the DCT coefficient is negative or zero, the output signal of the evaluation scheme mark closes the fifth logic element And 84 and opens the sixth gate "And" 85. In d the th logic element And 65 through sixth logic element And 85 and the logical element "OR" 86.

The fourth logical element "And" 65 delivers the DCT coefficient with the inverted parity and reduced the magnitude of schemes reduce the value 80 to the second logical element "And" 68 in response to the reset signal processing REQ1. If the comparator 62 determines that the DCT coefficient obtained by any .rdata channel is the DCT coefficient whose parity is allowed to invert DCT coefficient with a reduced size and an inverted sign is supplied from a scheme of reduction of size 80 to the IDCT circuit 15 (Fig. 10A), in the manner described above with reference to Fig. 11. On the other hand, if the third embodiment of the parity inverter shown in Fig. 15, did not receive the reset signal processing REQ1DCT coefficient whose parity is allowed to invert, is supplied to the IDCT circuit 15 without changes.

If the sum of the DCT coefficients should be done odd, the third variant of the parity inverter 28, shown in Fig. 15, submit to the IDCT circuit 15 DCT coefficient whose parity was proinvestirovany, by subtracting from it the unit, if its sign is positive, and submits to the IDCT circuit 15 DCT coefficient whose parity was proinvestirovany, by adding to it the unit, if its sign is negative or it is equal to zero. Such processing inverterate coefficients is odd.

Now will be described with reference to Fig. 16 and 17 of the fourth embodiment of the parity inverter 28.

If the fourth version of the parity inverter receives the reset signal processing REQ1he makes the sum of the DCT coefficients in the block is odd by replacing the DCT coefficient whose parity must be proinvestirovany, the DCT coefficient whose parity must be proinvestirovany and to which was added one if its sign is positive, and from which was deducted the unit, if the sign of the DCT coefficient is negative. This processing not only inverts the parity of the DCT coefficient whose parity must be proinvestirovany, but also increases the value of this DCT coefficient, that is, makes the DCT coefficient whose parity must be proinvestirovany farther away from zero. The processing used for the DCT coefficient whose parity must be proinvestirovany, is determined by the following equation:

if (res > 0)

res = res + 1

if (res < 0)

res = res - 1, (16)

where res is the DCT coefficient whose parity must be proinvestirovany.

The fourth variant of the parity inverter 28 may be provided with a computer or digital processor that operates according to the flowchart shown in figure 16. On facientem, whose parity is allowed to invert. For example, the inverter parity sets whether or not the DCT coefficient is the last non-zero DCT coefficient. If the result of step S1is "YES" and the DCT coefficient is the DCT coefficient whose parity is allowed to invert, execution proceeds to step S2. Otherwise, the DCT coefficient is not the DCT coefficient whose parity is allowed to invert, and execution proceeds to step S8.

In step S2the parity inverter 28 determines whether received or not the reset signal processing REQ1. If the result of step S2is "YES", indicating that the reset signal processing REQ1received, execution proceeds to step S3. Otherwise, i.e. if I have not received the reset signal processing, execution proceeds to step S8. As a result of "YES" in step S2can be obtained only if the "YES" is obtained in step S1the result of YES in step D2indicates that the DCT coefficient is the DCT coefficient whose parity must be proinvestirovany.

In step S3the parity inverter 28 determines the sign of the DCT coefficient. If the result of step S3is "YES", indicate th the rate is negative or it is equal to zero, and execution proceeds to step S6.

In step S4the parity inverter 28 adds one to the DCT coefficient, and then execution proceeds to step S5where DCT coefficient with proinvestirovanno parity is supplied to the IDCT circuit 15 (Fig. 10A). Execution then returns to step S1, where it is processed next DCT coefficient.

Otherwise, in step S6the parity inverter 28 subtracts one from the DCT coefficient (i.e., adds -1), then execution proceeds to step S7where DCT coefficient with proinvestirovanno parity is supplied to the IDCT circuit 15. Execution then returns to step S1, where it is processed next DCT coefficient.

Execution proceeds to step S8if the DCT coefficient is not the DCT coefficient whose parity is allowed to invert, or if the DCT coefficient whose parity is allowed to invert should not be subjected to inversion parity, that is, if you have not received the reset signal processing REQ1. In step S8The DCT coefficient is supplied to the IDCT circuit 15 without change. Execution then returns to step S1, where it is processed next DCT coefficient.

In Fig. 17 shows almost the Eisenia values of the DCT coefficient, whose parity is inverted, that is, in order DCT coefficient whose parity must be proinvestirovany, was farther from zero.

The parity inverter shown in Fig. 17, similar to the parity inverter 28, shown in Fig. 11. The elements in the circuit shown in Fig. 17, the corresponding elements in the circuit shown in Fig. 11, designated by the same numeric references and re are described here will not be. The parity inverter shown in Fig. 17 differs from the parity inverter shown in Fig. 11 in that it includes a scheme of increasing the value of 90 instead of the inverter 63 LSC.

The scheme of increasing the value 90 determines the sign of each DCT coefficient obtained from the first memory 26 or the second memory 27 through the channel of any .rdata. If the sign of the DCT coefficient is positive, the scheme of increasing the value adds one to the DCT coefficient, at the same time, if the sign of the DCT coefficient is negative or it is equal to zero, the circuit subtracts one from the DCT coefficient. Diagram of inverting the parity shown in Fig. 17, makes an odd amount of DCT coefficients in the block by selecting the DCT coefficients whose parity must be proinvestirovany, from increasing the value and replace the DCT coefficient with increased mn which engages the scheme of assessment value 91, which manages the fifth logic element And 94 directly and sixth logic element And 95 through an inverter 97. The scheme of increasing the value 90 also includes a +1 adder 92 and -1 myCitadel 93 which respectively add one and subtract one from each DCT coefficient. Either the output of the +1 adder 92, or exit -1 vicites 93 selects the fifth logic element And 94 or the sixth logic element "And" 95 in response to the output signal of the evaluation scheme mark 91. The outputs of logic elements And 94 and 95 are served on the logical element "OR" 96, which delivers the selected DCT coefficient increased value to the fourth logical element "And" 65. If you want to proinvestirovatj parity of the sum of the DCT coefficients in the block, the fourth logical element And selects the output signal with the inverted parity and increased value of the scheme increase the value of 90 for submission to the IDCT circuit 15 instead of the DCT coefficient whose parity is allowed to invert.

Assessment scheme mark 91 determines the sign of each DCT coefficient in the block of DCT coefficients received via any .rdata channel, and sets the state of its output to one or zero depending on whether the sign of the DCT coefficient is positive ozenki mark opens the fifth logic element And 94 and closes the sixth logic element And 95. As a result, the output +1 vicites 92, that is, the DCT coefficient, to which was added unit is supplied to the fourth logical element "And" 65 through fifth logic element And 94 and the logical element "OR" 96.

On the other hand, if the scheme of assessment mark 91 determines that the sign of the DCT coefficient is negative or it is zero, the output of the circuit evaluation mark closes the fifth logic element And 94 and opens the sixth gate And 95. As a result, the output -1 vicites 93, i.e., the DCT coefficient, from which was deducted the unit, is fed to the fourth logical element "And" 65 through sixth logic element And 95 and the logical element "OR" 96.

The fourth logical element "And" 65 delivers the DCT coefficient with the inverted parity and increased value from a pattern of increasing values of 90 to the second logical element 68 in response to the reset signal processing REQ1. If the comparator 62 determines that the DCT coefficient obtained by any .rdata channel is the DCT coefficient whose parity is allowed to invert DCT coefficient supplied from the circuit increasing the value to the IDCT circuit 15 (Fig. 10A) method, which was described above with reference to Fig. 11.

On the other hand, if the fourth option inost allowed to invert, is fed to the IDCT circuit 15, unchanged.

If the sum of the DCT coefficients should be done odd, the fourth variant of the parity inverter 28, shown in Fig. 17, delivers to the IDCT circuit 15 DCT coefficient whose parity was proinvestirovany by adding to it the unit, if its sign is positive, and delivers to the IDCT circuit 15 DCT coefficient whose parity was proinvestirovany by subtracting from it the unit, if its sign is negative or equal to zero. This treatment reverses the parity and increases the value of the DCT coefficient whose parity is inverted, and makes the sum of the DCT coefficients is odd.

Inverters parity 28, shown in Fig. 11, 13, 15 and 17, and their operation according to the block diagrams shown in Fig. 9, 12, 14 and 16 may be changed, in order to make the odd sum of DCT coefficients by modifying the parity DCT coefficient that is different from the last non-zero DCT coefficient read by zig-zag scanning. For example, in a two-dimensional 8 8 DCT transformation parity of one of the DCT coefficients of the DC components of DCT coefficient (7,7) component, i.e. the high-frequency component of the DCT coefficient (7,0) component in the top right corner or DCT mesothelioma, which is a high-frequency component has little effect on image quality, this component is especially suitable for the role of the coefficient whose parity may change.

In inverters parity shown in Fig.11, 13, 15 and 17 as the DCT coefficient whose parity is allowed to reverse, may be selected other DCT coefficients by replacing the address of the DCT coefficient address EOB-adrs supplied to the comparator 62. In another case, if the parity DCT coefficient of the high-frequency component needs to be changed, the counter reading 61 and the comparator 62 may be omitted, and to identify the DCT coefficient of the high-frequency component as the DCT coefficient whose parity may be changed, can be used to signal the memory is FULL.

In another embodiment, a scheme to bring the odd $ 14, shown in Fig. 6, 8 and 10, can determine the sum of the specified DCT coefficients, for example, DCT coefficients (0,0) component, (4,0) component, (0,4) component and the (4,4) element. Then the scheme of bringing to an odd amount may perform an operation of inverting the parity to make the sum of the specified DCT coefficients is odd. In Fig.18 shows a variant of the circuit of the cast to odd amounts which tests the parity. The elements in the circuit shown in Fig.18, the corresponding elements in the circuit shown in Fig.8, designated by the same numeric references and again not described here.

In the scheme of odd cast to the amount shown in Fig.18, the selector 51 interrupts the connection between the inverse quantizer 13 and the memory 23A. The selector 51 receives from the counter 29 the account coeff-adrs, which shows the number of DCT coefficients in the block received from the inverse quantizer 13.

In response to the result of counting coeff-adrs received from the counter 20, the selector 51 determines whether or not each DCT coefficient received from the inverse quantizer 13, one of the set of DCT coefficients, which therefore should be included in the amount determined by the memory 23A. For example, the selector determines whether the result of counting coeff-adrs, the value corresponding to the (0,0) component, (4,0) component, (0,4) component or (4,4) component. If the selector 51 determines that the DCT coefficient is one of the set of DCT coefficients, it delivers the DCT coefficient in the memory 23A. Accordingly, the odd cast to the amount shown in Fig. 18, determines the amount specified DCT coefficients in the block is to maintain. Scheme of bringing to an odd amount, shown in Fig.18, then takes the block of DCT coefficients with the adjusted parity in the IDCT circuit 15.

Variant shown in Fig. 18 may be modified by a method similar to that shown in Fig. 10A, to enable the scheme to determine the exclusive logical sum LSB set of DCT coefficients. The diagram in Fig.18 is modified by replacing the adder 23 LSB detector 29 and the logical element "OR" shown in Fig.10A.

Let us return now to Fig.6, where the DCT coefficients in the block of DCT coefficients is served from schemes odd cast to the amount 14 to the IDCT circuit 15 described above. The sum of the DCT coefficients received from the scheme to bring the odd sum is an odd number. If the sum of the DCT coefficients from the inverse quantizer was even, schemes odd cast to the sum of 14, changed the parity of at least one of the DCT coefficients in order to make the odd sum of DCT coefficients supplied to the IDCT circuit 15. The IDCT circuit 15 applies IDCT-processing to the DCT coefficients in the block to obtain a block of the restored difference S4. The restored block of the difference is supplied to the adder 16.

The adder 16 item by item performs addition of the block is the considerations applying 4. The resulting block of the restored frame S5served in the device memory image 4, where it forms the restored block of the frame, which is stored in one of memory devices, determined by the memory controller 3.

Encoder with variable word length 17 applies the encoding with variable-length words such as Huffman coding, etc. for each block discretized DCT coefficients SC of the encoder block differences 9 and the motion vector MV, the mode of the motion compensation MM, table data sample rate, etc. Encoder with variable word length also collects encoded with variable length data words together with the initial codes and header information of respective levels of MPEG for forming a compressed signal of the moving image.

Counter/layer macroblock 5 counts the signals the start of the layer S5and signals the beginning of the macroblock BS generated by the memory controller 3 synchronously with the beginning of each layer and each macroblock of frames read from the first memory device image 2 for processing. When the account reaches a preset value, the counter/layer macroblock 5 generates a start signal S0served on kodet multiplexed signal of the moving image to the output buffer 19, where it is temporarily stored. Then multiplexed signal of the moving image is read from the output buffer in the form of a stream of bits with a given bit rate. The compressed bit stream signal of a moving image is supplied to the expansion unit with the addition through the transmission channel or by recording a compressed bit stream signal of a moving image on a suitable recording medium such as an optical disk.

The recording medium is a carrier recorded a compressed signal of a moving image obtained from the signal of the moving image by encoding prediction and discrete cosine transform. Each block of each reconstructed frame is used as a reference picture when coding with prediction, restored by inverse sampling unit discretized DCT coefficients contained in a compressed signal of the moving image, the odd cast to the sum of the DCT coefficients in the resulting block of DCT coefficients and inverse orthogonal transform block of DCT coefficients is formed with an odd amount.

The transmission device according to the invention may include a device is performing an operation of forming an odd amount in the encoder block differences 9 of the sealing device. The operation of forming an odd amount would ensure that the sum of the DCT coefficients in each block discretized DCT coefficients included in the multiplexed signal of the moving image, would be odd. You would think that processing a compressed signal of the moving image in this way will eliminate the need to make the sum of the DCT coefficients is odd in the expansion unit. However, under this option, after the DCT coefficients are discretized in the sealing device and discretized inverse in the expansion unit, the sum of the DCT coefficients supplied to the IDCT circuit in the device extension, may not be an odd number. Therefore, the formation of odd sums should be done before IDCT-processing in the expansion unit to ensure the absence of mismatch errors.

Now with reference to Fig.19 will be described in the device extension of the compacted signal of the moving image, where used in this invention. In Fig.19 multiplexed signal of a moving image is taken in the form of a bit stream through a transmission channel from the sealing device, or obtained by reproducing a compressed signal of a moving image is de he is temporarily stored, and where it is read frame by frame in reverse video encoder with variable word length ("IVLC") 32. Inverse encoder with variable word length 32 retrieves the compressed signal of the moving image header information corresponding levels MPEG code, and retrieves the information of the header control information for decoding of the frame of the PH, which is supplied to the memory controller 33.

IVLC 32 applies the inverse of encoding with variable-length words for the blocks of DCT coefficients encoded with a variable length words, to obtain a block discretized DCT coefficients, including the current block, discretized DCT coefficients Cb. Block discretized DCT coefficients Cb is delivered to the decoder block differences 34. The decoder block differences 34 decodes the block discretized DCT coefficients Cb to obtain the restored block of the differences between BS and delivers the restored block of the differences in the adder 39.

IVLC 32 retrieves the compressed signal of the moving image, the motion vector MV and mode motion compensation MM for block discretized DCT coefficients Cb and submits them to the motion compensator 37. The motion compensator 37 causes the block mapping for the restored block from the to device memory image, each of which stores one already reconstructed frame. The block mapping BS is the block of the reconstructed frame is stored in one of the memory devices of the image at the address defined by the motion vector MV. The memory image in the memory unit 38, which stores the reconstructed frame, which is read by the block matching is determined by the memory controller 33.

As mentioned above, the frame may be encoded by prediction based on the previous reconstructed frame by predicting on the basis of subsequent restored frame by predicting on the basis of the block obtained by performing an element by element linear operation restored over the prior frame and the subsequent restored frame. In the end, the frame can be encoded without prediction. In this case, the block matching, which is provided by the memory block image 38 is zero block, i.e. the block in which the value of all elements set to zero. The block-matching motion compensation, provided by the memory block image 38, adaptive change, and for each block is selected optimal block spdy block mapping, provide a block of memory image 38, is supplied to the adder 39. The adder 39 performs an element by element addition of the restored block of the differences between the BS received from the decoder unit differences 34, and block mapping provided by the memory block image 38. The result of this addition is the restored block of the frame, which is stored in one of the memory devices in the memory block images 38 defined by the memory controller 33. The restored blocks of the frame formed by the adder 39 are stored one after another in the selected memory device, writing on top of the reconstructed frame previously stored in the device image, to form a new reconstructed frame.

Reconstructed frames stored in the memory unit of the image 38 is read in the order specified by signal indication output frame, which is provided by the memory controller 33. A few shots are served in the form of a reconstructed signal of a moving image on a suitable display device, such as a video monitor. The display device displays a moving image in accordance with the signal restored moving image.

Now the link is, Hemi odd cast to the sum of 35 and schemes inverse discrete cosine transform 36. The inverse quantizer 40 uses a table of sampling for inverse sampling unit discretized DCT coefficients Cb, obtained from the inverse of the encoder with variable word length 32. Scheme of bringing to an odd amount of 35 receives the output block of DCT coefficients from the inverse quantizer 40 and prevents errors, inconsistencies in the process IDCT-processed by the IDCT circuit 36. The IDCT circuit 36 applies IDCT-processing to the block of DCT coefficients is given to an odd value, the amount received from odd cast to the amount of 35.

In Fig. 20 shows an example of the structure of the inverse quantizer 40. The main parts of the inverse quantizer decoder 40 are range/level 41, the address counter 47, the transmitter address 48, the selector 49, the first memory unit 42, the second memory unit 43 and the scheme of the inverse of the sampling rate ("IQ-diagram") 46.

The decoder of number/level 41 receives the block discretized DCT coefficients Cb from the inverse of the encoder with variable word length 32. The decoder of number/level decodes the code number/level that was used to encode the discretized DCT the data of DCT coefficients is served in the first memory unit 42 or the second memory unit 43 in zigzag scan order. The first memory unit 42 and the second memory unit 43 stores each one unit discretized DCT coefficients.

The address counter 47 and the inverter address 48 respectively generate the address of the write and read address to the first memory unit 42 and the second memory unit 43. The discretized blocks of DCT coefficients are alternately written and read from the first memory block and the second memory block. Each block is discretized DCT coefficients is written in one memory block in a zigzag scan order in response to addresses provided by the address counter 47, and is read by the memory block in raster scan order in response to addresses provided by the Converter address 48. Different order of addresses when reading and writing changes the order discretized DCT coefficients in the block with a zigzag scanning order for the raster scanning order.

The address counter 47 generates the addresses of the entries in the zig-zag scanning order. The Converter address 48 receives addresses in the zig-zag scanning order from the address counter and uses the conversion table address to bring the addresses in the zigzag scanning order. the first memory unit 42 and the second memory unit 43 in the form of addresses adrs1and adrs2. If the unit is discretized DCT coefficients from row decoder/level 41 is written in the first memory unit 42 or the second memory unit 43 corresponding to the address adrs1and adrs2served by the address counter 47 through the selector 49 in zigzag scan order. If the unit is discretized DCT coefficients read from the first memory unit 42 or the second memory unit 43 in the inverse quantizer 46, the corresponding addresses adrs1and adrs2served Converter address 48 through the selector 49 in the raster scanning order.

If all sampled DCT coefficients in the block is recorded in the first memory unit 42 or the second memory unit 43, the block of DCT coefficients is read in raster scan order in the inverse quantizer ("IQ") 46. IQ 46 performs inverse quantization of discretized DCT coefficients in the block and delivers the resulting block of DCT coefficients in the scheme of bringing to an odd amount 35. The inverse quantization performed IQ 46 is the same as the inverse quantization performed by the inverse quantizer 13 in the local decoder device seals signal of the moving image shown in Fig.6.

If Shem inverse quantizer 40, even, it makes at least one DCT coefficient in the block, to make the sum of the DCT coefficients in the block is odd. Scheme of bringing to an odd amount of 35 sends a block of DCT coefficients with an amount of money given to an odd value, the IDCT circuit 36. A cast operation to an odd amount performed by the circuit of odd cast to the amount of 35, is the same as casting operation to an odd amount performed by the circuit of odd cast to the amount of 14 in the local decoder in the sealing device of the signal of the moving image shown in Fig.6.

The IDCT circuit 35 performs IDCT-processing block DCT coefficients with an amount of money given to an odd value, to obtain the restored block of the differences between the BS that is fed to the adder 39.

The inverse operation of discriminator 40, shown in figure 20, illustrates time charts shown in figures 21A through 21I. Inverse encoder with variable word length 32 retrieves the block discretized DCT coefficients Cb from a compressed signal of the moving image. Inverse encoder with variable word length generates the enable signal EV-EN shown in Fig. 21A, which instructs the decoder number/level 41 to read the block discretecontinuous system number/level.

IVLC 32 provides the signal number of events IVENT-NO decoder row/level 41, as shown in figure 21B. Signal number of events indicates the number of pairs number/level in the block discretized DCT coefficients Cb, that is, the number of pairs number of data - level".

If the decoder row/level 41 receives the signal number of events EVENT-NO, this causes the supply of the reset signal reading RE-REQ for each pair of number/level back to the inverse of the encoder with variable word length 32, as shown in Fig. 21C. Every time it receives a reset signal reading RE-REQ inverse encoder with variable word length 32 makes one a couple of number/level decoder number/level 41, as shown in the figures 21D and 21E. Thus, IVLC 32 supplies the row decoder/41 number of pairs number of/the level corresponding to the number of reset signals read that he received.

Decoder number/level 41 decodes the code number/level coded discretized DCT coefficients to deliver the block discretized DCT coefficients in a zigzag scan order in the form WDATA to the first memory unit 42, as shown in Fig. 21G. At the same time, as shown in Fig. 21F, ards1in the zig-zag scanning order, indicating the recording address of each of the sample DCT coefficient, through the selector 49 in the first memory unit 42.

If the decoder row/level 41 receives the EOB code from the IVLC 32, indicating that the last non-zero DCT coefficient decoder number of/the level sets sampled DCT coefficient corresponding to the EOB code, and all subsequent sampled DCT coefficients to zero and submits these zero DCT coefficients in the first memory unit 42.

If the decoder number/level receives the EOB code, it sends a signal EOB-EN registers position (POS REG) 44 and 45, as shown in Fig.21 H. the Signal EOB-EN indicates registers that received EOB code. Registers the position of the address counter 47 through the transducer address 48 also receive the address of each of the sample DCT coefficient supplied to the first and the second memory unit 42 and 43. If the encoder the number/level receives the EOB code, the address generated by the address counter 47 is the address of the last non-zero coefficient. The signal EOB-EN causes the write address EOB-POS last non-zero coefficient, which is converted to the address of the raster scan through preobrazhentsev. Thus, one of the POS registers 44 and 45 stores the address of the last non-zero coefficient of the block discretized DCT coefficients.

If the decoder number/level 41 was filed with the entire unit discretized DCT coefficients in the first memory unit 42 or the second memory unit 43, the address counter 47 sends a signal switching BANK to the first memory unit 42 and the second memory unit 43. Signal BANK switches the mode of the memory block, so that the first memory block that was previously in the write mode, switches to reading mode and the second memory block is switched to the recording mode. Thus, when the decoder number/level 41 decodes the next block discretized DCT coefficients, the resulting DCT coefficients will be written to the second memory unit 43. Signal BANK also switches the selector 49, so that the address supplied to the memory unit in the recording mode, are addresses in the zig-zag scanning order from the address counter 47, and the addresses supplied to the memory block in the reading mode, are addresses in raster scan order from the Converter address 48.

Also, if the decoder row/level 41 filed the entire block discretized DCT coefficients in the first memory unit 42, the Oia memory indicates that recorded all discretized coefficients in the block. If IQ receives the signal memory FULL1he sends a reset signal reading RD-EN in the first memory unit 42. The reset signal reading causes the first memory unit to read the stored sampled DCT coefficients in response to the address adrs1supplied in raster order scan Converter address 48 through the selector 49. Accordingly discretized DCT coefficients in the block are read from the first memory unit 42. DCT coefficients are read in accordance with each address supplied to the inverse quantizer 46.

At the same time, when discretized DCT coefficients in the block are read from the first memory unit 42, sampled DCT coefficients in the following block are recorded in the zig-zag scanning order in the second memory unit 43 according to the address from the address counter 47.

The inverse quantizer 46 performs inverse quantization of discretized DCT coefficients in the block discretized DCT coefficients by a method similar to that used by the inverse quantizer 13 in the sealing device of the signal of the moving image, described wiser CLASS="ptx2">

If the sum of the DCT coefficients in the block is even, the odd cast to the amount of 35 converts at least one of the DCT coefficients in the block to make odd the sum of the DCT coefficients in the block in the same way that is used in the circuit of the odd cast to the amount of 14 in the sealing device of the signal of the moving image as described above. The resulting block of DCT coefficients with the amount converted to an odd value, is supplied to the IDCT circuit 36.

For example, the odd cast to the amount of 35 can apply to POS registers 44 and 45 to determine whether or not the current DCT coefficient is the last non-zero coefficient in zigzag scan order, so that the scheme of bringing to an odd amount could change the parity of the last non-zero DCT coefficient to make the odd sum of DCT coefficients in the block. Alternatively, schemes odd cast to the amount of 35 can handle DCT coefficient of the high-frequency component to make the odd sum of DCT coefficients. Invert parity DCT coefficient of the high-frequency component may be preferred because of the high-frequency component does not influence the image quality is also true in the case, when the scanning order is different from the zigzag scanning order.

It should be clear that in order to avoid errors, inconsistencies operation cast to an odd amount performed in the sealing device of the signal of the moving image should be identical.

2. The second variant embodiment of the invention

The structure of the second variant of implementation of the sealing device signal of the moving image shown in Fig. 22. The second option is the preferred option of the invention. The structure of the schema bring to the odd $ 50 sealing device signal of the moving image shown in Fig. 22, shown in Fig. 23. The elements of the second variant of the device of the seal of the signal of the moving image corresponding to the elements in the first embodiment of the sealing device signal of the moving image shown in Fig. 6, designated by the same numeric references and again not described here. The second variant differs from the first variant of the device of the scheme to bring the odd $ 50. In the scheme of odd cast to the amount of 50, shown in detail in Fig. 23, the counter 20 counts the number of DCT coefficients received from the drive 23A consists of the adder 23 and the register 24. The adder 23 adds each DCT coefficient in the block of DCT coefficients received from the inverse quantizer 13, to the amount already received DCT coefficients in the block stored in the register 24. The register 24 is reset after it has been determined amount for each block of DCT coefficients. The resulting sum of the DCT coefficients supplied from the adder 23 and the register 24 and the scheme of assessment parity 21. Drive 23A requires only the sum of the least significant bit of the DCT coefficients in the block to obtain the suitable for estimation scheme definition to determine whether the checksum DCT coefficients is odd or even.

Assessment scheme parity 21 operates according to the value of the account coeff-adrs received from the counter 20 as follows. If the account indicates that the drive 23A summed all the DCT coefficients in the block diagram of the evaluation parity 21 determines whether the checksum DCT coefficients received from the drive 23A, odd or even. For example, in the case of two-dimensional 8 8 DCT transform, if the value of the account indicates that the determined amount of the 64 DCT coefficients in the block diagram of the evaluation parity 21 determines whether the sum of the DCT coefficients by ol, assessment scheme parity 21 estimates the least significant bit (LSB) of the sum of the DCT coefficients received from the memory 23A. Zero LSB indicates that the checksum is even. In this case, the scheme of assessment parity 21 sends a reset signal processing REQ1in the parity inverter 53 to force the parity inverter to perform an operation of inverting the parity. In response to the reset signal processing REQ1the parity inverter 53 changes the parity of at least one (i.e., an odd number) of the DCT coefficient in the block, to make the odd sum of DCT coefficients. On the other hand, a single LSB indicates that the checksum is odd. In this case, the scheme of assessment parity 53 does not issue a reset signal processing REQ1and the parity inverter 53 leaves the parity of all the DCT coefficients in the block without a change, because the checksum DCT coefficients already odd.

The block of DCT coefficients supplied from the inverse quantizer 13 is not only to drive 23A, but also to the parity inverter 53 through the delay circuit 52. The delay circuit 52 delays the DCT coefficients in the block of time corresponding to the processing times of the drive 23A and evaluation schemes parity 21, so that the last DCT coefficient, that is, vysokochetkoe 53 at the same time, as the reset signal processing REQ1.

Thus, the parity inverter 53 delivers all DCT coefficients, in addition to the high-frequency coefficient, the IDCT circuit 15 without change. If the scheme of assessment parity has not formed a reset signal processing REQ1the parity inverter 53 supplies and also the high-frequency DCT coefficient in the IDCT circuit without modification. Only if the scheme of assessment parity 21 has formed a reset signal processing REQ1the parity inverter 53 converts the LSB of the high-frequency DCT coefficient and supplies the high-frequency DCT coefficient with the inverted parity in the IDCT circuit 15.

Thus, if the scheme of assessment parity 21 indicates that the checksum DCT coefficients in the block is even, the parity inverter 53 processes the high-frequency DCT coefficient (for example, DCT coefficient (7,7) component in the 8 8) DCT transformation) in the block. The parity inverter converts the parity of high-frequency DCT component and, thus, makes an odd amount of DCT coefficients in the DCT block of coefficients, supplied to the IDCT circuit 15. Therefore, the checksum DCT coefficients in the block of DCT coefficients is always odd. DCT coefficient (7,7) component is a factor that is less than just what's odd cast to the amount of 50 preliminary version of the embodiment of the invention.

In Fig. 24 shows an example in which the LSB detector 29 and the logical element "Exclusive-OR (EXOR) 30 replace the adder 23 in Fig. 23. The elements in the circuit shown in Fig. 24, the corresponding elements in the circuit shown in Fig. 23 designated by the same numeric references and again not described here. LSB detector 29 determines the LSB of each DCT coefficient in the block, and the logical element "EXOR" 30 and the register 24 together define exclusionary logic LSB of DCT coefficients in the block. The parity of the exclusive logic circuit is determined by the scheme of assessment parity 21, as described above with reference to Fig. 23.

Alternatively, the logical element "And" 88 and the counter 89, shown in Fig. 10B, can be supplied instead of the logical element "Exclusive OR" and the register 24 shown in Fig. 24.

Another example is shown in Fig. 25. In it, the selector 51 is placed between the inverse quantizer 13 and the drive 23A in the scheme of odd cast to the amount shown in Fig. 23. The elements in the circuit shown in Fig. 25, the corresponding elements in the circuit shown in Fig. 23 designated by the same numeric references and again not described here. The diagram shown in Fig. 25, determines the amount of DCT coefficients only thadaniti, do I need to bring the sum to an odd value. The selector 51 receives the account coeff-adrs from the counter 20 to determine whether or not each DCT coefficient received from the inverse quantizer 13, one of the set of coefficients and therefore must be summed. If the selector determines that the DCT coefficient is one of the set of coefficients and must be summed, that is, the account coeff-adrs has a value corresponding to, for example, (0,0) component), (4,0) component, (0,4) component or (4,4) component, the selector 51 delivers DCT coefficient in the memory 23A. The selector 51 causes the scheme to bring an odd amount, shown in figure 25, to determine the sum of the given coefficients. Then the parity inverter 53 converts at least one of the specified CT coefficients, if necessary, to make an odd amount specified DCT coefficients. The block of DCT coefficients with the amount converted to an odd value, then served in the IDCT circuit 15.

In another embodiment, the selector 51, shown in Fig. 25, may be placed in the channel between the inverse quantizer 13 and LSB detector 29 in the diagram shown in figure 24. The diagram shown in Fig. 24, changed the torus. In another alternative scheme to bring the odd $ 50, if the last CT ratio, obtained from the inverse quantizer 13 is the coefficient of the DC component, that is, the order of raster scanning is reversed from the order in the embodiments described above, the DCT coefficient applied to the operation of inverting the parity is not high frequency DCT component, and is the DCT coefficient of the DC component.

Now with reference to Fig. 26 will be described an example of a schematic device parity inverter 53. The parity inverter 53 is a simplified version of the above inverter 28, shown in Fig. 11. The parity inverter 53 includes: LSB-inverter 63, the third and fourth logic elements "And" 64 and 65, the logical element "OR" 66 and inverter 71.

The parity inverter 53 LSB inverter 63 inverts the LSB of each DCT coefficient in the block of DCT coefficients received from the inverse quantizer 13. Thus, the inverted parity of each DCT coefficient. Typically, the reset signal processing REQ1no, so the parity inverter feeds each of the received DCT coefficient to the IDCT circuit 15 (figure 23) through the third logical element "And" 64 and the logical element "ILike, the bill value coeff-adrs from the counter 20 indicates the scheme of assessment parity 21 that the value obtained by the circuit evaluation parity, is the sum of all the DCT coefficients in the block. In response to this assessment scheme parity determines whether the checksum DCT coefficients is odd or even.

If the scheme of assessment parity 21 determines that the checksum DCT coefficients in the block is even, it sends a reset signal processing REQ1in the parity inverter 53. The reset signal processing enters the parity inverter 53 through delay element 52 at the same time, and when the high-frequency DCT coefficient. The reset signal processing REQ1changes the state of the third and fourth logic elements "And" 64 and 65. In the high-frequency DCT coefficient with inverted LSB is supplied from the inverter 63 LSB to the IDCT circuit 15 through the fourth logical element "And" 65 and the logical element "OR" 69. High-frequency DCT coefficient with inverted LSB is supplied to the IDCT circuit instead of the normal high-frequency DCT coefficient to make an odd amount DCT coefficients are supplied to the IDCT circuit.

On the other hand, if the scheme of assessment parity 21 determines that the checksum DCT coefficients in the block inefficient to the IDCT circuit 15 through the logical element "And" 64 and the logical element "OR" 69, because it does not require bringing the amount of block DCT coefficients to an odd value.

Options a practical example of the parity inverter 53, shown in figure 26, shown in Fig. 27 - 29.

In Fig. 27 shows the +1 adder 73, similar to the +1 adder shown in Fig. 13, which replaces the inverter 63 LSB in the parity inverter shown in Fig. 26. In the rest of the circuit remains unchanged. The modified parity inverter shown in Fig. 27 inverts the parity of each DCT coefficient in the block by adding to it the unit. Thus, if the scheme of assessment parity 21 sends a reset signal processing REQ1the inverter parity, the parity inverter shall submit to the IDCT circuit 15 high-frequency DCT coefficient appended with a unit instead of the normal high-frequency DCT coefficient. This replacement makes an odd amount of DCT coefficients in the block.

It is shown in Fig. 28 scheme of reduction of size 80, used in Fig. 15 may be replaced by an inverter 63 LSB in the diagram shown in figure 26. The diagram shown in Fig. 26, but otherwise remains unchanged. The parity inverter shown in Fig. 26 and modified, as shown in Fig. 28, makes an odd amount DCT coefficients>the sum of the DCT coefficients in the block is odd by feeding high-frequency DCT coefficient with the inverted parity in the IDCT circuit 15. Parity high-frequency DCT coefficient is inverted in one of two ways: from the high-frequency DCT coefficient using -1 vicites 62 subtracts one if the high-frequency DCT coefficient is positive, or high-frequency DCT coefficient using the +1 adder 83 adds the unit, if the high-frequency DCT coefficient is zero or negative.

It is shown in Fig. 29 scheme of increasing the value 90 in figure 17 may be replaced by inverter 63 LSB in the diagram shown in figure 26. The diagram shown in figure 26, the rest remains unchanged. The parity inverter, shown in figure 26 and modified, as shown in figure 29, makes an odd amount of DCT coefficients according to equation (16) described above. If the scheme of assessment parity 21 generates the reset signal processing REQ1the sum of the DCT coefficients in the block is odd by feeding high-frequency DCT coefficient with proinvestirovanno parity in the IDCT circuit 15. Parity high-frequency DCT coefficient is inverted in one of two ways: from the high-frequency DCT irately, or to high-frequency DCT coefficient using the +1 adder 92 adds the unit, if the high-frequency DCT coefficient is positive.

Now will be described the second embodiment of the device of the expansion of the compacted signal of the moving image.

In the second variant of the device of the expansion of the compacted signal of the moving image diagram of the odd cast to the amount of 50 replaces the scheme of bringing to an odd amount of 35 in the first embodiment of the decoder of the compacted signal of the moving image described above with reference to Fig. 19. In the rest of the diagram shown in Fig. 19 remains unchanged. In the second variant of the device of the expansion of the compacted signal of the moving image processing with the aim of bringing the sum of the DCT coefficients to an odd value performed in the same manner as the processing that is performed by the scheme to bring the odd amount in the second embodiment of the sealing device signal of the moving image, shown and described above with reference to Fig. 22. Thus, in the second variant of the device of the expansion of the compacted signal of the moving image is not required to file address EOB-adrs from the inverse of the encoder variable is implement the method of the inverse discrete cosine transform and the back of the device cosine transform, the sealing device signal of the moving image, the device extension of the compacted signal of a moving image and a compressed signal of the moving image, in which the probability of occurrence of a conversion error is so small that mismatch errors almost never appear. In addition, the invention enables to obtain a recording medium, which does not appear mismatch errors when the multiplexed signal of the moving image is reproduced from the media and enhanced through processing including inverse orthogonal transformation.

If the seal signal of a moving image using a discrete cosine transformation and expansion of a compressed signal of a moving image using the inverse discrete cosine transformation, the invention enables to prevent occurrence of errors, inconsistencies inverse discrete cosine transform. This prevents deterioration of image quality. Accordingly, in the sealing device of the signal of the moving image in the device extension of the compacted signal of the moving image, which use Adri, restored by the expansion unit will differ from each other. Thus, it is possible to provide a high quality image.

Although shown to illustrate variants of the invention have been described herein in detail, it should be clear that the invention is not limited to the described variants identified here and what can be done various modifications within the subject of the invention defined by the attached claims.

The following is the transcript of the inscriptions on the accompanying drawings.

Inscriptions in the accompanying drawings:

Fig. 1:

101 - formatting unit 102 is a predictor of movement, 103 - calculation unit differences, 104 orthogonal transformation, 105 - sampling, 106 coding with variable word length, 107 - output buffer 108 - inverse quantizer 109 - inverse orthogonal transform, 110 - adder 111 - selector 112A - memory image A, 112B - memory image B, 112C - memory image C, 112D - memory image D, 113 - predictor, 114 - generating read address, 115 - determine the mode of prediction.

Fig. 2:

121 - input buffer 122 - inverted encoder with variable word length, 123 inverse the display, 128 - memory image, 129 - predictor, 130 - generating read addresses, 131 - generation clock.

Fig. 3:

2, the first memory device frame, 3 - memory controller 4 to the second memory device frame, 5 - count, 6 - prediction motion, 7 - motion compensation, 8 - diagram of the formation of differences, 9 - coder block differences, 10 - local decoder 11 - the discrete cosine transform, 12 - discretization, 13 - inverse sampling, 14 - diagram reduction to an odd amount, 15 - inverse discrete cosine transformation, 16 - adder 17 - encoder with variable word length, 18 - bit counter, 19 - the output buffer. The input element 2 - "input moving image; the output element 19 - bit stream (multiplexed signal of the moving image)"; MM - mode motion compensation; MV is the motion vector.

Fig. 8:

13 - inverse sampling, 15 inverse discrete cosine transformation, 20 - count, 21 - evaluation of parity, the 22 - selector memory 23 to the adder 24 - case 25 case 26 - memory #1, 27 - memory #2, 28 - inverter parity.

Fig. 9:

S1the coefficient should be set to an odd value?, S3- invert LSB, S4 / o S5 - output of the DCT coefficients is ATI, 24 - case 25 case 26 - memory #1, 27 - memory #2, 28 - inverter parity, 29 - allocation LSB, 89 - counter LSB. At the exit 89 - "reset" output - "the accounts".

Fig. 11:

61 - meter reading, 62 - comparison, 63 - inverting LSC.

Fig. 12:

S1the coefficient should be set to an odd value?, S3- add +1 to the DCT coefficient, S4o, S5the output of the DCT coefficient.

Fig. 13:

61 - meter reading, 62 - comparison, 63 - adder +1.

Fig. 14:

S1the coefficient should be set to an odd value?, S3- coefficient, which should be brought to an odd value, positive?, S4- add -1 to the DCT coefficient, S5o, S6- add +1 to the DCT coefficient, S7o, S8the output of the DCT coefficient.

Fig. 15:

61 - meter reading, 62 - comparison, 81 - evaluation of parity, 82 - -1 myCitadel, 83 - +1 adder.

Fig. 16:

S1the coefficient should be set to an odd value?, S3- coefficient, which should be brought to an odd value, positive?, S4- add -1 to the DCT coefficient, S5o, S6- add -1 to the DCT coefficient is e, 91 - evaluation of parity, 93 - -1 myCitadel, 92 - +1 adder.

Fig. 18:

13 - inverse sampling, 20 - count, 21 - evaluation of parity, the 22 - selector memory, 24 - case 25 case 26 - memory #1, 27 - memory #2, 28 - inverter parity, 51 - selector.

Fig. 19:

31 - the input buffer (input: stream of bits (multiplexed signal of the moving image)"), 32 - invert coding with variable word length, 33 - memory management (input: "header frame"), 35 - scheme of bringing to an odd amount, 36 - inverse discrete cosine transformation, a 37 - the motion compensator (input: MM - mode, motion compensation, MV is the motion vector), 38 - device memory image (output: "show frame").

Fig. 20:

32 - invert coding with variable word length, 35 - odd cast to the amount of 36 inverse discrete cosine transformation, 41 - decoder number/level 42 - memory #1, 43 - memory #2, 44 and 45 registers the position of the # # 1, 2, 47 - address counter, 48 - Converter addresses, 49 - selector.

Fig. 22:

2, the first memory device frame, 3 - memory controller 4 to the second memory device frame, 5 - count, 6 - prediction motion, 7 - motion compensation, 8 - diagram of the formation of differences, 9 - encoder the discretization, 14 - diagram reduction to an odd amount, 15 - inverse discrete cosine transformation, 16 - adder 17 - encoder with variable word length, 18 - bit counter, 19 - output buffer. The output element 2 - "input moving image; the output element 19 - bit stream (multiplexed signal of the moving image)"; MM - mode motion compensation; MV is the motion vector, 50 - scheme of bringing to an odd amount.

Fig.23:

13 - inverse sampling, 20 - count, 21 - evaluation of parity, 24 - register, 53 - inverter parity.

Fig.24:

13 - inverse sampling, 20 - count, 21 - evaluation of parity, 24 - register, 29 - allocation LSB, 53 - inverter parity.

Fig. 25:

13 - inverse sampling, 20 - count, 21 - evaluation of parity, 24 - register, 51 - selector 53 - inverter parity.

Fig. 26 and 27:

63 - inverting LSB. At the entrance: "the detainee DCT coefficient". At the output 69: "IDCT". 73 - +1 adder

Fig. 28 and 29:

61 - evaluation of the mark 82 - -1 myCitadel, 83 - +1 adder 91 - evaluation of parity, 92 - +1 adder 93 - -1 myCitadel.

Fig. 30:

31 - the input buffer (input: "multiplexed signal of the moving image"), 32 - invert coding with variable word length, 33 - memory management (at the entrance: the R motion (input: MM - mode motion compensation, MV is the motion vector), 38 - device memory image (output: output signal of the moving image"), 40 - inverse sampling, 50 - scheme of bringing to an odd amount.

1. The method of processing the set of transform coefficients, each of which has parity, providing sensitive to errors, the set of conversion factors for processing by the inverse orthogonal transformation, and is not sensitive to errors, the set of conversion factors is not subject to rounding errors when its inverse orthogonal transformation, the method includes the following steps: summary of conversion factors to obtain the amount having parity, evaluating the parity of the sum, characterized in that it includes inverting the parity of one of the transform coefficients, if the checksum is even, while the conversion factor with the inverted parity makes the checksum is odd, and obtaining transform coefficients, including the conversion factor from proinvestirovanno parity, in the form of a set that is not sensitive to errors.

2. The method according to p. 1, characterized in that the coefficients PREOBRAZOVANIYa includes the conversion factor representing the DC component, the step of inverting the parity of one of the conversion factors invert the parity of one of the conversion factors, non-conversion coefficient representing the DC component.

3. The method according to p. 2, wherein the set of transform coefficients includes a conversion factor representing the high frequency component, the step of inverting the parity of one of the conversion factors invert parity conversion factor representing the high frequency component.

4. The method according to p. 3, wherein each conversion coefficient in the set represented by a binary number with the lowest discharge step of inverting the parity of one of the conversion factors invert the least significant bit of one of the conversion factors.

5. The method according to p. 2, wherein each conversion coefficient in the set has a sign, and the step of inverting the parity of one of the transform coefficients includes the following steps: determination of the sign of one of the conversion factors, the addition of set is about an odd number of one of the transform coefficients, if the sign is positive.

6. The method according to p. 2, characterized in that it includes a step of obtaining transform coefficients in the set in sequential order, and conversion factors include the conversion of the last, and the step of inverting the parity of one of the conversion factors invert parity conversion factor, obtained last.

7. The method according to p. 1, characterized in that all the transform coefficients in the set have values other than zero.

8. The method according to p. 1, wherein each conversion coefficient in the set represented by a binary number with the lowest discharge step of summing the conversion factors add to the amount only the least significant bit of each conversion.

9. The method according to p. 1, characterized in that it contains a step of selection of the transform coefficients in the set of unit conversion factors.

10. Device for pre-processing the set of transform coefficients, each of which has parity, providing a fixed errors a set of conversion factors for processing through is not subject to rounding errors when running over him inverse orthogonal transformation, including the drive receiving each of the transform coefficients in the set and provide the amount with parity, the assessment tool parity, receiving the sum from the drive, to evaluate the parity of the sum, characterized in that it contains a means of inverting the parity functioning when the assessment tool parity sets that checksum is even, for inverting the parity of one of the transform coefficients, to obtain the conversion factor from proinvestirovanno parity, and the conversion factor from proinvestirovanno parity makes the checksum is odd, and the means to obtain transform coefficients, including the coefficient conversion proinvestirovanno parity, in the form set not error-prone.

11. The device according to p. 10, characterized in that a device for processing a set of transformation coefficients generated by the two-dimensional discrete cosine transform, a set of transform coefficients includes the conversion coefficient representing the DC component, and means for inverting the parity is a tool for inverterbased DC component.

12. The device according to p. 11, wherein the set of transform coefficients also includes a conversion factor representing the high frequency component, and means for inverting the parity is a means for inverting the parity conversion factor representing the high frequency component.

13. The device according to p. 12, wherein each conversion coefficient in the set represented by a binary number with the lowest discharge and the means of inverting the parity includes means for inverting the LSB of one of the conversion factors.

14. The device according to p. 10, wherein each conversion coefficient in the set represented by a binary number with the lowest discharge and the drive includes a means for summing only the LSB of each conversion.

15. The device according to p. 10, characterized in that it includes means for selecting transform coefficients in the set of unit conversion factors.

16. The method of the inverse orthogonal transform of the set of transform coefficients without rounding errors, moreover, the th following steps: assessment of the LSB of each conversion factor, calculation of conversion factors with a single low-order to get the account, the assessment of the accounts on parity, characterized in that it includes a change to one of the transform coefficients, if the account is an even number, to obtain the modified conversion, and the modified conversion factor makes the account is an odd number, and inverse orthogonal transformation of the set of conversion factors, including the revised conversion factor.

17. A device for inverse orthogonal transform of the set of transform coefficients without rounding errors, and each of the transform coefficients has a parity containing means for summing the conversion factors used to obtain the amount having parity, the assessment tool parity sum, characterized in that it contains a means of bringing the values sum to odd functioning when the assessment tool parity sets that checksum - even, for inverting the parity of one of the transform coefficients to obtain the conversion factor from proinvestirovanno parity, thanaleng conversion, receiving a set of transform coefficients, including the coefficient conversion proinvestirovanno parity, from the circuit to bring the values sum to odd.

18. The device under item 17, characterized in that the means of bringing the values sum to odd made with the possibility of adding one to one of the transform coefficients, if the assessment tool parity sets that checksum is even.

19. The device under item 17, characterized in that it each conversion coefficient has a sign, a means of bringing the values sum to odd includes means for determining the sign to determine the sign of each coefficient conversion tool, used respectively for adding units to the conversion factor, if the means for determining the sign determines the sign of the conversion coefficient is positive, and subtracting units of the conversion factor, if the means for determining the sign determines the sign of the conversion coefficient is negative.

20. The device under item 17, characterized in that each conversion coefficient in the set represented by a binary number with the lowest discharge assessment tool h is the cue element "Exclusive OR", having a first input receiving the least significant bit of each coefficient of conversion from the means of determining the LSB, the second input and output register having an input connected to the output of the logical element "Exclusive OR", the output connected to the second input of the logic gate Exclusive-OR circuit evaluation parity connected to the output of the register.

21. A device for inverse orthogonal transform of the set of transform coefficients without rounding errors, and each of the transform coefficients represented by a binary number, comprising the least significant bit having a state that contains a means of assessing the state of the LSB of each conversion, the tool accounts for the calculation of the conversion factors, the least significant bit of which is estimated by the assessment tool the Junior level and which should be in a single state, the assessment tool of the account to ensure that the accounts received from the account balance is an even number, characterized in that that contains a means of bringing the account to an odd value, working, when cf is th of transform coefficients, to get an updated conversion factor, which makes the result of counting odd number, and circuit inverse orthogonal transformation that takes a set of conversion factors, including the revised conversion factor from funds to bring the account to an odd value.

22. Device for sealing a signal of a moving image consisting of frames, and each frame is divided into blocks containing a means for predictive coding blocks signal of a moving image by matching blocks of the reference frame for forming blocks of differences, a means of encoding block differences for sealing units of the differences coming from the predictive encoding to generate a compressed signal of the moving image, and a means of encoding a block of differences includes means of an orthogonal transform block of the differences coming from the means for predictive coding to retrieve the blocks of transform coefficients, means for sampling the blocks of transform coefficients supplied from the orthogonal transformation, for obtaining a compressed signal, of which formiruete signals, coming from means coding block differences, to obtain recovery of blocks of differences without rounding errors, when the blocks are compressed signal subjected to the inverse orthogonal transformation, and a local decoding includes means inverse sampling compacted blocks of a signal from means coding block differences, to retrieve the blocks of the restored transform coefficients, each of the restored transform coefficients has parity, means for summing the restored transform coefficients in each block of transform coefficients supplied from the inverse quantization to obtain the amount with parity, the assessment tool parity sum, characterized in that that contains a means of bringing the sum to an odd value, operating when the assessment tool parity sets that checksum is even, for inverting the parity of one of the restored transform coefficients in the block, to obtain a conversion factor with proinvestirovanno parity, and the conversion factor from proinvestirovanno parity makes SW conversion, including the conversion factor from proinvestirovanno parity, from the means of bringing the sum to an odd value, and the circuit inverse orthogonal transformation provides the restored blocks of differences, a tool for predictive decoding the restored blocks of the differences coming from the local decoding to restore staffing blocks corresponding to the blocks of the signal of the moving image, and an image memory that stores the recovered HR blocks coming from funds predictive decoding, in the form of blocks of restored frame for use as a reference frame for predictive coding of other frames of the signal of the moving image.

23. The device according to p. 22, characterized in that is used for recording a compressed signal of the moving image on the recording medium and provides the means for application coding with variable length words to blocks compressed signal for forming a compressed signal of the moving image, the means for forming a recording signal from the compressed signal of a moving image and a means for recording the recording signal on the recording media.

24. Ustroystvo.ranee and contains means for applying coding with variable length words to blocks compressed signal for forming a compressed signal of the moving image, the means for forming a signal transmission from a compressed signal of a moving image and a means for transmitting the transmission signal through the transmission channel.

25. The device according to p. 22, wherein the image memory is the second memory image includes a first image memory, the first memory temporarily stores the image signal of the moving image, a means for predictive coding predictive coding blocks signal of the moving image read from the first memory image, a means of encoding with variable-length words for the formation of a compressed signal of the moving image through the use of encoding with variable-length words to blocks compressed signal from means coding block differences, and means motion compensation for motion detection between the restored frames stored in the second memory image, and the signal of the moving image stored in the first memory image to apply motion compensation to the already restored frames stored in the second memory image, in response to the detected movement to form blocks of one of vosstanovlenie the encoding.

26. The device according to p. 25, characterized in that is used for recording a compressed signal of the moving image on the recording medium and provides the means for forming a recording signal from the compressed signal of a moving image and a means for recording the recording signal on the recording media.

27. The device according to p. 25, characterized in that is used for transmitting a compressed signal of the moving image through a transmission channel and includes means for forming a signal transmission from a compressed signal of a moving image and a means for transmitting the transmission signal through the transmission channel.

28. Device for sealing a signal of a moving image consisting of frames, and each frame is divided into blocks containing a means for predictive coding of blocks of signals of the moving image by matching blocks of the reference frame for forming blocks of differences, a means of encoding block differences for sealing units of the differences coming from the predictive encoding to generate a compressed signal of the moving image, and a means of encoding a block of differences includes the means of the orthogonal transform blocks of the differences, PTO sampling blocks of transform coefficients, coming from a means of orthogonal transformations for obtaining a compressed signal, which is generated multiplexed signal of a moving image, a local decoding for expansion of the compacted blocks signals from means coding block differences, to obtain the restored blocks of differences without rounding errors, when the blocks are compressed signal subjected to the inverse orthogonal transformation, and a local decoding includes means for inverse sampling compacted blocks of a signal from means coding block differences, to retrieve the blocks of the restored transform coefficients, each of the restored transform coefficients represented by a binary number, comprising the least significant bit, a means of assessing the state of the LSB of each of the restored transform coefficients, means the account to ensure the counting of the restored transform coefficients having the single least significant bit in the block, the assessment tool of the account to establish what the result means the account is an even number is as the assessment tool of the account sets, the result is an even number, to change one of the restored transform coefficients in the block to obtain a modified conversion factor, which makes the result of counting odd number, and circuit inverse orthogonal transformation, receiving each block of recovered transform coefficients, including the revised conversion factor from funds to bring the account to an odd value, and the circuit inverse orthogonal transformation provides the restored blocks of differences, a tool for predictive decoding the restored blocks of the differences coming from the local decoding for the personnel recovery unit corresponding to the blocks of the signal of the moving image, and an image memory that stores the recovered HR blocks, coming from funds predictive decoding in blocks restored frame for use as a reference frame for predictive coding of other frames of the signal of the moving image.

29. The device according to p. 28, characterized in that is used for recording a compressed signal of the moving image on the recording medium and Mirovaya aggregated signal of the moving image, the means for forming a recording signal from the compressed signal of the moving image and the means for recording the recording signal on the recording media.

30. The device according to p. 28, characterized in that is used for transmitting a compressed signal of the moving image through a transmission channel and provides a means for the application of encoding with variable-length words to blocks compressed signal for forming a compressed signal of the moving image, means for forming a signal transmission from a compressed signal of a moving image and a means for transmitting the transmission signal through the transmission channel.

31. The device according to p. 28, wherein the image memory is the second memory image includes a first image memory, the first memory temporarily stores the image signal of the moving image, a means for predictive coding predictive coding blocks signal of the moving image read from the first memory image, a means of encoding with variable-length words for the formation of a compressed signal of the moving image through the use of encoding with variable-length words to blocks of compacted base is tion between the restored frames, stored in the second memory image, and the signal of the moving image stored in the first memory image to apply motion compensation to the already restored frames stored in the second memory image, in response to the detected movement to form one block from the restored frames selected as the reference frame, and to supply blocks of the reference frame by means of predictive coding.

32. The device according to p. 31, characterized in that is used for recording a compressed signal of the moving image on the recording medium and provides the means for forming a recording signal from the compressed signal of a moving image and a means for recording the recording signal on the recording media.

33. The device according to p. 31, characterized in that is used for transmitting a compressed signal of the moving image through a transmission channel and includes means for forming a signal transmission from a compressed signal of a moving image and a means for transmitting the transmission signal through the transmission channel.

34. Device for expanding a compressed signal of the moving image to provide an output signal of the moving image, and orignal moving image, where part of the signal contain blocks of a compressed signal, encoded with variable length words containing the means of the inverse of encoding with variable-length words for the application of inverse coding with variable length words to blocks compressed signal encoded with variable length words, for obtaining a compressed signal, decoding means for expanding the compacted blocks of a signal from the inverse of encoding with variable-length words, to obtain the restored blocks of differences without errors fillets, when the blocks are compressed signal subjected to the inverse orthogonal transformation, and the decoding means includes means inverse sampling each block in the compressed signal, coming from means coding block differences, to obtain a block of reconstructed transform coefficients, each of which has parity, means for summing the restored transform coefficients in the block of transform coefficients supplied from the inverse quantization to obtain the amount with parity, the assessment tool parity sum, characterized in that it contains among whom, that checksum is even, for inverting the parity of one of the restored transform coefficients in the block to get the conversion factor from proinvestirovanno parity, and the conversion factor from proinvestirovanno parity makes the sum is odd, and the chain inverse orthogonal transformation, the receiving block of the restored transform coefficients, including the coefficient conversion proinvestirovanno parity, from the circuit to bring the values sum to odd, when this circuit is the inverse orthogonal transformation provides the restored blocks of differences.

35. The device according to p. 34, characterized in that the means of decoding variable length words, in addition, provides the motion vectors and mode information to the motion compensation and includes a tool for predictive decoding for predictive decoding the restored blocks of the differences coming from the decoding means, to restore the blocks of the frame image memory that stores the reconstructed HR blocks coming from funds predictive decoding, in the form of blocks of restored frame for use as a reference frame according to the motion vector and the data mode, motion compensation, coming from the inverse of encoding with variable-length words, to perform motion compensation for the already restored frames stored in the memory image to form from one of the already restored frames selected as a reference block of the reference frame and submit the block of the reference frame in the tool predictive decoding, and means for reading the output signal of the moving image from the memory image.

36. Device for expanding a compressed signal of the moving image to provide an output signal of the moving image, and the multiplexed signal of the moving image consists of parts, each of which represents the output signal frame of the moving image, where part of the signal contain blocks of a compressed signal, encoded with variable length words containing the means of the inverse of encoding with variable-length words for the application of inverse coding with variable length words to blocks compressed signal encoded with variable length words, for obtaining a compressed signal, decoding means for expanding the compacted blocks of a signal from the means and the rounding errors, when the blocks are compressed signal subjected to the inverse orthogonal transformation, and the local decoding means includes means inverse sampling for inverse sampling each block in the compressed signal from means coding block differences, to obtain a block of reconstructed transform coefficients, each of which is represented by a binary number, including the least significant bit having a certain status, a means of assessing the state of the LSB of each of the restored transform coefficients, means account for the calculation of the transform coefficients in the block, the least significant bit of which is estimated by the assessment tool the Junior level, on the subject of his single status, the assessment tool of the account to ensure that the accounts received from the account balance is an even number, characterized in that it contains a means of bringing the values sum to odd functioning when the assessment tool parity States that the account is an even number, to change one of the restored transform coefficients to obtain the modified coefficient convert analnogo conversion, the receiving block of the restored transform coefficients, including the revised conversion factor coming from the means of bringing the values sum to odd, when this circuit is the inverse orthogonal transformation provides the restored blocks of differences.

37. The device according to p. 36, characterized in that the means of decoding variable length words made with the possibility of generating motion vector data mode, motion compensation, provides a tool for predictive decoding for predictive decoding the restored blocks of the differences coming from the decoding means, for recovery of personnel units, image memory that stores the recovered HR blocks coming from funds predictive decoding, in the form of blocks of restored frame for use as a reference frame for predictive decoding of other frames of the signal of the moving image, means functioning according to the motion vector and the data mode, motion compensation, coming from the inverse of encoding with variable-length words, to perform motion compensation for the already restored frames stored is wow, block of the reference frame and the feed block of the reference frame to the tool predictive decoding means for reading the output signal of the moving image from the memory image.

38. The method of multiplexing signal of the moving image to provide a compressed signal of a moving image, comprising the following steps: application of predictive coding and orthogonal transform to blocks of the signal of the moving image, to obtain blocks of transform coefficients, which is formed multiplexed signal of the moving image, characterized in that it includes conversion to an odd value of the sums of the blocks of transform coefficients before applying inverse orthogonal transform and predictive decoding the blocks of transform coefficients to obtain blocks of restored frame for use as a reference frame predictive coding of other frames of the signal of the moving image.

39. The method according to p. 38, characterized in that the step of bringing to an odd value of the sums of the blocks of transform coefficients includes the following steps: the sum of the transform coefficients in each block for recip, the formation that the checksum is even, and if it is determined that the checksum is even, inverting the parity of one of the transform coefficients in the block to make the odd checksum.

40. The method according to p. 38, wherein each conversion coefficient represented by a binary number, including the least significant bit, the step of bringing to the odd value of the sum of the blocks of transform coefficients includes the following steps: assessment of the LSB of each of the transform coefficients, the calculation of the transform coefficients in the block, with the single least significant bit, to get the account and if the account is an even number, the change per unit of one of the transform coefficients in the block.

41. The method according to one of paragraphs.38 to 40, characterized in that is used for recording a compressed signal of the moving image on the recording medium, and includes the following steps: providing a recording media, the formation of the recording signal from the compressed signal of a moving image and recording the recording signal on the recording media.

42. The method according to one of paragraphs.38 to 40, characterized in that is used to transfer compressed signal is armirovanie signal transmission of the compressed signal of the moving image, and transmitting the transmission signal in the transmission channel.

43. The method of multiplexing signal of the moving image, to obtain a multiplexed signal of a moving image, comprising the following steps: detection of movement between the blocks of the frame signal of the moving image and the blocks of a reconstructed signal of a moving image serving as reference frame, applying motion compensation to the reference frame in response to a detected movement for the formation of blocks matching the reference frame, the use of block matching of the reference frame for the application of predictive coding block signal of the moving image, to obtain a block of differences, orthogonal transformation blocks of the differences to obtain a block of transform coefficients, forming a compressed signal from the blocks of transform coefficients by applying the sampling and coding with variable word length, characterized in that it comprises, before performing the inverse orthogonal transform to the blocks of transform coefficients to obtain blocks of restored differences bring to an odd value, the checksum of each block of transform coefficients, in order to prevent rounding errors when reverse Orologeria blocks restored frame for use as a reference frame when using predictive coding to other frames of the signal of the moving image.

44. The method according to p. 43, characterized in that the step of bringing to an odd value of checksum blocks of transform coefficients includes the following steps: the sum of the transform coefficients in each block to obtain the sum, and each conversion factor has parity to ensure that the amount, with parity, establishing that the checksum is even, and if it is determined that the checksum is even, inverting the parity of one of the transform coefficients in the block to do a checksum odd.

45. The method according to p. 43, wherein each conversion coefficient represented by a binary number, including the least significant bit, the step of bringing to an odd sum value of each block of transform coefficients comprises the following steps: assessment of the LSB of each of the transform coefficients, the calculation of conversion factors with the single least significant bit in the block, for receiving the account and if the account is an even number, the change per unit of one of the transform coefficients in the block.

46. The method according to one of paragraphs.43 to 45, characterized in that is used for satisifes records the formation of the recording signal from the compressed signal of a moving image and recording the recording signal on the recording media.

47. The method according to one of paragraphs.43 to 45, characterized in that is used for transmitting a compressed signal of the moving image through a transmission channel and includes the following steps: provision of a transmission channel, the signal transmission of the compressed signal of the moving image and signal transmission in a transmission channel.

48. The recording media on which is recorded multiplexed signal representing a moving image, and the multiplexed signal of a moving image is generated from the signal of the moving image through the use of predictive coding and orthogonal transform to blocks of the signal of the moving image to obtain a block of transform coefficients, which is formed multiplexed signal of the moving image, characterized in that it contains are given to odd value of checksum blocks of transform coefficients before applying inverse orthogonal transform and predictive decoding the blocks of transform coefficients to obtain blocks of vosstanavlivaeshsya image.

49. The recording medium on p. 48, characterized in that the blocks of transform coefficients are subjected to the operation of bringing the sum to an odd value by summing the transform coefficients in each block to obtain the sum, and each conversion factor has parity to ensure that the amount, with parity, establishing that the checksum is even, and if it is determined that the checksum is even, inverting the parity of one of the transform coefficients in the block to do a checksum odd.

50. The recording medium on p. 48, wherein each conversion coefficient represented by a binary number, including the least significant bit, and the blocks of transform coefficients are subjected to the operation of bringing the sum to an odd value by evaluating the LSB of each of the transform coefficients, the calculation of the transform coefficients in the block, with the single least significant bit, to get the account and if the account is an even number of changes per unit of one of the transform coefficients in the block.

 

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