Device for quality control of discrete communication channels

 

(57) Abstract:

The invention relates to techniques for telecommunication and can be used in adaptive data transmission systems for monitoring the status of discrete communication channels. The technical result of the invention is reducing the delay in the determination of the moment of changing the state of a discrete communication channel. This goal is achieved by the fact that the device containing the sensor signals reset, connected in series block matching, the input of which is the input of the block error detection and counter single errors have been added to the register, two delay elements, a memory unit, an adder, a subtraction unit, the two units compare codes, two inverters, two logical element And a logic element OR two triggers and new relationships. The device implements the evaluation of the state of the channel according to the method of confidence intervals, which provides a higher accuracy in comparison with point estimation, which makes it easier to detect when the status changes of the channel. 4 Il.

The invention relates to telecommunication and can be used to analyze the state of the communication channel affected by interference, leading to e connected in series block matching, which input is the input of the block error detection and counter single error, a second input connected to the output of the sensor signals reset [1].

It is known device [2] , providing higher accuracy assessment of the condition of the channel by introducing two elements of the delay element And the element OR counter related errors and new links.

The common disadvantage of the devices [1,2] is the delay in deciding about the status of the channel. This is because during the transition of the channel from one state to another controlled sample for time T=Nt, where N is the number of blocks in a controlled sample, t is the duration of one block) contains the units taken in different States of the channel. Therefore, the number of errors in the controlled sample changes its value gradually, reaching a threshold value, corresponding to the decision on the status of the channel, only after some time after this change.

To reduce lag features:

- determine the average number of errors in a controlled sample of size N for each link-state: state =owith error probability pothe average Chi is error p1the average number of errors is determined by the formula

k1.Wed,= p1N (2)

- for the number of errors k in another controlled sample to determine confidence interval [kn,kin], the boundaries of which are calculated by the formula

< / BR>
where

t- is the factor that determines the number of standard deviations the value k, which need to defer to the left and to the right of the current value of k to ensure that the confidence interval has covered an average value k with a given probability [3];

- to decide on the state of the channel according to the rule

< / BR>
according to which the channel is in state [n]=0: p = paboutif the confidence interval [kn, Kin] covers the value of kOh,cf.and the state [n]=1: p = p1if this interval covers the value of k1.cf.. In addition, it is believed that the canal passed into the state [n]=1: p = p1if the interval [kn, kin] covered both values of kOh,cf.and k1,cf.provided that in the previous step estimation he is in the state [n-1]=0: . In turn it is believed that the canal passed into the state [n]=0: p = p0if the interval [kn, kin] covered kOh,cf.and k1,cf.peretse thus, so he covered both values of kOh,cf.and k1,cf.during the transition of the channel from one state to another. The decision-making process according to the formula [4] is illustrated in Fig.1.

In Fig. 2 shows time diagrams, allowing to compare the determination of the state of the channel according to the method of confidence intervals, i.e., according to rule (1) to(4), and by the method of point estimation, i.e. by comparing the number of errors k with a threshold. In this figure, the solid stepped line shows the average number of errors in the controlled sample, equal to kOh,cf.as0and k1,cf.- as1; the sequence of discrete samples is the actual number of errors k in a controlled sample; tabout- when changing channel status; square brackets shows the confidence intervals for k;1is the delay a decision about the status of the channel according to the method of confidence intervals;2is the delay a decision about the status of the channel by the method of point estimation. It is evident from Fig.2 shows that2>1, i.e., procedure (1)-(4) determines the status of the channel before comparing the number of errors k with a threshold.

As prototypename decision on the alleged invention is to reduce the delay in the determination of the moment of changing the state of a discrete communication channel.

To obtain a technical result in the device for quality control of discrete communication channels, containing the sensor signals reset, connected in series block matching, the input of which is the input of the block error detection and counter single error, entered the register, two delay elements, a memory unit, an adder, a subtraction unit, the two units compare codes, two inverters, two logical element And, logical-OR, and two triggers, and the sensor output signal reset is connected directly to the first input register, and through the first delay element with a second counter input single error, the output of which is connected to the input register, the output of which is connected to the input of the memory block, the first inputs of the adder and the subtractor, a second input which is connected to the output of the memory unit; the output of the adder connected to the first input of the first block of code compares the second input is a second input device, and the output of the subtraction unit is connected to the first input of the second block of code compares the second input of which is the third input device; the output of the first block of code compares connected to the first input of the first logic element And the first vhodyaschego element And, and through the first inverter to the second input of the second logic element, And a third input connected through a second inverter with the output of the first flip-flop, the first input of which is connected through a second delay element to the output of the first delay element and the second input is connected to the output of the second trigger whose output is the output; the first input of the second trigger is connected to the output of the first delay element, and a second input connected to the output of logic element OR a first input connected to the output of the first logic element, And and the second input is connected to the output of the second logic element And.

The proposed technical solution the device for quality control of discrete communication channels characterized by the fact that reduces lag in making decisions about the status of the communication channel, which is achieved by the introduction of the register, two elements of the delay block of memory, adders, the subtraction unit, two units of comparison codes, two inverters, two logic elements And logic element OR, two triggers, and new links.

Positive effect, namely the reduction of delays in decision-making about the status of the communication channel is more high reliability in comparison with point estimation. As shown by the simulation results, the confidence interval for the number of errors in the controlled sample quickly covers "the new state of the channel than the number of errors in the controlled sample passes through the threshold level.

Structural diagram of the device shown in Fig.3.

Device for quality control of discrete communication channels, containing the sensor signals reset 1, connected in series block matching 2, the inlet of which is the input of the block error detection 3, counter single error 4 and case 5, the delay elements 6, 7, the memory unit 8, an adder 9, a subtraction unit 10, the blocks comparison codes 11, 12, inverters 13, 14, logic gates And 15, 16, the logical element OR 17 and triggers 18, 19, moreover, the sensor output signals reset 1 is connected directly to the first input of the register 5, and through a delay element 7 with the second counter input single error 4, the output of which is connected to the input of the register 5, the output of which is connected to the input of the memory unit 8, the first inputs of the adder 9 and the subtraction unit 10, the second inputs of which are connected with the output of the memory block 8; the output of the adder 8 is connected to the first input of the comparison codes 11, the second input of which is the WTO is d which is the third input device; the output of the Comparer codes 11 connected to the first input of the logical element And 15 and the first input of the logic element And 16, and the output of the Comparer code 12 is connected to the second input of logic element And 15, and through the inverter 13 to the second input of logic element And 16, a third input connected through an inverter 14 with the output of the trigger 19, the first input of which is connected through a delay element 7 to the output of the delay element 6 and the second input is connected to the output of the trigger 18, the output of which is the output; the first input of the trigger 18 is connected to the output of the delay element 6, and a second input connected to the output of logic element OR 17, the first input connected to the output of the logical element And 15, and a second input connected to the output of the logical element And 16.

The device operates as follows.

The signal from the discrete communication channel through the block 1 is supplied to the unit 2, which detects errors. If an error is detected at the output of unit 2, you receive a pulse input to the counter 4, counting these pulses.

Sensor 1 produces pulses with a period T equal to the interval of the monitoring channel and appearing in moments the end of the controlled sample (Fig. 4). About the th observation interval. After recording the information in the register 5, the same pulse delayed by the delay element 6, resets the counter to zero 4, preparing it for the next measuring cycle, and writes to the trigger 18, the outputs of the OR element 17. A logical unit at the output of the trigger 18 indicates that the channel is in state [n]=1. A logical zero in the trigger 18 indicates that the channel is in state [n]=0. After an additional delay element 7, the pulse sensor signals reset 1 arrives at the trigger 19, rewriting in his state of the trigger 18. The trigger 19 is used to store information [n-1] about the state of the channel is not previous step estimation. From the output of the register 5, the code number k is supplied to the address bus of the memory block 8, which stores pre-calculated by the formula

< / BR>
the values needed to define the boundaries of the confidence intervals calculated by the formula (3). These values are added to the k to the adder 9 and deducted from k in the subtraction unit 10, forming the outputs of these blocks, the values of the boundaries of the confidence intervals of the knand kinrespectively. Codes boundaries of the confidence intervals of the kn, kinfrom the outputs of the adder 9 and the subtraction unit 10 accordingly sustained the, is the quiet pre-defined by the formulas (1) and (2) and fed to a second input blocks of comparing codes 11, 12, respectively. If the first or the fourth condition of formula (4), the output of the OR element 17 there is a logical zero, which is written in the trigger 18 pulse from the output of the delay element 6. A logical zero at the output of the trigger 18 is a sign that the channel is in state0characterized by the error probability pabout. If the second or the third condition of formula (4), the output of the OR element 17 appears logical unit and the trigger 18 moves to the state "1", it indicates the transition of the channel state1with error probability p1.

Units of comparison codes can be implemented on the basis of the digital Comparators CSP or IP, and the memory block on the chip RT(5,6) [4].

Literature

1. A. S. N 269976 (USSR), CL H 04 L 1/10, 1968 (prototype).

2. A. S. N 658753 (USSR), CL H 04 B 3/46 1979.

3. Wentzel E. C. probability Theory. - M.: Fizmatgiz, Moscow, 1967.

4. Zeldin E. A. Digital integrated circuits in information-measuring equipment. - L.: Energoatomizdat. Leningrad. Department, 1986, (page 150).

Stroitelnye block matching, which input is the input of the block error detection and counter single errors, characterized in that it further introduced a register, two delay elements, a memory unit, an adder, a subtraction unit, the two units compare codes, two inverters, two logical element And, logical-OR, and two triggers, and the sensor output signal reset is connected directly to the first input register, and through the first delay element with a second counter input single error, the output of which is connected to the input register, the output of which is connected to the input of the memory block, the first inputs of the adder and the subtractor, a second input which is connected to the output of the memory block, the output of the adder connected to the first input of the first block of code compares the second input is a second input device, and the output of the subtraction unit is connected to the first input of the second block of code compares the second input of which is the third input device, the output of the first block of code compares connected to the first input of the first logic element And the first input of the second logic gate And the output of the second block of code compares connected to the second input of the first logic element And through the first investment is the output of the first trigger, the first input of which is connected through a second delay element to the output of the first delay element and the second input is connected to the output of the second trigger whose output is the output, the first input of the second trigger is connected to the output of the first delay element, and a second input connected to the output of logic element OR a first input connected to the output of the first logic element And a second input connected to the output of the second logic element I.

 

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