The frequency synthesizer

 

(57) Abstract:

The invention relates to electrical engineering and can be used in transmitting and receiving devices. The objective of the invention is the simplification of the device and improving the accuracy of the output frequency. In the frequency synthesizer containing connected in series multiplexer, accumulating adder, a memory unit, the digital-analog Converter and low pass filter, the element OR the output of which is connected to a clock input of the accumulating adder, while the first and second information inputs of the multiplexer are respectively the input frequency and the input set extension code synthesizer frequency control input of the multiplexer and the first input of the OR element connected to the output transfer accumulating adder, the second input element OR an input reference signal of the frequency synthesizer. 1 Il.

The invention relates to electrical engineering and can be used in transmitting and receiving devices.

Known frequency synthesizer containing a reference oscillator, a cumulative adder, a delay element, a multiplexer, two adder codes, three frequency register, the multiplier to testator is too complex and does not provide sufficient accuracy output frequency.

Known frequency synthesizers, in order to improve accuracy using different circuit designs [2].

Used to improve the accuracy of the circuitry or complex, such as schema decimal adder, where due to the series connection of binary adders reduces the performance of the scheme, or not at all can ensure the accuracy not worse than the accuracy of the reference oscillator.

The objective of the invention is the simplification of the device and improving the accuracy of the output frequency.

To do this, in the frequency synthesizer containing connected in series multiplexer, accumulating adder, a memory unit, the digital-analog Converter and low pass filter, the element OR the output of which is connected to a clock input of the accumulating adder, while the first and second information inputs of the multiplexer are respectively the input frequency and the input set extension code synthesizer frequency control input of the multiplexer and the first input of the OR element connected to the output transfer accumulating adder, the second input element OR an input reference signal of the frequency synthesizer.

The proposed solution of santow and new relationships between the elements.

The drawing shows a block electrical diagram of the device.

The frequency synthesizer includes connected in series multiplexer 1 (MX), accumulating adder 2 (HC), block 3 memory (BP), digital-to-analogue Converter 4 (DAC) and the filter 5 low pass (LPF). Additionally introduced element OR 6, the output of which is connected to a clock input of the accumulating adder, while the first and second information inputs of the multiplexer are respectively the input frequency and the input set extension code frequency synthesizer On the control input of the multiplexer and the first input of the OR element connected to the output transfer accumulating adder, the second input element OR an input reference signal Fo of the frequency synthesizer.

The device operates as follows.

As you know, in direct digital frequency synthesizers formation Segal given frequency by calculating the clock in the time code linearly increasing phase transformation code phase code amplitude sinusoidal oscillations, d / a conversion and low-pass filtering.

The output frequency of the direct digital synthesis>/BR>N - accumulating capacity of the accumulator.

The output frequency of the standard high-stability oscillators, usually a multiple of 1 MHz, the accumulating capacity of the accumulator is equal to powers of 2.

If natrataste numbers in the numerator and denominator of the real value of the frequency at the output of the device is obtained by dividing these numbers do not accurately corresponds to the desired frequency value, because the result of dividing the number is not an integer.

Imagine the capacity of the accumulating adder as the sum of two numbers - one of them is a multiple of the code of the desired frequency A, and the other adds this number to the value, which is a power of 2

N = K A + D

where K is an integer;

Dr. incremental code.

To obtain the value of output frequency accuracy of the reference oscillator is provided in each operating cycle is accumulating adder to adjust its capacity. For this purpose, in the known device additionally introduced element OR 6.

In the absence of the signal transfer on the output of the accumulating adder 2 to the information input of the accumulating adder 2 is connected code frequency A. If the flow through the element OR 6 pulses of the reference signal on the clock input is accumulating adder 2 is code with each pulse of the reference frequency.

Overflow is accumulating adder 2, which occurs after receipt of the next pulse of the reference frequency, the output transfer accumulating adder 2 a signal, which, by controlling the multiplexer 1, and connects to the information input of the accumulating adder 2 extension code E and at the same time, acting through the element OR 6 on the clock input is accumulating adder 2 as an additional measure, summarizes the incremental code D code of residue accumulating adder 2.

At the end of the process an additional summation signal to transfer the output is accumulating adder 2 disappears and the multiplexer 1 reapplies code frequency And on the information input is accumulating adder 2, the next pulse of the reference signal continues summation code And begins a new cycle of accumulating adder 2.

The summation of each new cycle starts with a code equal to the amount of residue from the previous cycle and the extension code.

The generated code values output from the accumulating adder 2 is provided directly to the block 3 memory, executed on programmable permanent memory (ROM), and determine aranym capacity is accumulating adder (N-D). The remainder of the ROM is not programmed and is not used. Each code on the output of the accumulating adder 2 corresponds to the exact value of the envelope of the sinusoid.

Code amplitude arrives at the inputs of digital-to-analogue Converter 4, the output which is obtained from a multi-level step voltage, from which the filter 5 lower frequencies allocated signal generated frequency.

The advantage of the proposed device in comparison with the known is that due to the correction capacity of the accumulating adder in each cycle of its operation, the accuracy of the output frequency of the frequency synthesizer even when nonmultiple values of the accumulating capacity of the accumulator and the frequency of the reference signal is determined by the accuracy of the reference oscillator frequency.

The device proposed by the authors differs from known as the organization of the code Converter, and mapping the generated code values at the output of the accumulating adder in multi-level step voltage and has the following advantages: scheme of the claimed device is more simple, the accuracy of the generated frequencies above.

The frequency synthesizer containing a follower of the lowpass characterized in that it introduced an element OR the output of which is connected to a clock input of the accumulating adder, while the first and second information inputs of the multiplexer are respectively the input frequency and the input set extension code synthesizer frequency control input of the multiplexer and the first input of the OR element connected to the output transfer accumulating adder, the second input element OR an input reference signal of the frequency synthesizer.

 

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