The push-pull switch

 

(57) Abstract:

The invention relates to switching devices and may find application in systems management, monitoring, measuring, computing devices, communication devices in different industries. The technical result consists in the fact that the device allows you to switch the output signal without a delay relative to the input signal. The device manages two consecutive signals using a single control channel. The switch contains a JK flip-flop, two elements And the elements, OR, AND NOT and the delay line. 1 Il.

The invention relates to switching devices and may find application in systems management, monitoring, measuring, computing devices, communication devices in different industries.

Known switch /R-S trigger/ described, for example, in [1], which contains two elements AND NOT with cross-feedback, two inputs and two outputs. The disadvantages of such devices should include the need for changes to the opposite value of the two input signals from two channels to switch the device to its original state /off/.

Also known peretu, the control circuit on the digital elements /MACS/ or transistors, 5 inputs and two outputs. The disadvantages of such devices include switching device after the control signal that generates the delay of the output signal relative to the input.

However, many digital systems do not allow for these delays and require control switch two cycles over a single channel /switch with memory/.

As the prototype is accepted, the device described in [2].

The aim of the present invention is the extension of functionality, namely the ability to control switch on one channel, two bars and an exception signal output delay relative to the input.

This objective is achieved in that the device additionally introduced one input element AND two two-input element And one trehochkovoy element OR one delay line.

The drawing shows a diagram of the push-pull switch.

The device contains an input I, output O, J-K-flip-flop 1, the first input element And 2, trehochkovoy element OR 3, the delay line 4, the input element AND NOT 5 and the second Duhlata the enta And 2 and a second input of two-input element AND NOT 5. Direct output of J-K flip-flop 1 is connected to the first input of the second input element And 6 and the first input of two-input element AND NOT 5, the output of which is connected with the second input of the second input element And 6. The outputs of the first 2 and the second 6 input elements And connected with the first and third inputs Tregubova item OR 3, respectively, and the output of the first element 2 is also connected to the input of the delay line 3, the output of which is connected with the second input Tregubova item OR 3, the output of which in turn is connected to the output O of the device.

Using J-K flip-flop element AND-NOT, two elements, one element OR one delay line to achieve this goal in the sources not detected. The device operates as follows. J-K-flip-flop 1 to implement the counting mode must be on the inputs J and K of the potential of a single signal. In the initial state the device is filing a short-zero signal at the input R when the potential of a single signal at input S J-K-flip-flop 1. While the direct output of J-K flip-flop 1 is set to zero, and the inverse - isolated signal. At the output of the Output device is zero signal. In such herded /first quantum/ single signal fed to the input of J-K flip-flop 1, the first input of the first input element 2 and the first input of two-input element AND NOT 5. The output of the first element And 2 appears when this unit the signal at the first input of two-input element OR the output of which the output you receive a single signal. At the same time a single signal at the input of the delay line 4. The output of two-input element AND NOT 5 is saved to a single signal to the second input of the second input element And 6, the output of which there is still no signal. After graduating at the input I of the device of the first control signal J-K trigger 1 turns into a single signal to direct the output and zero - inverse. At the output of two-input element AND NOT 5 is saved to a single signal, and the output of the second input element And 6 receive a single signal on the third input Tregubova item OR 3. At the time of switching of the J-K flip-flop 1 and the second element And 6-element OR 3 saves at its output a single signal due to the delay of a single signal at its second input single-output signal delay line 4. The output of the first input element And 2 receive a zero signal will occupait to the second input of two-input element AND NOT 5, switching it to a single output signal at zero, which is applied to a second input of the second input element And 6. Its output is zero, the signal received at the third input element OR 3. When this element OR 3 acquires on all inputs zero signal and output on the Output device, you receive a zero signal. After finishing the second input of J-K trigger 1 goes to zero state direct and single - inverted outputs. Diagram of the device goes into its original state.

Thus a single output signal appears when the first control signal /on the front of the signal of the first stage/ and disappears when the second control signal /on the front of the signal of the second quantum/, which virtually eliminates the delay of the output signal relative to the input.

For normal operation of the device, you must have a time delay of the signal delay line 4.

tZVtPC.Tr+tPC.n,

tPC.Trand tPC.pthe time switch J-K flip-flop element And respectively.

Literature:

1. Zeldin E. A. Digital integrated circuits in information-measuring devices is azione measuring equipment. HP: Energoatomizdat, 1986, S. 181, Fig. 10-13.

The push-pull switch that contains the input, output and JK flip-flop, characterized in that it additionally introduced elements of two-input AND - NOT, trehochkovoy OR two two-input element And the delay line, and an input device connected to the input of CJK-flip-flop, the first input of the first input element And a second input of two-input element AND IS NOT, a direct output of the JK-flip-flop connected to the first input of two-input element AND - NOT and the first input of the second input element And to the second input of which is connected to the output of two-input element AND - NOT, and the inverted output of the JK-flip-flop connected to a second input of the first input element And the output of which is connected to the first input Tregubova element OR the input of the delay line, the output of which is connected to a second input Tregubova element OR, to the third input of which is connected the output of the second two-input And gates and the output device is connected to the output Tregubova OR.

 

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