A device for computing the eigenvalues (non) matrix

 

(57) Abstract:

The invention relates to the field of computer engineering and can be used in specialized computer systems for computing the eigenvalues of the matrix (n n). The purpose of the invention is to enhance reliability at the expense of control and redundancy, enhanced functions by solving problems of different dimensions. This objective is achieved in that the device contains L processing units 1 (where L = p + R, where R is the number of redundant processing units); unit 2 I / o; L combinational adders 3; (L - 1) register 4; L nodes compare 5; L groups of elements, OR 6; L groups of elements And 7; the element OR NOT 8 and the element OR 9. 2 C.p. f-crystals, 2 tab., 5 Il.

The invention relates to the field of computer engineering and can be used in specialized computer systems to calculate all the eigenvalues of (n n)-matrix.

A device for computing all eigenvalues of a symmetric (n n)-matrix containing the n processing units of the first type (3n2-n)/2 processing units of the second type and the unit of analysis [1].

The closest in technical essence of avlo type, (2n-1) processing units [2].

Usually to ensure the accuracy obtained by the data processing results using the test periodic monitoring conducted by using external software and hardware. When the periodic test control the probability of missing failure processing unit proportional to the time between the test audits (control period), the volume of erroneous information, the issuance of which occurs between the test checks, is also proportional to the control period. Time spent on test validation are determined by the volume of the test, so the bandwidth range of the processing units of the known devices is inversely proportional to the time spent on test validation. The probability of a failure is detected using the test checks is determined by the resolution of the test and the amount of equipment covered by the control. The recovery time computing process after detection of the failure processing unit (obtaining a reliable result on the output device) is proportional to the number n of processing units of the device (the length n of the line device).

The purpose of the invention is to enhance reliability at the expense of what cnyh dimensional matrices.

This objective is achieved in that the device contains (2n-1) processing units 1, and a clock input device 21 is connected to the clock inputs of all processing units 1, information inputs of the first group 12 of the device connected to the information inputs of the first groups of all processing units, the first control input 17 of the device connected to the first control inputs of all processing units, the outputs of the first group of the i-th processing unit 1 (where i = 1, ..., (2n-2)) are connected respectively to the information inputs of the second group (i+1)-th processing unit, introduced with the 2n-th and L-th processing units 1 (where L = 2n - 1 + R, R is the number of redundant processing units 1), block I / o 2, L - combinational adders 3, (L-1) register 4, L nodes comparison 5, (L-1) group elements, OR 6, L groups of elements And 7, the element OR NOT 8 and the element OR 9, moreover, the clock input device 21 is connected to the clock inputs of the processing units with 2n-th to L-th block I / o 2 and inputs the read/write all registers 4, the first and second outputs of the i-th processing unit connected respectively to the second and third control inputs (i+1)-th processing unit outputs the first group, the first and second outputs of the j-th processing unit 1 (where j = 2n-1, ..., L-1) are connected respectively to inform the passages of the second group 10, the second 13 and third 14 control inputs connected respectively to the information inputs of the first group, the first and second control inputs of the block I / o 2, the outputs of the first group, the first and second outputs of which are connected respectively to the information inputs of the second group, the second and third control inputs of the first processing unit, the outputs of the second group which is connected to information inputs of the second group block I / o 2, the information inputs of the third group of the k-th processing unit 1 (where k = 1, ..., L) connected respectively to the outputs of the elements And 7 k-th group, the first inputs of elements And 7 l-th group (where l = 1, ..., L-1) are connected respectively to the outputs of the second group (l + 1)-th processing unit, the input elements And 7 L-th group are connected respectively to the information inputs of the third group 11 of the device control inputs of the first group 18 of which are connected respectively to the control inputs of the first group of the first processing unit, the outputs of the third group of the k-th processing unit connected to the inputs of the group of k-combinational adder 3, the outputs of the l-th combinational adder 3 is connected to information inputs of the l-th register 4 and the inputs of the first group of l-th node comparison 5 the nternet outputs of the k-th node comparison 5 are connected respectively to the second inputs of elements And 7 k-th group and the k-th input element OR NOT 8, the output of which is connected to the first input element OR 9, the output of which is connected to the output 30 of the sign of failure, the outputs of the l-th register 4 are connected respectively to the first inputs of the element OR 6 l-th group, the outputs of which are connected respectively to the control inputs of the first group (l+1)-th processing unit 1, the outputs of the fourth group of l-th processing unit 1 is connected respectively to the second inputs of the elements OR 6 l-th group, control inputs of the second group 19 devices are connected to the control inputs of the group block I / o 2 and the control inputs of the second groups of all processing units 1, the control inputs of the third group 20 are connected to the inputs of the second group all sites in comparison 5, the input set to the initial state 15, the inputs are exactly 16 and the input 28 sign of the end of solving the problem connected respectively to the input of the installation to its original state, the information inputs of the third group and the third output block I / o 2, the fourth output of which is connected to the second input element OR 9, k-th input set of the first group of 23 device connected to the first input set of the k-th processing unit 1, the k-th input set of the second group 24 of the device connected to the second input set of the k-th BL the processing 1, k-th entry lock device 22 is connected to the input block of the k-th processing unit 1, the outputs of the groups from the second to the (L + 1)-th and outputs (L + 2)-th group block I / o connected respectively to the outputs of the 26 and output characteristic of the device 27.

Unit 2 I / o contains the first and second nodes 31 and 32 I / o node comparison 33, the trigger 34 and the group of items 35, and informational inputs of the first group 36, the second group 37, the third group 40, the first control input 38, the second control input 39, the control inputs 41 of the group and the input 43 of the installation to its original state unit connected respectively to the information inputs of the first, second, and third groups, the first, second, third control inputs, the control inputs of the group and the input set to the initial state of the first and second nodes, I / o, clock input 44 of the block is connected to the clock inputs of the first and second nodes, I / o and synchronization input of the trigger 34, the outputs of the first group, the outputs of the groups from the second to the (L + 1)-th and outputs (L + 2)-th group, the first, second and third outputs of the first node of the input-output 31 connected respectively to the inputs of the first node group comparison 33 and the first inputs of elements And 35 group, the outputs are connected the UB>3(L + 2)-th group, the first 40, second 47 and 48 third outputs of the block, the outputs of the first, second and third group, the first, second and third outputs of the second host I / o 32 are connected to the inputs of the second node group comparison 33, the output of which is connected to the information input of the trigger 34, the direct and inverted outputs of which are connected respectively to the second inputs of elements And 35 group and the fourth output 49 of the block.

Each processing unit 1 includes first and second computing nodes 50 and 51, site 52 comparison, the trigger 53, the first, second and third nodes And elements 54, 55 and 56, the node elements OR 57 and the element And 58, and informational inputs of the first group 59, the third group 60, the control inputs of the first group 65, the second control input 62 and the third control input 63 connected respectively to the inputs of the groups of the first and second nodes And elements 54 and 55, the outputs of the first group of the first node elements And 54 are connected to the inputs of the first group of node elements OR 57, the outputs of which are connected respectively to the outputs of the first group 74, the second group 75, the first 76 and second 77 outputs of the block, the outputs of the first group to the second node elements And 55 are connected respectively to the information inputs of the first group, second group, the first choice of the second group, the first and second outputs of the first computing node 50 is connected to the inputs of the first group of node comparisons 52 and input group of the third node elements And 56, the outputs of which are connected to the inputs of the second group of node elements OR 57, the outputs of the first group, second group, the first and second outputs of the second computing node 51 is connected to the inputs of the second node group comparison 52, the output of which is connected to the information input of the trigger 53, the output of which is connected to the input of the third node elements And 56, the input of the second node elements And 55, inverted input of the first node elements And 54 and the third output block 78, the outputs of the second groups of the first and second computing nodes 54 and 55 are connected respectively to the outputs of the fourth group 73 and the third group block 72, the information inputs of the second group 61, the first control input 64, the control inputs of the second group 66 and the first input set 67 which are connected respectively to the information inputs of the third group, the third control inputs, the control inputs of the groups and inputs installed in the original state of the first 50 and second 51 computing nodes, the second and third inputs of the unit are connected respectively to the inputs setup to zero and the trigger unit 53, the input is the same And 58, the output of which is connected to the clock inputs of the first and second computing nodes and the synchronization input of the trigger 53.

Each node I / o 31 (32) contains L Raman vychitala 79, the host computing the reciprocal of the number 80, two divider 81 and 82, L nodes comparison 83, two registers 84 and 85, two groups of registers 86, three trigger - 87 - 89, (5L + 4) group elements And 90 - 97, the six elements And 98 - 103, three groups of elements OR 104 - 106, two elements OR 107 and 108 and decoder 109, moreover, the information inputs of the first group 109 host I / o is connected to information inputs of the first register 84, the outputs of which are connected to first inputs of elements And 96 of the first group, the outputs are connected to first inputs of elements OR 104 of the first group, the outputs of which are connected to the outputs of the first group 117 host I / o information inputs of the second group 110 which is connected to information inputs of the second register 85, the direct outputs of which are connected to information inputs of the first register of the first group 861information inputs compute node reciprocal 80 and the first inputs of elements And 97 of the second group, the outputs of which are connected to the second inputs of the elements OR 104 of the first group, the outputs of the node vices is the elements And the third group 95 and the first input element And the fourth group 94, the outputs are connected respectively to third and fourth inputs of elements OR 104 of the first group, the outputs of the i-th register of the first group 86 (where i = 1, ..., L) are connected to first inputs of elements And 90 (4 + i)-th group, the first inputs of elements AND 91 (4 + 2L + i)-th group and outputs (2 + i)-th group 118 host I / o, the outputs of the elements AND 91 (4 + 2L + i)the second group are connected respectively to the inputs of the elements 106 OR the second group, the outputs of which are connected to information inputs of the first register 86L + 1 of the second group, the outputs of the elements And 90 (4 + i)-th group are connected to the inputs of the first group of the i-th combination vicites 79 whose outputs are connected respectively to the information inputs of the first group of the i-th node comparison 83, the output of which is connected to the first input element AND 92 (4 + 3L + i)-th group, the output of the i-th element AND 92 (4 + 3L + i)-th group is connected to the i-th inputs of elements And 93 (4 + 4L + i)-th group, the output of which is connected to the i-th input of the second element OR 108, the output of which is connected to the third output node 120 I / o, data input 111 of the third group which is connected to information inputs of the second group all sites in comparison 83, the outputs of the j-th register of the second group 86 (where j = 1, ..., L - 1) connected to information inputs (j + 1)-th registrati to the first inputs of elements AND 902L(4 + 2L)-th group, the outputs of the elements And 90 (4 + L + i)-th group are connected to the inputs of the second group of the i-th vicites 79, the first 112 and second 113 control inputs of node I / o connected respectively to the information inputs of the first 87 and second 88 triggers, direct the first flip-flop 87 is connected to the first inputs of the first element 100, the fourth element And 103 and the first output node 121 I / o, the inverse output of the first flip-flop 87 is connected to the first input 101 second and third elements 102 And direct the output of the second trigger 88 is connected to the second inputs of the first element 100, the third element 102 and the second output node 122 of the input-output inverted output of the second trigger 88 is connected to the second inputs of the second 101 and 103 fourth elements And control inputs group 114 of node I / o is connected to the inputs of the decoder 109, a clock input node 114 I / o connected to the counting inputs of the first 81 and second 82 divider, the first inputs 98 fifth and sixth 99 elements And inputs the synchronization triggers from the first to the third 87 - 89 and inputs the read/write of the first 84 and second registers 85, the output of the fifth element And 98 are connected to the inputs of the read/write registers 86 of the first and second groups, the output of the sixth element And 99 are connected to the odes of the first 81 and second 82 divider connected respectively to the second input of the first element OR 107, and the control input of the third trigger 89, the output of which is connected to the second input of the sixth element And 99 and the input set to the zero state of the first divider 81, j-th output of the decoder 109 is connected to the second inputs of elements AND 91 (4 + 2L + j)-th group (j = ), j-th entry of items OR 105 with the j-th to the first (j = ) and (j + 1)-th input element And 93 (4 + 4L + j)-th group, the output of the j-th element OR 105 is connected to the second inputs of the j-th element And the (4 + j)-th group 90, (4 + L + j)-th group 90 and (4 + 3L + j)-th group 92, L-th output of the decoder is connected to the second inputs of the L-th element And the (4 + L)-th group 90L, (4 + 2L)-th group 902Land (4 + 4L)-th group 92Lthe input set to the initial state node 115 I / o connected to the inputs setup to zero all flip-flops, registers and dividers node I / o, output i-th element OR 105 of the second group are connected to the i-th outputs (3 + L)-th group 119 host I / o, L-th output of which is connected to the L-th output of the decoder 109.

Each compute node 50 (51) contains combinational adder 123, combinational multiplier 124, four register 125, 126, 127 and 129, the group of registers 128, three trigger 130 - 132, (L + 7) groups of elements And 133 - 140, three groups of elements OR 141 - 143, two elements OR 144 and 145, the six elements And 146 - 151 and the decoder 152, and informational inputs of the first group 153 calc the charac teristics of the inputs of the first group of combinational multiplier 124 and the first inputs of elements And 136 of the first group, the outputs are connected to the outputs of the first group 163 computing node, the information inputs of the second 154 which is connected to information inputs of the second register 127, the outputs of which are connected to information inputs of the second group of combinational adder 123 and the first inputs of elements And 138 of the second group, the outputs are connected to first inputs of elements OR first 143 group whose outputs are connected to information inputs of the second group of combinational multiplier 124, the outputs of which are connected to information inputs of the second group of combinational adder 123, the information input of the third register 129 and the first inputs of elements And 133 of the third group, the outputs are connected to first inputs of elements OR 142 of the second group, the outputs of which are connected to information inputs of the first register 128 group of information inputs of the third group 155 computing node connected to the first inputs of elements And 134 of the fourth group of information inputs of the fourth register 126, the outputs of which are connected to first inputs of elements And 139 of the fifth group, the outputs of which are connected to the second inputs of the elements OR 143 of the first group, the combinational outputs of the adder 123 is connected to the first inputs of the third group which are connected to the outputs of the elements And 134 of the fourth group, the outputs 129 third register connected to the first inputs of elements And 137 of the seventh group, the outputs of which are connected to the third inputs of the elements OR 143 of the first group, the outputs of the i-th register 128 group (where i = 1,...,L - 1) is connected to the first inputs of elements And 140 (7 + i)-th group and information inputs (i + 1)-th register 128 groups, the outputs of the L-th register group 128 is connected to the first inputs of elements And 140 (7 +L)-th group, the outputs of the elements And 140 groups with eight (7 + L)-th connected respectively to the inputs of elements OR 141 of the third group, the outputs of which are connected to the outputs of the second group 162 computing node, the first control input 156 which is connected to the information input of the first flip-flop 130 and the first (inverted) input of the first element And 151, the second control input 157 of the computing node is connected to the information input of the second trigger 131 and the second input of the first element And 151, the third control input 158 of the computing node is connected to the information input of the third trigger 132 and the third input of the first element And 151, the direct output of the first trigger 130 is connected to the first inputs of the second 148 and 150 third element And the first output 164 of the computing node, the inverse output of the first flip-flop connected to the first whod and 147 fourth elements And the second output 165 of the computing node, inverted output of the second trigger 131 is connected to the second inputs of the second 148 and 149 fifth element And inverted output of the third trigger 132 is connected to the third inputs of the second 148 and 147 fourth elements And the clock input 160 of the computing node connected to the inputs of a read/write register group 128, the first 125, 127 second, fourth registers 126, the first input of the sixth element And 146 and the input synchronization triggers from the first to the third 130 - 132, the input set 161 in the initial state of the computing node connected to the inputs of the installation in the zero state of all registers and triggers, control inputs group 159 computing node connected to the inputs of decoder 152, the k-th output of which (where k = 1,..., L) is connected to the second inputs of elements And 140 (7 + k)-th group, the output of the first 151 element And connected to the second inputs of elements And 134 of the fourth group, the output 148 of the second element And is connected to the second inputs of elements 135 And sixth and seventh 137 groups and the first input of the first element OR 144, the output of which is connected to the second inputs of elements And 136 of the first group, the output of the third element 150 And is connected to the third inputs of elements And 135 of the sixth group, the second input of the first element 144 OR and the first input of the second element OR 145, the n to the second inputs of the elements 138 And the second and third 133 groups, the third input of the first element OR 144 and the second input of the sixth element And 146, the output of which is connected to the input of the read/write 129 third register, the output of the fifth element And 149 are connected to the fourth inputs of elements And 135 of the sixth group, the fourth input of the first element OR 144 and the second input of the second element OR 145.

In Fig. 1 shows a block diagram of the device of Fig. 2 is a structural block circuit diagram of the I / o of Fig. 3 is a structural diagram of a computing unit of Fig. 4 is a block diagram of the node I / o, and Fig. 5 is a structural diagram of a computing node.

The device (Fig. 1) contains L computational units 1 (where L = 2n+R, R is the number of redundant processing units), unit 2 I / o, L combinational adders 3, (L - 1) register 4, L nodes comparison 5, (L - 1) group elements, OR 6, L groups of elements And 7, the element OR NOT 8, item, OR 9, informational inputs 10, 12 control inputs 13 and 14, the input set to the initial state 15, the input values are exactly 16, groups of control inputs 17 - 20, clock input 21, the inputs of the block 22, inputs installation 23 - 25, the outputs 26 of the outputs 27 sign of the result, the output 28 sign of the end of a task, the outputs 29 sign of the failure group and the output 30 Priya 33, the trigger 34, block 35, informational inputs 36 and 37, the control inputs 38 - 41, the input set to the initial state 43, the clock input 44, the outputs 45 - 49.

The processing unit 1 (Fig. 3) contains the compute nodes 50 and 51, site 52 comparison, the trigger 53, the element nodes And 54 - 56, the node elements OR 57, the And gate 58, the information inputs 59 and 61, the control inputs 62 - 66, inputs installation 67 - 69, entry lock 70, the clock input 71, the outputs 72 - 78.

The host I / o 31 (32) (Fig. 4) contains combinational myCitadel 79, node 80 calculate the reciprocal, dividers 81 and 82, nodes comparison, 83, registers 84 and 86, triggers, 87 - 89, group elements And 90 - 97, elements, And 98 - 103, groups of items OR 104 - 106, elements OR 107 and 108, the decoder 109, an information input 109 - 111, control inputs 112 and 113, the input set to the initial state 115, the clock input 116, the outputs 117 - 122.

Compute node 50 (51) (Fig. 5) contains combinational adder 123, combinational multiplier 124, registers 125 - 129, triggers, 130 - 132, groups of items And 133 - 140, groups of items OR 141 - 143, elements OR 144 and 145, elements, And 146 - 151, the decoder 152, informational inputs 153 - 155, control inputs 156 - 159, clock input 160, the input set to the initial state 161, outputs 162 - 165.

IN THE SUB>i(1 i n) matrix A = {aij}, 1 i, j n where the distribution

Based computational schemes triangular power method is a consistent calculation of the matrix

< / BR>
m = 1,2,... rule ACm-1=Bm, Bm= CmRm,

where Cabout= , 1i, jn - some lower triangular matrix with ones on the main diagonal.

This(mii)_iwhen m _ , 1in, therefore, for sufficiently large m can be puti(mii), 1in.

If the iterative process is terminated at step m, the approximate calculation of eigenvectors of ximatrix A can be performed according to the rule

RmU(im)=(mii)U(im)< / BR>
(i.e., the first solution is U(im)triangular system of linear algebraic equations)

x(im)= CmU(im)x x(im).

These ratios show that if for computing the eigenvalues of the matrix A sufficient diagonal elements(mii)to find eigenvectors need and off-diagonal elements of the matrix Rmmthe matrix Cmand Rmrepresented by the following recurrent relations:

< / BR>
< / BR>
Will generate the following matrices, the elements of which will be fed to corresponding inputs of device:

< / BR>
where the asterisk ( * ) denotes any value of 0 or 1.

< / BR>
The elements of dijare l-bit integers aijand the bit number which takes the value 0 or 1.

4. The matrix {hij}, 1 i, j n:

< / BR>
The host I / o 31 (32) has the ability to implement the following functions:

< / BR>
wherejand - values respectively at the inputs 111 and 112 of the host I / o to the j-th clock cycle;

Vi+1and Wj+1values respectively at the outputs 121 and 122 of the host I / o (j + 1)-th step,

Aj+1- the value at the output 117 to (j + 1)-th clock cycle, where

< / BR>
where ajand bjvalues respectively at the inputs 109 and 110 of the node I / o to the j-th step,

< / BR>
In addition, the host I / o 31 (32) produces the issuance of eigenvaluesiand signal processing characteristic end computing eigenvalues.

Approximations to eigenvalues of a matrix from the output of the register 85 are fed to the input register 861at times

< / BR>
/SUP> in the registers 86j(j = ) is carried out clock pulses that are fed with the output element And 98 points in time . In table. 1 shows the state of the divider 81 modulo account (n + 1), divider 82 modulo account n2, trigger registers 89 and 86j(j = ) for n = 3. For (n2- 1)-th clock cycle at the output of the divider 822is formed of a single signal, n2-m step sets the divider 81 in the zero state, and the trigger 89 is in one state, which opens the item And 99. For (n2+ 1)-th cycle through the elements AND 99, OR 107 and 98 clock pulse is supplied to the state clock inputs of the registers 86, recording eigenvalues. The trigger 89 is set to the zero state. For ((i - 1)n + i + mn2- 1)-th cycles (i 1) at the output of the divider 81 is formed of a single signal, which is ((i - 1)n + i + mn2)-m bars (i 1) opens the item And 98 and permits the entry in the registers 86. For (n2(m + 1) - 1)-th cycles at the output of the divider 82 is formed of a single signal, which is (n2(m + 1)-th step sets the trigger 89 in one state and is allowed to write into the registers 86. For (n2(m + 1)-th step of checking the accuracy of calculations . If this ratio is, the output 120 of the sign of the end of the this ratio is not performed, the iterative process of computing eigenvaluesicontinues. Checking the correlation is performed by vycitalem 80, nodes compare 84 (i=), and element 104.

The outputs 119 node 31 (32) I / o used to indicate (means external device interface) outputs 118, excluding the value ofifor specific values of n and L. the outputs 1191, ..., 119nwhere n L, from the outputs of the elements OR 1061, ..., 106ngiven a single characteristic values p, and outputs 119n+1, ..., 119L- zero characteristic p.

Compute node 50 (51) has the ability to implement the following functions:

< / BR>
wherejand - values respectively at the inputs 156 and 157 of the computing node to the j-th clock cycle;

Vj+1and Wj+1values respectively at the outputs 164 and 165 of the computing node to the (j + 1)-th step,

< / BR>
where bj, ajand cjvalues respectively at the inputs 155, 153 and 154 of the computing node to the j-th clock cycle;

k is a parameter defined by the algorithm;

Aj+1- the value at the output 163 of the computing node to the (j + 1)-th clock cycle;

Cj+n-1- the value at the output 162 of the computing node to the (j + n - 1)-th step,

< / BR>
j- value is aetsa to (j + 1)-th stage, and the control signalj5on the j-th step.

The computational module of the first type 8 operates in four modes, which are control signals and supplied respectively to the inputs 15 and 16.

Depending on the values and supplied respectively to the inputs 111 and 112, the node 31 (32) I / o can operate in four modes.

In the first mode,(,) = (1, 1). At the output of element 100 is formed of a single signal (1= 1), which opens the elements And 96. The output 109 is a number, which is recorded in the register 84 and through the elements And 96 and 104 OR available at the output 117. The number of bjis input 110 is recorded in the register 85 and is supplied to the input register 861.

In the second mode,(,) = (0, 0). At the output of element 101 And a signal is generated2= 1, which opens the elements And 97. The number b is recorded in the register 85, available at the output 117 and transferred to the input register 861.

In the third mode(,) = (0, 1). The output element 102 And a signal is generated3= 1, which opens the elements And 95. On output 110 is the number of bjthat is recorded in the register 85 and is supplied to the input register 861. Exit 117 through the compute node back ve). Output element And 103, a signal is generatedj4= 1. Open elements And 94. In register 86 is written the number of bjwhich is fed to the input register 861. With the inverted output of the register 85 at exit 117 issued the number of (-bjthrough the elements And 94 OR 104.

Comparing values(im+1)and(im)runs in the host I / o regardless of the mode specified values .

Compute node 50 (51) operates in five modes, which are control signals , and served respectively to the inputs 153, 157 and 158.

In all modes, write numbers from register 128i(i = 1, L - 1) in the register 128i+1. The output 162 is issued the number recorded in the register 128 L-th. Control signals and are recorded respectively in the triggers 130 and 131 and are given respectively to the outputs 164 and 165.

In the first mode (j,j,j) = (0, 1, 0), output element And 147 is formed a signalj1= 1, which opens the elements And 135, 136, 138, and 146. In the register 125 is written the number of ajin the register 127 - number of cj. The output of multiplier 124 is formed product ajcjthat (j + 1)-th step of records is UP>,j,j) = (1, 0, 0), output element And 148 is formed a signalj2/= 1, open items And 135, 136 and 137. The number of ajrecorded in the register 125 and through the elements And 136 available at the output 163. The output of multiplier 124 is formed product aj< the contents of register 129>, at the output of the adder 123 - sum ((cj+ aj<the contents of register 129>), which is (j + 1)-th step is recorded in the register 128.

In the third mode (j,j) = (0, 0), the output element And 149 is formed a signalj3= 1. Open elements And 139, 135 and 136. In the register 125 is written the number of ajissued at exit 163. The output of multiplier 124 is formed product ajbj(the number of bjrecorded in the register 126), at the output of the adder 48 - sum (cj+ ajbj(in the register 127 is written the number of cj) is written to a (j + 1)-th cycle in the register 1281.

In the fourth mode (j,j) = (1, 1). The output element 150 is formed a signalj4= 1. Compute node works in a similar way as in the third mode.

In the fifth mode (j,j,j) = (0, 1, 1). Output element And 151 is formed a signalj5= 1, , is AutoRAE to the j-th step on the trailing edge of the clock pulse is recorded in the register 1281.

Input and output data streams are formed according to the following expressions.

The outputs 12iand 17i() are the elements of the input matrix {dij} = { aij, } in time

< / BR>
On output 10 are elements of C(oqj), 1 j < q at time = (q - 1)n + j - 1.

The outputs 13 and 14 are given correspondingly control signals and matrices {ij} in time

< / BR>
Own values(im)are formed at the outputs 26i(i = ) when value = 1 at the output 28 at time

< / BR>
The elements of the matrix {h(mij)} generated at the output of the register 85 node 31 (32) block I / o points in time

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In table. 1 shows the state of the triggers, registers, and the outputs of the nodes in the I / o and compute nodes for n = 3 in the absence of failure. On the tenth step of the block 2 is formed is(11)on the fourteenth beat(21)on the eighteenth beat(31)on nineteenth -(12)on the twenty-third beat(2)2/n the I

Each processing unit 1 is duplication of computational operations using computing nodes 50 and 51. The results of operations are generated upon completion of transients in combinational circuits 123 and 124 and are issued on the outputs 162 and 163 of computational nodes, where these results are received, respectively, on the information input node 52 comparison. When the coincidence of the information on the information input node 52 comparison of computational nodes 50 and 51, the processing unit 1jis considered healthy and one output node 52 comparison is recorded in the trigger 53, which is used for fixing the sign of the health of this processing unit 1j. With the trigger output unit 53 is supplied to corresponding inputs of elements And 56 and the outputs of the computing node 50 through the elements And 56 and 57 is fed to the outputs 74 - 77 processing unit 1j. Single output trigger 53 is also provided on the inverted inputs of the And elements 54 and blocks bypass this block processing 1j. As a result, the value of g at the input 65 of the block 1j, available at the output 72 of the block 1j. A single value is given also to the output 78 of block 1jand relevant is edstam external management about the health of block 1j. If this does not match the information on the information input node 52 comparison of computational nodes 50 and 51, the processing unit 1jis considered faulty and zero output node 52 comparison is recorded in the trigger 53. Output trigger 53 zero signal is applied to corresponding inputs of elements And 56 and the data output from the outputs 162 - 165 computing node 50 is blocked. Output trigger 53 zero signal is applied to corresponding inputs of elements And 55 and inverted inputs of elements And 54. As a result, the flow of information in the computing nodes 50 and 51 through the elements And 55 blocks and opens the path of traversal of the given processing unit 1j. In this case, the information coming from the previous processing unit 1j-1through elements 54 and 57 are issued respectively by the outputs 74 and 77 of this processing unit 1j. The value of g at the input 65 of the block 1j, available at the output 73 of the block 1j. A value of zero is given also to the output 78 of block 1jand respectively to the output 29jsign of failure. Zero signal at the output 29jdevice specifies the means of external control on the detected fault block 1j.

To generate Novotny input 24jdevice. In this case, by means of external control output 24jthe device is formed of a single signal through the inlet 68 of the processing unit 1jis supplied to the input set to zero trigger 55. In order to force the processing unit 1jthe structure of the device, for example, after his forced withdrawal or after fixation of false rejection, using input 25jdevice. In this case, by means of external control input 25jthe device is formed of a single signal through the input 69 of the processing unit 1jis supplied to the input set to the trigger unit 53.

Thus, the operation processing unit 1jcan be blocked by an input device 22 of a single signal. In this case, the unit via an input 70 of block 1jis supplied to an inverse input element And 58, which blocks the passage of clock pulses to the clock inputs of the computing nodes 50 and 51 and the trigger 53.

To install registers and triggers computing nodes 50 and 51 block 1jin the initial state at the start and restarts the device using input 23jdevice. For unit 1jin the source of sostoyanii installation to its original state computing nodes 50 and 51. The input set to the initial state of the computing nodes 50 and 51 are connected to the inputs of the installation in the zero state of all registers and flip-flops of the nodes 50 and 51 (Fig. 5 not shown).

To the input 18 of the device is zero value for g. In the presence of intact blocks 11,...., 12n-1with outputs 29I, ..., 292n-1signs of failure are given individual signals which are fed to the inputs of the corresponding combinational adders 3I, ..., 32n-1. The value of g at the input 65 of the block 1iwhere i = 1, ..., 2n-1in the case of health blocks 11, ..., 1i-1is i - 1. In the case of the health unit 1ithis value g outputted to the output 72 of the block 1iand is supplied to the corresponding input of the combinational adder 3ifrom the output of which is removed is g = i, which is recorded in the register 4iand is supplied to one input node of the comparison 5ithe other input of which receives the value 2n-1. Thus, each also in the case of the health unit 1iwith output combinational adder 3ireturns the value g = i.

If the values match, g and 2n-1 with inverted output node comparison 5igiven the zero signal is those on the input 60 of the block 12n-1and further to the input 154 of the respective computing nodes 50 - 51 goes to zero. This defines the working range of units 1 processing. In case of failure of the unit 1ihappens bypass this block, as described above. In the case of health the previous blocks 1I, ..., 1j-1to the input 65 of the block 1jreceives the value g = j - 1, which is then delivered to the output 73 of the block 1jwith outputs 72 and 78 of block 1jremoved zero values and, thus, the output of the combinational adder 3jremoved zero g. As a result, inverted output node comparison 52n-1removed a single value that reveals the elements AND 72n-1. If block 12nOK, to the input 65 of the block 12nreceives the value g = 2n, the output of block 78 12ngiven a single signal and therefore, the output of the combinational adder 32nremoved the value g = 2n-1. As a result, inverted output node comparison 52nremoved zero signal, which closes the elements AND 72n. As a result, the input 60 of the block 12nand further to the input 154 of the respective computing nodes 50 and 51 are received zero values. This defines the working line of the respective bars, supplied to corresponding inputs of elements OR 6iand further does not affect the value of g at the input 65 of the block 1j+1.

Thus, the processing unit 1iderived from the computational process by bypassing, and the first of defective spare blocks, for example, 12nenter in the calculation process, the length of the line of well-functioning processing units of 1 device.

Upon detection of S bounce blocks 1 is bypassing the failed units 1 as described above. Let k be the number of the last failed block-1 line, then the output 73 of the block 1kwill be given a value of g = 2n - 1 - S, which is fed to the input 65 of the block 1k+1. Because the block 1k+1is considered healthy, then exit 72 unit 1k+1given a single signal, the output of the combinational adder 3k+1will be given a value of g = 2n - 3, which is fed to the input 65 of the block 1k+1and so on, When you hit the g-values at the input 65 operable unit 1jat the output of the combinational adder 3iformed magnitude equal to g + 1. When you hit the g-values at the input 65 of the defective block 1iat the output of the combinational adder 3iformed a zero value, and value is the first adder 32n-1+Sthe output of the node comparison 52n-1+Sis is g = 2n-1, with the inverted output node comparison 52n-1+Sgiven a zero signal, which closes the elements AND 72n-1+S. As a result, the output 60 of the block 12n-1+Sand further outputs 154 of the respective computing nodes 50 and 51 are received zero values. This defines the working range of units 1 processing. In this case, one of the inputs of the element OR NOT 8 receives a single signal and respectively at zero signal at the output 49 of the block 2 I / o output 30 sign of failure is removed, the zero signal, which indicates availability of the device. When R < S on the outputs of the nodes compare 5I, ..., 5Lwill be zero, the output of the element OR NOT 8 through the element OR 9 to exit 30 sign of failure will be given a single value, which indicates the exhaustion of the reserve and the failure of the device.

Thus, the accumulation of R failures, the efficiency of the device is stored and the length of the line of well-functioning processing units 1 device remains constant.

The nodes 31 and 32 I / o block I / o 2 also operate in the backup mode. When I'm 33, output node 33 comparison to the information input of the trigger 34 receives a single signal, which is recorded in the trigger 34. If there is a mismatch of information coming from the respective output nodes 31 and 32 I / o, output node 33 comparison to the information input of the trigger 34 receives a zero signal, which is recorded in the trigger 34. A single signal from the inverted output of the trigger 34 through the OR element 9 is held at the output 30 of the sign of failure and a zero signal from the direct output of the trigger 34 blocks the data output from the block 2. Setting the trigger 34 to the zero state is performed using the alarm setup in the initial state of the device (corresponding circuit and, in particular circuit installed in the zero trigger 34 (Fig. 1 - 6 not shown)).

Thus, upon detection of (R + 1)-th failure or upon detection of a failure of the block I / o, output device 30 is given a single sign of failure, which then enters the external controls. When the device is unlocked backup units 1 automatically operate in a control mode duplication. In this case, the inputs of the first backup processing unit 1pwhere p 2n information on the tion in computational nodes 50 and 51 and the subsequent comparison of results in the node 52 backup processing units is updating the values of the triggers 53 these blocks. Then use this backup processing units will be based on their health.

The values of n and (2n-1) are respectively the inputs 19 and 20 of the device. The value of n is supplied through the inlet 41 of the block I / o and the input node 114 I / o 31 (32) to the input of the decoder 109. In addition, the value of n is supplied to the inputs of the initial setup of the account dividers 81 and 82 (not shown). At the output of the divider 81 periodically issued individual signal after counting (n + 1) clock pulses, and the output of the divider 82 - after counting n2clock (multiplier divider 81 is equal to (n + 1), and divider 82 - n2).

After decoding the values of n corresponding input of the decoder 109 the value of xi(i= ) opens the elements AND 91iand 93i. When this output elements AND 91iapproximate values iserved on the information input register 86L+1through the elements OR 106, and also offer the item AND 93iforming signal = 1, which is provided over the element OR 108 to the output 120 of the host I / o. The values of x1, x23..., xLfrom the outputs of the decoder are received at the respective inputs of the elements OR 105. A single value of P1P21..the formation of eigenvaluesiand the sign of the end of computing the number of elements 90, 91, 92 and 93, registers 86, nodes comparison 83 and vychitala 79, specified by the value n (n= ).

The values of n also go through the entrance 159 to the input of the decoder 152 computing nodes 50 (51) of the processing unit 1. After decoding the values of n, with the corresponding output of the decoder 152 a single value of xiopen items AND 140i(i = ) and the information from the output register 128ithrough the elements AND 140iand OR 141 available at the output 162 of the computing node.

Thus, by setting specific values of n in the device implements the possibility of computing the eigenvalues of the matrix (n n) for various n L.

Consider the operation of the device for the particular case n = 3 and R = 1. Let the fifteenth cycle of the device detected the failure processing unit 13. In this case, the organization of the input and output data streams, the contents of the triggers, registers and generated values on the outputs of the processing units 11, 12, 13, 14, 15and 16(where 16- back processing unit), are given in table. 2.

At stage t = 15 detected failure of the unit 13at stage t = 16 held lock and abolene the further processing), at stage t = 17 happen blocking and reset block 11at stage t = 18 occurs zeroing unit 2 I / o, at step t = 19 occurs the device is restarted (on unit 2 I / o initiated by the filing of appropriate value) unlock 11, 12, 14and 15.

One of the possible recovery algorithms computing process after detection of the failure block 1jinvolves the following steps:

Cycle i: the fixing block 1jwith the detected failure;

cycle i+1: block block 1jthe reading unit 1j-1, reset and lock blocks 1j-1, 1j+1, 1j+2, ..., 12n-1;

cycle i+2: reading unit 1j-2, reset and lock block 1j-2;

cycle i+3: read block 1j-3, reset and lock block 1j-3;

.................................................. ..................

cycle i+k: reading unit 1j-k, reset and lock block 1j-k;

cycle i + j: zeroing unit 2 I / o;

cycle i + j + 1: restart the device, unlock blocks 11, 12, ..., 1j-1, 1j+1, ..., 12n-1.

Upon detection of a failure of the unit 2 I / o the number of clock cycles), required to restart the device by means of external control, the time reinit line will be (j+tn) cycles.

Due to technological crystal structure of IP, the health state or failure of its various fractions are interrelated. The degree of connection between the failures of different shares the IP is measured by the correlation coefficient, the value of which is greater, the higher the level and the degree of integration of IP. The presence of at least 16-bit combinational nodes (multiplier, site, finding the reciprocal of a number, adder, registers) determine the degree of integration and the level of technology, sufficient for the manifestation of a high degree of correlation of failures. When the control duplication of computational nodes need to bounce these nodes were independent. For this purpose, the nodes 31 and 32 I / o unit 2 I / o nodes 50 and 51 of the processing unit 1 were implemented on different crystals of IP. Similarly, on the basis of the correlation of failures inside the crystal IP, you need to excess or redundant processing units 1 did not appear on some crystals of IP together with the workers.

Technical and economic effect of the proposed device is following the time and lock the issuance of erroneous information upon detection of the faulty processing unit. The device implements the most complete hardware control, focused on the detection of all types of failures, the time control is comparable with a clock period. Further, we assume that the failure rate of block I / o is comparable to the failure rate of the processing unit in accordance with the volume of devices block I / o and processing unit). Reliability operation processing unit or block I / o device will be determined as

Df(t)=PCR(t)+P0,0(t)

where PCR(t) is the probability of correct operation of the unit;

Po(t) is the probability of correct operation of the unit in the issuance of a sign of failure on his way out.

For consideration systolic devices

PCR(t) = P2yC(t)

Po(t)=2Puz(t)(1-Puz(t)

where Puz(t) is the probability of the unit.

Therefore, the reliability of operation can be estimated as

Df= (2Puz(t)-P2yC(t)2n.

Puz(t)=0,999, n = 5, Df= 0,999989, and Puz(t) = 0,9999 and above Dfalmost equal to 1.

The recovery time computing about the SUB>OTC2n-1, mOTC- the number of the failed processing unit in the line device.

1. Device for computing eigenvalues of (nn) matrix containing 2n - 1 processing units, each of which includes a first computing node, and a clock input devices are connected to the clock inputs of all processing units, information inputs of the first group of devices connected to the information inputs of the first groups of all processing units, the first control input device connected to the first control inputs of all processing units, the outputs of the first group of the i-th processing unit (where i = 1,..., 2n-1) are connected respectively to the information inputs of the second group (i+1)-th processing unit, characterized in that the device contains L processing units (where L = 2n + R, R is the number of redundant processing units), the block I / o, L combinational adders, (L-1) th register, L nodes comparison, (L-1)-th group of items OR L groups of elements And the element OR NOT, and the member OR, with the clock input devices are connected to the clock inputs of the processing units with 2n-th to L-th, the clock inputs of the block I / o and inputs the read/write all registers, the first and second outputs of the i-th processing unit connected respectively to the second the processing (where j = 2n-1, 1..., L-1) are connected respectively to the information inputs of the second group, the second and third control inputs (j+1)-th processing unit, the information inputs of the second group, the second and third control inputs connected respectively to the information inputs of the first group, the first and second control inputs of the block I / o, the outputs of the first group, the first and second outputs of which are connected respectively to the information inputs of the second group, the second and third control inputs of the first processing unit, the outputs of the second group which is connected to information inputs of the second group block I / o, the information inputs of the third group of the k-th processing unit (where k = 1,..., L) are connected respectively to the outputs of the elements And To the second group, the first inputs of elements And l-th group (where l = 1, ..., L-1) are connected respectively to the outputs of the second group (l+1)-th processing unit, the input elements And the L-th group are connected respectively to the information inputs of the third group of devices, the control inputs of the first group which are connected respectively to the control inputs of the first group of the first processing unit, the outputs of the third group of the k-th processing unit connected to the inputs of the group of k-Combi and the inputs of the first group of l-th node of the comparison, the outputs of the L-th combinational adder connected to the inputs of the first group of L-th node of the comparison, the inverse and the direct outputs of the k-th node comparison connected respectively to the second inputs of elements And k-th group and the k-th input element OR NOT, the output of which is connected to the first input member OR the output of which is connected to the output of the sign of failure, the outputs of the l-th register are connected respectively to the first inputs of the elements OR l-th group, the outputs of which are connected respectively to the control inputs of the first group (l+1)-th processing unit, the outputs of the fourth group of l-th processing unit connected respectively to the second inputs of elements OR l-th group, the control inputs of the second group of devices connected to the control inputs of the group block I / o and control inputs of the second groups of all processing units, the control inputs of the third group of devices are connected to the inputs of the second group all nodes comparison, the input set to the initial state, the input accuracy and output characteristic of the final decision tasks connected respectively to the input set to the initial state, the information inputs of the third group and the third output block I / o, the fourth output of which is connected to the second input Di, k-th input set of the second group of devices connected to the second input set of the k-th processing unit, the k-th input set of the third group of devices are connected to the third input set of the k-th processing unit, the k-th entry lock device connected to the input block of the k-th processing unit, the outputs of the groups second (L+1)-th and outputs (L+2)-th group block I / o connected respectively to the outputs of the and output characteristic of the device, each processing unit further comprises a second computing node, node comparison, the trigger, the first, second and third nodes of elements And node elements OR element And, moreover, the information inputs of the first group, the third group, the control inputs of the first group, the second control input and a third control input connected respectively to the inputs of the groups of the first and second nodes of the elements And the outputs of the first group of the first node elements And are connected to the inputs of the first group of node elements OR whose outputs are connected respectively to the outputs of the first group, second group, first and second outputs of the processing unit, the outputs of the first group to the second node elements And connected respectively to the information inputs of the first group, second group, Petrou group, the first and second outputs of the first computing node connected to the inputs of the first group of node comparisons and input group of the third node elements And whose outputs are connected to inputs of the second group of node elements OR, the outputs of the first group, second group, the first and second outputs of the second computing node connected to the inputs of the second node group comparison, the output of which is connected to the information input trigger, the output of which is connected to the input of the third node elements And the input of the second node elements And the inverse input of the first node and third elements And the output of the processing unit, the outputs of the second groups of the first and second computing nodes connected respectively to the outputs of the fourth group and the third group unit, the information inputs of the second group, the first control input, control inputs of the second group and the first input set which are connected respectively to the information inputs of the third group, the third control inputs, the control inputs of the groups and the inputs of the installation to its original state of the first and second computing nodes, the second and third inputs of the unit are connected respectively to the inputs setup to zero and the trigger unit, entry lock and a clock input unit ucen to the clock inputs of the first and second computing nodes and the input of the synchronization trigger, and the block I / o contains the first and second nodes of the I / o node comparison, the trigger and the group of items, and informational inputs of the first group, second group, third group, the first control input, a second control input, control inputs of the group and the input set to the initial state of the block I / o are connected respectively to the information inputs of the first, second, third group, the first, second, third control inputs, the control inputs of the group and the input set to the initial state of the first and second nodes, I / o, clock input block I / o is connected to the clock inputs of the first and second nodes, I / o and synchronization input trigger, the outputs of the first group, the group output from the second (L + 1)-th and outputs (L + 2)-th group, the first, second and third outputs of the first host I / o connected respectively to the inputs of the first node group comparison and the first inputs of elements And groups whose outputs are connected respectively to the outputs of the first group, the outputs of the groups second (L + 1)-th, outputs (L + 2)-th group, the first, second and third outputs of the block I / o, the outputs of the first, second and third group, the first, second and third outputs of the second host I / o is connected to wheny the outputs of which are connected respectively to the second inputs of elements and groups, And the fourth output unit I / o.

2. The device under item 1, characterized in that each node I / o contains L Raman vychitala, the node determining the reciprocal of a number, two divider L nodes comparison, two registers, two groups of registers, three trigger (5L + 4) group elements And three groups of members OR six members, two elements OR decoder, and information inputs of the first group of node I / o is connected to information inputs of the first register, the outputs of which are connected to first inputs of elements And the first group, the outputs are connected to first inputs of the elements OR of the first group, the outputs of which are connected to the outputs of the first group of host I / o information inputs of the second group which is connected to information inputs of the second register, the direct outputs of which are connected to information inputs of the first register of the first group of information inputs of the node computing the reciprocal and the first inputs of elements And the second group, the outputs of which are connected respectively to the second inputs of the elements OR of the first group, the outputs of the compute node reciprocal and inverse outputs of the second register are connected respectively to the first inputs of elements And the third group and the first entry is tov OR the first group, the outputs of the b-th register of the first group (where b = 1,..., L) are connected to first inputs of elements And (4 + b)-th group, the first inputs of elements AND (4 + 2L + b)-th group and outputs (2 + b)-th group of node I / o, the outputs of the elements AND (4 + 2L + b)-th group are connected respectively to the inputs of the elements OR the second group, the output of which is connected to information inputs of the first register of the second group, the outputs of the elements And (4 + b)-th group are connected to the inputs of the first group of b-th combination vicites whose outputs are connected respectively to the information inputs of the first group of b-th node of the comparison, the output of which is connected to the first input element AND (4 + 3L + b)-th group, the output of the b-th element AND the (4 + 3L + b)-th group is connected to the b-inputs of elements And (4 + 4L + b)-th group, the output of which is connected to the b-th input of the second element OR the output of which is connected to the third output node I / o, data inputs of the third group which is connected to information inputs of the second group all nodes of the comparison, outputs the l-th register of the second group (where l = 1, ..., L-1) are connected to information inputs (j + l)-th register of the second group and the first inputs of elements And (4 + L + l)-th group, the outputs of the L-th register of the second group are connected to first inputs of elements AND (4 + 2L) th grassie inputs of node I / o connected respectively to the information inputs of the first and second triggers, direct the output of the first flip-flop connected to the first inputs of the first element And the fourth element And the first output node I / o, the inverse output of the first flip-flop connected to the first inputs of the second and third elements And direct the output of the second trigger is connected to the second inputs of the first element And the third element and the second output node of the input-output inverted output of the second trigger is connected to the second inputs of the second and fourth elements And the control inputs of the group of node I / o is connected to the inputs of the decoder, a clock input node of the input-output connected to the counting inputs of the first and second dividers, the first inputs of the fifth and sixth elements And inputs the synchronization triggers from the first to the third and inputs the read/write of the first and second registers, the output of the fifth element And connected to the inputs of the read/write registers of the first and second groups, the output of the sixth element And connected to the first input of the first element OR the output of which is connected to the second input of the fifth element And the outputs of the first and second dividers respectively connected to the second input of the first element OR the control input of the third trigger, the output of which is connected to the second input of the sixth element And whoi (4 + L + g)th g th input elements OR g-th to the first and the (j + 1)-th input element And (4 + 4L + g)-th group, the output of the g-th element OR is connected to the second inputs of g-x elements, And (4 + g)-th group, (4 + L + g)-th group and (4 + 3L + g)-th group, the L-th output of the decoder is connected to the second inputs of the L-th element And the (4 + L)-th group, (4 + 2L)-th group and (4 + 4L)-th group, the input set to the initial state of node I / o is connected to the inputs setup to zero all flip-flops, registers and dividers node I / o, output b-th element OR the second group is connected to b-m outputs (3 + L)-th group of node I / o, L-th output of which is connected to the L-th output of the decoder.

3. The device according to p. 1, wherein each compute node contains combinational adder combinational multiplier, four register group registers, three trigger, L + 7 member groups And three groups of elements, OR two elements, OR, the six elements And the decoder, and information inputs of the first group of compute nodes connected to information inputs of the first register, the outputs of which are connected to information inputs of the first group of combinational multiplier and to the first inputs of elements And the first group, the outputs of which are connected to the outputs of the first group of compute nodes, the information inputs of the second group which is connected to the information is umutara and the first inputs of elements And the second group, the outputs are connected to first inputs of the elements OR of the first group, the outputs of which are connected to information inputs of the second group of combinational multiplier, the outputs of which are connected to information inputs of the second group of combinational adder, the information input of the third register and the first input element And the third group, the outputs are connected to first inputs of the elements OR the second group, the outputs of which are connected to information inputs of the first register group of information inputs of the third group of the computing node connected to the first input element And the fourth group of information inputs of the fourth register, the outputs of which are connected to first inputs of elements And the fifth group, the outputs are connected to second inputs of the elements OR of the first group, the outputs of the combinational adder connected to the first input element And the sixth group, the outputs of which are connected to second inputs of the elements OR the second group, the inputs of the third group which are connected to the outputs of the elements of the fourth group, the outputs of the third register connected to the first inputs of the And elements of the seventh group, the outputs of which are connected to the third inputs of the elements OR first group of outputs l-g is l + 1)-th register group, the outputs of the L-th register group are connected to first inputs of elements And (7 + L)-th group, the outputs of the elements And groups with eight (7 + L)-th connected respectively to the inputs of the elements OR the third group, the outputs of which are connected to the outputs of the second group of compute node, the first control input of which is connected to the information input of the first trigger and the first (inverted) input of the first element And the second control input of the computing node is connected to the information input of the second trigger and the second input of the first element And the third control input of the computing node is connected to the information input of the third trigger, and a third input of the first element And direct the output of the first flip-flop connected to the first inputs of the second and third elements And the first output of the computing node, the inverse output of the first flip-flop connected to the first inputs of the fourth and fifth elements And direct the output of the second trigger is connected to the second inputs of the third and fourth elements And the second output of the computing node, an inverse input of the second trigger is connected to the second inputs of the second and fifth elements And an inverse input of the third trigger is connected to the third inputs of the second and fourth elements, And otwartego registers, the first input of the sixth element And the input synchronization triggers from the first to the third input set to the initial state of the computing node connected to the inputs installed in the zero state of all registers and triggers the control inputs of the group of compute nodes connected to the inputs of the decoder, the g-th output of which (where g = 1, ..., L) is connected to the second inputs of elements And (7 + g)-th group, the output of the first element And connected to the second inputs of the elements of the fourth group, the output of the second element And is connected to the second inputs of elements And the sixth and seventh groups and the first input of the first element OR the output of which is connected to the second inputs of elements And the first group, the output of the third element And is connected to the third inputs of the And elements of the sixth group, the second input of the first element OR the first input of the second element OR the output of which is connected to the second inputs of elements And the fifth group, the fourth output element And is connected to the second outputs of elements And the second and third groups, the third input of the first element OR the second input of the sixth element, And the output of which is connected to the input of the read/write of the third register, the output of the fifth element And connected to the fourth inputs of the elements of the

 

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FIELD: computer science.

SUBSTANCE: device has block of registers of first memory, block of registers of second memory, block for controlling reading of columns, block for controlling reading of rows, block for controlling reverse recording; according to second variant, device has same elements excluding block for controlling reverse recording. Third variant of device is different from second variant by absence of block for controlling reading of columns, and fourth variant of device is different from second one by absence of block for controlling reading of rows.

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4 cl, 9 dwg

FIELD: computer science, possible use for engineering devices meant for processing numeric information arrays, in particular, for permutation of rows of two-dimensional array (matrix) stored in memory of computing device.

SUBSTANCE: device contains matrix of unary first memory registers and matrix of unary registers of second memory, which are identical to each other. Between them a commutator is positioned. Unary memory registers, positioned conditionally in one row, are connected between each other as shifting row registers. Commutator on basis of law given externally connects output of shifting register of first memory, corresponding to i-numbered row, to input of shifting register of second memory, corresponding to j-numbered row in second memory. After sending a packet of shifting pulses to shifting input of i-numbered shifting register of first memory, information from it moves to j-numbered shifting register of second memory. Therefore, transfer of i-numbered row to j-numbered position in new array occurs. Transfer of rows can be realized row-wise, or simultaneously for all, while structure of commutator is different for different cases.

EFFECT: realization of given permutation of rows and/or columns of two-dimensional array.

7 cl, 10 dwg, 1 tbl

FIELD: computer engineering, possible use for parallel computation by digit cuts of sums of paired productions of complex numbers, may be used for solving problems of digital signals processing, solving problems of spectral analysis and hydro-location, automatic control systems.

SUBSTANCE: device contains adder-subtracter, two blocks for computing sums of products, each one of which comprises multiplier registers, multiplicand registers, matrix multiplexers, transformer of equilibrium codes to positional codes, matrix adders.

EFFECT: expanded functional capabilities, increased speed of operation.

5 dwg

FIELD: information technology.

SUBSTANCE: device has a matrix comprising m rows and n columns of a homogeneous medium, n blocks for counting units, unit for finding the maximum, adders, a memory unit, a lower-bound estimate search unit which has a pulse generator, element selection multiplexers, row selection decoder, incidental vertex decoders, fixed arc decoders, row and column counters, fixed arc counters, incidental vertex counters, mode triggers, group of m triggers, group of m inhibit circuit units, matrix (i.j) (i=1.2,…, m, j=1.2,…,n) of fixed arc counters, matrix (i.j) (i=1.2,…, m, j=1.2,…,n) of OR elements, matrices (i.j) (i=1.2,…,m, j=1.2,…,n) of AND elements, an OR element, inverters, AND elements, group of m OR elements.

EFFECT: broader functional capabilities.

2 dwg

FIELD: radio engineering.

SUBSTANCE: invention applies new sequence of interrelated actions, including procedure of vector disturbance in combination of array basis reduction and multi-alternative quantisation. Invention makes it possible to simultaneously service group of several subscriber stations in one and the same physical channel. Invention advantage is possibility of quite simple realisation in transmitter and especially simple realisation in receiver of subscriber station. Invention advantage is possibility of realisation with only one receiving antenna available in each of subscriber stations.

EFFECT: increased throughput capacity of communication channel.

6 cl, 7 dwg

FIELD: information technologies.

SUBSTANCE: system to carry out dot product operation includes the following: the first memory device designed to store instruction of a dot product of "single instruction - multiple data flows" type (SIMD); a processor connected to the first memory device to execute instruction of SIMD dot product, in which instructions of SIMD dot product include an indicator of source operand, an indicator of target operand, at least one indicator of direct value, at the same time the direct value indicator includes multiple control bits.

EFFECT: increased efficiency of processor.

28 cl, 18 dwg

FIELD: information technology.

SUBSTANCE: apparatus has an inverting unit, comprising shift code generating circuits, shift circuits, circuits for generating the code for setting the adder-subtractor operating mode and n normalising units, each having shift circuits and adder-subtractors.

EFFECT: faster operation.

1 dwg

FIELD: information technology.

SUBSTANCE: device has a matrix of homogeneous computing environment cells, having m-1 rows and m-1 columns, where m is the number of bits of the input signal, wherein a cell contains an OR element, an AND element and two flip-flops.

EFFECT: high reliability of a homogeneous computing environment owing to fewer connections between homogeneous computing environment cells and faster operation owing to use of faster homogeneous computing environment cells.

3 dwg, 1 tbl

FIELD: information technology.

SUBSTANCE: device has first registers 1ij (i=1,…,m, j=l,…,n), second multiplier units 2ij (i=1,…,m, j=1,…,n), second registers 3j (j=1,…,n), first adders 4i (i=1,…,m), second adders 5j (i=1,…,m), first multiplier units 6i (i=1,…,m), fourth adders 7i (i=1,…,m), 9j (j=1,…,n), first delay elements 10j (j=1,…,n), AND elements 11j (j=1,…,n), a fifth adder 12, a third multiplier unit 13, a maximum code selection circuit 14, a third register 15, a sixth adder 16, a second delay element 17, an input 18, outputs 19 and 20.

EFFECT: faster operation of the device for simulating the decision making process in conditions of uncertainty.

1 dwg

FIELD: information technology.

SUBSTANCE: invention is meant for use in high-performance computer systems, particularly digital signal processing systems operating in real time, fast process control systems, in personal computers as a means of enhancing performance, realised as a subcircuit in an arithmetic processor or as part of a separate device (special-purpose processor). The apparatus has n normalisation units, each having shift and adder-subtractor circuits and a radical inversion unit having shift circuits, shift code generating circuits, circuits for generating the code for setting the operating mode of adders-subtractors, double adders-subtractors.

EFFECT: high rate of normalising an n-dimensional vector.

1 dwg

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