The imaging device

 

(57) Abstract:

The invention relates to the processing device processing and formation of the images. The device includes a storage medium in which recorded video data in the image background. The device also includes a storage means for storing color data of the image elements and processor means for processing the image. When you rotate, enlarge or reduce the original image are calculated specifies the addressing scheme of the data processor means of the image background. 6 C.p. f-crystals, 19 ill. .

This invention relates to a processor device for processing and generating video images, intended for use in the TV's setup (console) or similar device and allows you to play on the TV screen as a moving image and a background image.

The known device, enabling rotation of the moving image: see , in particular, Japanese patent publication N 45225/1980 and laying out the invention in departmental Bulletin of the Patent office of Japan N 113529/1976 (duplicate of U.S. patent N 4026555). In turn, know what dostavlenny in Fig. 17, includes videoshomemade device VPAM 102 with a random sample of data (hereinafter referred to in the Russian text - vtupv) containing ordinary resident RAM-memory (NVR) and the CPU CPV 103 (hereinafter CPU) connected to the processor unit 101 of the image processing. Operational (main) storage device 104 along with these background images and moving images remembers the service control data used for controlled playback of the image data; it UPP connected to the Central processor 103. The image data recorded in the operational ROMs 104, is transmitted in vtupv 102 (VPAM 102) via the image processor 101. In accordance with the control data from the CPU 103 (CPU 103), the image processor 101 reads data from videotaping device 102 and displays the data on the display device 105 in the form of a video signal on which the device 105 in accordance with the specified data is generated, the video plays. Address vtupv 102 comply with the provisions of the horizontal and vertical directions of the image formed on the display (screen) 105. The above data of the moving image or the image background (in some vtupv 102.

When working analyzed known televizionnaya setup when turned, increase or decrease the size of the corresponding image background and his playing on the TV screen 105 in the period personnel quenching pulse on image data, the CPU 103 (CPU 103) performs the calculation in accordance with the position in the horizontal direction (in the following text "the horizontal position, horizontal position) and the position in the vertical direction (in the following text - "the vertical position, vertical position) on the display screen (TV) 105 operational data on the original source image background stored in vtupv 102, - horizontal and vertical position (when is rotate, enlarge or reduce an image background) and writes the data on the initial image background and addresses of the video memory 102 (RAM 102) corresponding to the calculated horizontal and vertical positions. After that, the image processor 101 converts the data recorded in vtupv 102, a video signal and outputs it to the device 105 display in the line scan periods.

which of the devices described in the layout of the patent, published in the departmental Bulletin of the Patent office of Japan for N 172088/1985 (duplicate of U.S. patent N 4754270).

It is noteworthy that the technical means described in the aforementioned Japanese publication of patent N 45225/1980 and laying out in the Bulletin N 113529/1976 cannot be used to rotate the image background.

Further, it should be said that the prototype processor device shown in Fig. 17, has the following disadvantage: when rotated, enlarged or reduced image background and it plays a Central processor 103 (CPU 103) must calculate the horizontal and vertical position. As a result, the performance of this processor is reduced so that it is not capable of any other video treatment, and the process of processing data in turn, increase or decrease image background stretches over a relatively long time.

In addition, when carrying out the above-mentioned information processing in turn, increase or decrease image background data on this image, recorded in vtupv 102, are overwritten. Of course, it is not possible to save the data on the first is whether the reduction of such images. It is appropriate to cite the following example: when multiple sequential rotation of the original image background with angular step 30oa full turn of 360oover time, calculation errors on the relevant step-by-step turning, being summarized in the course, become so large that the playback picture background on coordinate vzaimopoleznoe his plots will differ significantly from the original image, and the shape of the reproduced image is different from the specified form of the original image. Thus, the current processor is a processing technique of videosurgery, not ensuring conservation of the original image background (videophonograms) both shape and position, is inefficient and requires fundamental improvement.

In conclusion, we should indicate that the device described in the display Japanese patent Gazette of the Patent office of Japan N 172088/1985 has the fundamental disadvantage that when rotating the image background may not be enlarged or reduced in scale, however, the processing of data by turning and increase or decrease the image is not m seukasoum the main aim of the present invention is to develop videoprocessing device, able to play in the processing of the image background with the same shape as that of the original image signalosome, without any deformation distortion before or after the rotation.

Another object of the invention is to create videoprocessing device capable of processing video information about and/or increase or decrease image background with high performance without overloading the CPU, reproducing the original image without any distortion.

Another purpose of this invention is to develop a device capable of processing information to increase or decrease image background while implementation of the rotation.

The present invention is characterized by the presence in its structure the following functionalities: storage device, recording video image background in the address corresponding to the playback position of the specified image to the information processing at the turn; Executive means owning on the basis of the control data generated for rotary processing ingenia background after the implementation of information processing in his turn; reading means for retrieving the video data recorded in the address storage device, zadeistvovany mentioned actuating means; and a generator that generates a video signal based on the video data read mentioned reading means.

In another embodiment, the composition of the proposed videoprocessing device may include a storage device for recording video data on the image background in the address corresponding to the position on the screen of the specified image before performing data processing on the turn and increase or decrease image; actuating means for actuating in accordance with the control data used for processing the information on the rotation and increase or decrease the specified image address storage device-drive corresponding to the playback position of a background image background after the implementation of at least one of the above types of data processing for converting image; a reading means for sampling the video data, recorded in the address storage device, zadeistvovany mentioned actuating means; a generator for forming bitprocessor system storage device-drive writes before carrying out data processing according to the rotation (and/or increase or decrease) of the video image in the address, corresponding to the position of the image on the screen before processing the rotation (and/or increasing and decreasing scale).

Then in the process of turning (and/or increase or decrease) of the image of the Executive, the tool uses the address of the storage device corresponding to the position on the screen image after the processing of the information on the rotation (and/or increase or decrease), in accordance with the control data used for the specified processing, after which the reading means reads the video data stored at the address of the storage device, which is operated actuating means, the generator based on the video data read mentioned reading means, generates a corresponding signal. Thus, the video signal is formed in accordance with the video data stored in the memory device during the implementation of at least one of the operations of information processing in turn, increase or decrease of the image.

This invention allows you to play with turning the image background is exactly the same shape as the original, the reference of formationa machining by turning and/or increase or decrease the image background is carried out at high speed without CPU overload and without distortion of the original image background.

The above and other objectives, the strengths and distinctive features of the present invention more fully and more clearly revealed and illustrated in the detailed description being offered below. This description is accompanied by explanatory graphics, a summary of which is analyzed directly below.

In Fig. 1 shows a block diagram of the television's setup (device), is solved in accordance with one of the embodiments of the present invention.

In Fig. 2 presents a diagram showing the relationship between the workspace videoshomemade device random access vtupv (VPAM) and the playback area of the image background on the screen according to this image, recorded in vtupv 7 (VPAM 7).

In Fig. 3 is a diagram showing the bit configuration of the coordinate "X" and "Y" to determine the position of the data area vtupv shown in Fig. 2.

In Fig. 4 is a diagram representing a map of posting information and videoshomemade device vtupv (VPAM).

In Fig. 5 is a diagram illustrating conditions (order) recording and storing video data on the colored isoa bit configuration address and data in the iconic image area reverse background and square tidnevnogo image in vtupv, included in the circuit of Fig. 1.

In Fig. 7 shows a graph explaining the principle of processing data by turning and increase or decrease the image background.

In Fig. 8, 9 shows the structural and functional diagram of a control device of the sample address according to the image background.

In Fig. 10 to 12 are shown timing diagrams explaining the principle of operation of the above-mentioned control device (circuit) fetch address of a video image background.

In Fig. 13 is a diagram illustrating an example of playback of the original (the original) image background, while in Fig. 14 to 18 of this scheme, showing the same image, but enlarged, rotated, reduced or transformed together. And, finally, in Fig. 19 depicts a block diagram telegraphy setup (console) known standard type.

Although the preferred embodiment of the invention considered in relation to the video processor for televizionnaya machine, it should be remembered that, in principle, the invention is applicable to processors for various purposes, in particular for personalnovel scan etc.

In Fig. 1 shows a block diagram telegrafico apparatus, which is one of the variants of the present invention.

Before proceeding to the analysis of this scheme, it is advisable to say a few words about the display device (the display) used in this case. Usually, the display device in telegraphic apparatus using a raster-razvedochny cathode ray type display visual display device with the input signals RGB (PCB monitor; PCB - red-green-blue) or a standard television receiver, if the screen is divided into 256 256 pixels (picture elements). However, due to the fact that the image cannot accurately be reproduced on sites a few lines from the top and bottom of the screen, as determined by the curvature of the surface of the cathode ray tube, in fact, to play vertically are used 224 points. Therefore, if a single character, which is the minimal element of the background (and/or moving images), consists of 8 x 8 pixels, then on the screen at the same time can be played 32 x 28 = 896 characters.

Consider telegrafos the device is designed in such a way that from the deposits of the plan, which cannot be changed individually playing (by the operator), and moving image, which is moved by the operator or the automated control from the Central CPU processor 2 (CPU 2), are controlled independently. This gaming machine includes a processing unit 1 of the image that displays on the CRT display 8, the video signal in the form of a combination of a background image background and the moving image reproduced at the same time on the specified display. It is appropriate here to draw attention to the fact that the TV game machine (installation, set-top box) is different in that the processing unit 1 includes a control circuit or block 24 addressing image (picture elements) background, which determines the address of the read image data to the image background from videotaping devices with arbitrary sample 7 (VPAM 7) when performing information processing by rotation and/or increase or decrease this image and just change the address being read, not touching, not changing the video data used in the implementation of rotation, increase or decrease the size of the above image.

In the scheme, pucini to the Central processor CPU 2 (CPU 2), through a variety of monitoring telegrafico apparatus through an address bus 11, the information data bus 12 and the control bus 13.

The ROM 3 is used for recording, storing program data necessary for the control in question telegraphy apparatus, the data necessary to run programs (commands), and landmark data. This storage device is, for example, in a cassette (not shown) that are inserted or extracted from telegrafico apparatus. Software data includes data for determining the type of rolling sign and/or sign background, playing on the screen, the time when the mark should be reproduced, and the coordinate position it on the screen, and overhead required to rotate, enlarge or reduce the image background, etc. In the composition data of the moving character (attributes display moving image) data is included in the horizontal position (Hc: 8 bits) used to identify the character positions in the horizontal direction, data in the vertical position (Vc: 8 bits) character code (9 bits) that identifies the type of character code of the color palette (3 bits), permit number (2 bits) to denote the reverse of the sign of the data (2 bits) to indicate the priority of the moving image relative to the image background. As the data for each character image background are symbolic code (8 bits) to identify the type of sign; data on the chromaticity of each of picture elements constituting a character, and so on, the Set of characters background is displayed in combination, reproducing the image background (stationary or slow-moving human image); in turn, many moving characters when displaying the reproduced moving image. The image background and the moving image reproduced on the screen combined. Characterized by the fact that the data used to reproduce any image background, is the character code of the background corresponding to each address generated image and determines thus, some of the characters background should be recorded in the particular address from the set of addresses in the vertical and horizontal directions in sagastume region 40 vtupv, and thus reproduced on the screen in a predetermined position (coordinates) corresponding to the address used.

NVR 4 is used as a working area above the Central processor CPU 2. Keypad 4 Hipolito part videoprocessing unit 1 includes an interface 21 of the CPU. Interface (interface unit) 21 is connected to the CPU 2 (CPU 2) through an address bus 11, the information bus 12 and the control bus 13. Output to the unit 1 connect the generator 6 of the reference signal videoshomemade device derived sample vtupv 7 (VPAM 7), consisting of two NVR (7a, 7b), and a CRT display (CRT) 8 type of visual display units 8A with RGB input signals or standard television receiver 8b.

Unit 1, the video processing functions under the control of the Central processor CPU 2 and is used for broadcast video moving image and a still image background into the memory vtupv 7 during the period damping reverse vertical scan or force sinhronizovano with the read image data of moving images and/or image background, recorded in vtupv 7, without changing or retrieving video data obtained as a result of the operations of the information processing by turn, increase or decrease the image that is the hallmark of this invention. In the end, the processing unit 1 converts the video data into RGB video signal (trehtsvetkovaya signal) and/or color signal in syslocal includes an interface 21 of the Central processor; the control unit 22 addressing the moving image; block 24 addressing image background; interface 27 VRAM vtupv; generator 28 color signal. All these means connected to the interface 21 of the Central processor unit CPU 2 via the data bus 14. The address bus 15 is connected to the block addressing 22 of the moving image; concurrently, the address bus 15 and an information bus 16 is connected to the control unit 24 addressing the image background and the interface 27 vtupv. The address bus 15 and an information bus 16 consist of channels or lines 15a, 15b and 16a, 16b, corresponding to two videoshomemade devices 7a and 7b. To the data bus 16 connected together unit 23 of the data processing of the moving video image and the block 25 of the data processing on the image background. Rendering information on a moving image is carried out using a circuit (block) addressing 22 and block 23 of the data processing of such images; in turn, the information processing on the video image background by the management scheme 24 addressing this image and the block 25 processing image data back to the background. The output unit 23 of the data processing on the moving image and the block 25 data trehtsvetkovaya RGB the signal generator 28 chroma signal; this signal comes directly from the RGB monitor 8A and simultaneously converted into a full color video NTSC format NTSC - encoder 29, the output 9 of which NTSC video signal is supplied to a conventional television receiver 8b.

In addition, the processing unit 1 includes a generator 30 clock signal and HV counter 31. The generator 30 generates various Chronologie signals in accordance with clock pulses with a frequency of 21, 417 MHz synchronization signal vertically and a sync signal horizontal, which come from the output of the generator 6 of the reference signal. HV counter 31 counts the number of data Hcand Ucto identify provisions playback horizontally and vertically within the zone display 41 on the display screen shown in the diagram of Fig. 2; this operation is carried out in accordance with a clock signal, a synchronization signal vertically and a sync signal horizontal, coming from the generator 6 reference signal.

In Fig. 2 presents a diagram illustrating the relationship between the display area on the screen of the CRT display 8, and a data recording area on the image background in video memory In which INIC, formed by the 32 characters in the horizontal direction (width: x) and 28 marks vertically (length y). On the other hand, if the region 40 write (store) data in the image background (hereinafter referred to as the "region vtupv") does not contain such data on the part which is not visible (not visible) on the screen with reduced size, the last in black color only plays the part of izobrazheniya background, which really visible, i.e., such image being reproduced. Further, in the case when the image background when playing moves up and down, if the video on this image to be rewritten in real time, smooth movement cannot be implemented. In accordance with this region 40 vtupv should be several times larger working area (zone playback) 41 in the vertical and horizontal directions. In this embodiment, the workspace record 40 vtupv consists of 128 characters in both x, y directions (128 128 = 16384), so that the horizontal and vertical position can be identified by a 7-bit address data. Code sign the reverse of the background to be reproduced, is recorded in the address specified by the relevant coordinate is. 2 and is represented as X = O and Y = O, while the display position of the corresponding point in the area of 40 seems coordinate address function P (X, Y). Next, to determine the position 53 of the upper left end of the working zone 41 of the playback image on the display area vtupv 40 used reference distance Hpand Vp(hereinafter referred to as "offset") in the X and Y directions from the beginning of the specified area. The coordinates X and Y are the corresponding address data XC and YC (7 bits each) that indicates the character position in the field 40 vtupv, and X and Y (3 bits each) that identifies the position of a point in one character 52 (see Fig. 3).

The video memory 7 consists of two working sections vtupv 7a and 7b (RAM 7a and 7b) with the same capacity (see Fig. 4). Each of vtupv 7a and 7b has the addresses from 0 to 32K and can remember each address 8-bit data.

Storage device - steps 7a and 7b is divided into area 51 to 54 for each 16K. Region 51 and 52, having addresses 0-16K, will be used to log data associated with the image of the background; in turn, the area 53 and 54, having addresses (16K + 1) - 32K are used for recording data relating to a moving image (i.e., multiple mobile-sign data is it background). More specifically, the area 51 in the storage stage vtupv 7a is used as a significant area for recording data color a maximum of 256 characters image background. As shown in Fig 5, a single character is represented by the number of bits of information, corresponding to 8 x 8 (length x width) points and includes an 8-bit color data for each pixel. Thus one sign has a memory capacity of 512 bits (64 bytes). For each sign given symbolic code. Section 52 in memory vtupv 7b is used to write a certain number of bits corresponding to 128 x 128 (length x width) of the cell region 40 vtupv shown in Fig. 2, and serves as a zone display, used for writing character image background in the address determined by coordinates in the vertical and horizontal directions. In Fig. 6 as an example, the formats of data stored in area 51 and 52 of the considered memory.

Considering the next Fig. 1 - 6 together, it is necessary to characterize the performance of functional elements in the circuit of Fig. 1. When the controlling influence of the Central processor CPU 2 (CPU 2) its interface 21 transmits to the interface 27 of the storage device with arbitrary IOM accessing memory during blanking reverse vertical blanking or under the action of external commands. Simultaneously generates the locking signal LA 1 - LA 4, LA 11 LA 12 LA 14 LA 15 for transmitting control data in turn, increase or decrease the image background in the addressing scheme 24 the data of this image. Data on the sign (symbol) background and character of the moving image is recorded ahead in vtupv 7 interface 27 of this memory.

The control unit 22 of the addressing data of the moving image attribute contains the memory of this image, diagram of the intra-array detection (search) and a method of forming data addressing the moving image, detailed description of which is available in patent sources, in particular in the distribution of Japanese patent published in the departmental Bulletin of the Patent office of Japan for N 118184/1984, the author of an invention which is the applicant of the present patent application. Attribute (indicative) data 128 movable signs of the reproduced image transmitted in said attribute memory of the Central processor CPU 2 via the interface 21 and the data bus 14 and stored in the memory during the period of clearing backstop personnel (field) scan. The above scheme of detection of the implementation cycle of the horizontal scanning, an array of data recorded in the attribute memory of the moving image in the foreground. In turn, the scheme of the address data on the moving image generates a memory address vtupv 7, defines the reverse (inverted) position in zone 41 playback on the display screen, displaying the address via the address bus 15, when V-triggiani (inverted) data resulting from application of search and retrieval on the attribute data are at the level "H". On the other hand, this scheme generates a memory address vtupv 7, corresponds to the location of videosnaked data in the working area of play 41 on the display screen in the specified storage device 7 via the address bus 15 without any change when V-triggere inverted data rising to the level "L". With the arrival of information at the address storage device vtupv 7 grants scheme 23 data on a moving image via the data bus 16 data color (4 bits per pixel) of the specified moving image, recorded in a region 53 and 54 characters of this image, corresponding to the addresses issued by the shaping circuit address data to the control circuit 22 addressing the moving image. processing information on this image N-triggere inverted data (1 bit), color data for the image element (3 bits) and the priority data (2 bits) of the number of data characteristics of mobile character that is selected in the above-mentioned application of search.

Thus a 10-bit data for each point of the image includes color data read from the memory vtupv 7, H - trigger data, the data in the color image element and the priority data coming directly from the control unit 22 addressing moving perianalnogo images entered in block 23 of the data processing specified by the image carrying information on a 256-point line scan.

In the process, the processing unit 23 produces rapid entry of data on the next line scan, entered during the period damping reverse line scan, and then quickly writes 9-bit video data at each point, excluding H-triggerevent data included in the data with the inverse order relative to the order of input, when the H-data is at the level "H", with the implementation of the N-trigger processing. In turn, the specified processing unit 23 carries out the operational record 9-bit data in order of input, when Xia image is displayed on the control priority scheme 26 sinhronizovano with the horizontal sweep, and in accordance with the account details Hccoming from the HV counter 31.

During data processing on the image background control address circuit 24 calculates the current read address (16 bits) of the signed code, previously recorded at area 52 in the memory 7b and the corresponding point of the specified image, and this calculation is carried out based on the data at offset HpVpon-screen guidance and control data, which include H-triggere inverted data HF and V-trigger data VF, which are received from the CPU 2, and taking into account data account Hcand Vccoming from the HV counter 31, Susila ultimately address in memory vtupv 7b via the address bus 15b. Additionally, it should be stated that during the processing of data in turn, increase or decrease image background control address circuit 24 calculates the current read address of the symbolic code, the corresponding point of the image background; this operation is carried out based on the data offset HpVpon the screen, H-trigger data HF, V-trigger data VF and parametric data, which includes working constants A, B, C, and D used in the processing of information in turn, increase the Vccoming from the HV counter 31. The calculated address is filed in the memory 7b. The algorithm operating data turn, increase or decrease the image background will be considered somewhat below with reference to Fig.7.

Then you should specify that the control circuit 24 addressing the image data background also provides the definition of the read address sign code corresponding to one point of the specified image after performing data processing on the moving image on the screen; this computing operation is performed based on the data offset Hpand Vpon the screen, coming from the CPU 2. Simultaneously, the circuit 24 calculates a read address of the symbolic code, the corresponding point of the image background; this operation is carried out after H-trigger processing when H-triggerevent HF data are at the level "H". In addition, this scheme calculates the read (current) address symbolic name corresponding point of the image background after the implementation of the V-trigger processing when V-triggerevent data VF is at the level "H". The most important two bits of the 16-bit dannymac less priority 14 bits these data represent the positional data Xcand Yc(7 bits each) at the character position corresponding to the position of the playback image background (see Fig. 6).

Storage device vtupv 7b generates symbolic code written in the address specified by the management scheme 24 addressing data background, this scheme via data bus 15b. Accordingly, the address scheme (block) 24 generates in memory vtupv 7a via the address bus 24, the address contains the most significant priority two bits "00", the landmark eight-bit code and positional data Y (3 bits) and X (3 bits) from the position of the point corresponding to the position of the playback image background. Memory vtupv 7a reads 8-bit data of the color written to the address specified by the management addressing scheme 24, Susila them via data bus 16a in the processing unit 25 of the data processing on the image background. The processor 25 registers (latches) the incoming data of the color components of 8 bits per pixel, and then outputs them to the control scheme of priorities 26, which is implemented based on the account data, Hccoming from the output of the HV counter 31.

The management (specify) circuit 26 determines the priority between semipilosum data on the moving image, postupayuschim 25 processing of such data; establishing the priority is based on the data by priority. With the output of the circuit 26 to the generator 28 chroma signal goes high priority data selected from the total set of data on the moving image and image data of a background. For example, the control circuit 26 priorities can "give" to the output and next to the generator 28 data on the image background, containing the three most important bits of "000" and eight-bit color data, when data on priority are "00", and Vice versa: to produce an output data of a moving image of the foreground in summary format 7 bits containing 8-bit data on the color palette and 4-bit color data, when data on priority equal to "01".

The generator 28, a color signal is a color table palette-based NVR with eight-bit address and data storage on the chrominance signal which emerges from the CPU 2 into the specified table during blanking reverse the vertical scan. During the period damping reverse line scan generator 28 color signal, reads data in the chrominance signal stored in the corresponding address table color, setpause block 26 priorities and then converts the data signal color trehtsvetkovaya RGB signal (red - green - blue) with 5 bits for each color. Thus formed the RGB video signal from generator 28 on an RGB monitor (videocontrol device) 8a sinhronizovano with the account details Hcand Vccoming from the HV counter 31, and at the same time on the encoder 29 running in the system NTSC. The device 29 performs digital to analog conversion of the RGB signal for each color with the subsequent translation of the signal in full color video NTCS that comes on a standard television receiver 8b with the output terminals 9.

In Fig. 7 is a diagram explaining the principle of processing data in turn, increase or decrease the image's background carried out by the circuit 24 addressing the specified image. In Fig. 7 X-coordinate of each point in the horizontal direction on the screen of the CRT display 8, and the Y-coordinate of the point vertically. Here it is pertinent to note that the direction of the ordinate "Y" in Fig.7 back to the same coordinate in Fig.2.

Let us assume P(X1, Y1) coordinate position of the original image background before making the addressing scheme 24 rotatable about the Q(X'2, Y'2as the coordinate position of the above-mentioned image after the rotation from the initial position around the point R(X0, Y0) angle (rad). Next, we assume Q(X2, Y2) for the coordinates of the image background after its increase or decrease in relation to the position Q'(X'2, Y'2) with the corresponding scale in the X direction and with large-scale conversion in the Y-direction when using the fiducial reference point R(X0, Y0). In this case, the ratio between the coordinates of P, R and Q is expressed by the following relationship (I):

< / BR>
This ratio constants (parameters) A, B, C and D are expressed as follows:

< / BR>
In this case, when the image background is only subjected to rotary conversion without increase or decrease, = = 1 . In this case, the constants A, B, C and D are expressed as A= cos ... (6), B= sin ... (7) C= -sin ... (8) D= cos ...(9).

Further, when the rotation of the image background is not performed, but only increase or decrease its size, =0. in this case, the constants A, B, C and D are expressed by the following formulas (10) - (12):

< / BR>
In the formula (1), the coordinates P (X1, Y1) original image of a background of opasti 40 storage device vtupv (see Fig.2) and the account data, Hcand Vcthe output VH - counter 31:

X1=Hp+Hc...(13), Y1=Vp+Vc...(14).

The substitution of formulas (13, 14) in a parametric expression (1) variables, X2and Y2represented by the following formulas (15) and (16):

X2=[Xabout+(Hp-Xabout)B+VcB]+HwithA... (15)

Y2=[Yabout+(VpYabout)C+VcD]+HcC...(16)

In formulas (15) and (16) members of the HcA and HcC change from point to point on the screen, while other members (bracket expressions) do not change during a single line scan. Thus, members of the HcA and HcC should be calculated for each point during line scan. On the other hand, in this period there is no need to calculate other members. Here it is necessary to specify that the calculation of these members of the formulas (15), (16) in time is quite a challenging process, since for every point of the line scan is given very little time. On this basis, the members are calculated in the aggregate before the corresponding scan lines (pre-computing data processing). In order to calculate sostavlyajushie expressions (17) - (24), the calculation of which is the step-by-step numerical method:

E1= Hp- Xabout(17); E2= Vp- Yabout(18); E3= Xabout+ E1A (19)

E4= Yabout+ E2D (20); E5= E3- E2B (21); E6= E4- E1C (22)

E7= E5- VcB (23); E8= E6- VcD (24).

Next, you should refer to Fig. 8, 9, which shows the structural diagram of the above-mentioned setting unit 24 of addressing data on the image background. This unit evaluates the coordinates (X2, Y2during the rotation, increase or decrease the specified image on the matrix algorithm using the above equation (1), forming eventually the corresponding coordinate data representing the read (current) address section 52 of the screen and read the address of sign area 51.

In more precise formulation of the address circuit 24 includes registers FF 1 - FF 23, each of which consists of a set of D-flip-flops with a delay. Each of these registers registers (latches) the data received at its input terminal simultaneously with a signal lock (commit), extracting the relevant data on his Vinodolski, formed as a result of inverting pulse 10 MSK frequency 10,739 MHz coming from the output of the generator 30 clock. In turn, the inputs of registers FF 18 FF 20 FF 21 FF 22 FF 23 receives the inverted clock pulses generated in the reverse conversion, the conversion clock signal 5 MSK frequency 5,369 MHz generated by the generator 30.

16-bit data on the constants A, B, C and D received from the CPU 2 via the interface 21 of the CPU and the data bus 14, is locked in place properly registers FF 1 - FF 4 simultaneously with the arrival of the corresponding signals of the lock-LA 1 - LA 4. The recorded data is transmitted to the input terminals a, b, c, d switch (switching device) SW 1. This switch makes the selection of incoming data, selecting one of them and passing next to input terminals of the multiplier MPY in accordance with the XS-signals from the generator 30 to the clock (sync) signal.

Account details Hcoutput from the HV counter 31 are introduced into a logical scheme (cell) XOR XOR 1. Register FF 5 latches (registers) eight-bit data account Vccoming from the output of the HV counter 31, directing them further on the logic of EXCLUDING debetowe V-triggerevent data VF, coming from the CPU 2, with the arrival of the master clock pulse from the same Central process, passing on the XOR XOR circuit 1 and case 2 respectively H-triggerevent HF data and data of 8 bits having the same level, and V-triggerevent data VF plus 8 data bits having the same level.

The principle of the logic XOR XOR 1 and XOR 2 is discussed below. Each of these circuits contains eight exclusive OR gates. On certain inputs of gates XOR circuit 1 receives the appropriate data bits bills Hcon the other outputs corresponding data bits from the register FF 6. In turn, a part of the eight inputs of gates XOR circuit 2 receives certain data bits account Vcon the other inputs of respective bits of data (numbers) register with FF 7. Consider the valves in the composition logic XOR 1 and XOR 2 XOR perform an operation to a strict disjunction on the respective two inputs, while the output of the eight-bit data, which are received at input terminals a and b of the switch SW 2, directly or through a register FF 8. Switching device SW 2 has output terminals with 11 digits each, with the most significant priority (weight) three digits of each of the guide c and d, which receives an 11-bit data registers FF 9 FF 10, respectively.

Register FF 9 latches the least priority 11 bits (E1) 18-bit data supplied from the adder ADD, the operation begins to be realized on the leading edge of signal lock (commit) LA 9 coming from the output of the generator 30 clock. Clear data are fed to the input terminal c of the switching device SW 2. In turn, the register FF 10 latches the data with the lowest priority 11 digits (E2) of the number of 18-bit data coming from the mentioned adding devices ADD; this operation is carried out with the arrival of the leading edge of signal lock (capture) LA 10 from the output of the clock 30. Locked data is fed further to the input terminal d of the switching device SW 2. This device produces a selective sample of one of the data arriving at the input terminals a, b, c, d, based on the YS signal coming from the output of the generator 30 clock, feeding otsilindrovannoe number (this) at the input terminal b of the multiplier die.

A multiplier device die produces a multiplication of one of the data A - D, arriving at the input terminals a, on one of the data E1, E2, and Vcpost the data, representing the result of multiplying and coming next to input terminals c switching device SW 3 through the register FF 13.

Register FF 11 latches the data of the shift (shift) Hp(10 bits) in the direction "x", coming from the Central processor CPU 2 (CPU 2); this operation is carried out with the arrival of the leading edge reference pulse. From the output of register FF 11, the data arrives at the input terminal a of the switching device SW 3. In turn, the register FF 12 latches the data shift Vp(10 bits) in the direction "y", coming from the CPU 2; this operation is also carried out with the arrival of the leading edge reference pulse. From the output of register FF 12 data displayed on the input terminal b of the switch SW 3. The most important priority of 6 digits and the least significant 2 digits of each of the input terminals a and b of the switching device SW 3 grounded. The least significant priority two bits of data for each of the input terminals of the switching device SW 3, correspond to the data after the decimal point.

Switching device SW 3 selectively selects one of the data arriving at the input terminals a, b and c, in accordance with the signal AS coming from the output of the generator 30, and serves on the position in the direction "x" of the image background. This data is supplied to CPU 2 ( the snap is on the least significant eight bits of the data bus 14). Operation place (commit) data is performed with the arrival of the leading edge master clock pulse. Then full format data is 10 bits, which include the two most important priority bits "00", and clicked the data arrives at the input terminals of the switching device SW 4. In turn, the register FF 15 latches the data Yothe position of the image background in the Y direction; this data is supplied to CPU 2 (most significant two bits exceed the above data Xoa data bus 14) when the leading edge reference pulse. The output of the specified register data is received, in the amount of 10 bits, contains the eight most significant weight bits "00000000", and clicked the data; these data are fed to the input terminal b of the switching device SW 4. The most significant six bits and the least significant two digits of the input terminals a and b of the switch SW 4 is connected to the ground. The least significant two bits of data coming at each of the input terminals of the switch SW 4 represent numeric values after the decimal point.

Loka ADD, on the leading edge of the clock pulse ck 16 coming from the generator 30 clock. The output of this register is connected with the inputs c of the switching device SW 4. In turn, the register FF 17 carries the latch 18-bit data from the output of the adder ADD; this operation is initialized on the leading edge of the clock pulse ck 17 coming from the output of the generator 30 clock. The output signal of register FF 17 is applied to the input terminal d of the switching device SW 4. This device, in response to receipt of the data on its inputs a, b, c, d takes the 18-bit data EXCLUSIVE OR circuit XOR 3 upon receipt of the signal BS output synchronology generator 30. The scheme is simple disjunction XOR 3 contains 18 of EXCLUSIVE OR gates. Certain bits of data in the switching device SW 4, serves to corresponding inputs of EXCLUSIVE OR gates, while the other input receives the signal ADS from the output of the clock 30.

Next, a specific one bit signal ADS is entered on the terminal transfer adder ADD. When receiving one bit of the signal ADS to the said terminal of the adder ADD, if this signal has the level "H", the signal ADS supplied to the respective other input kingda one bit signal ADS, supplied to the terminal transfer adder ADD, has the level "L", the signal ADS supplied to other input terminals of the EXCLUSIVE OR gates in the logic circuit XOP 3, is a signal in which all 18 bits are at the level "L". Logic XOP 3 XOR functions in exactly the same way as the XOR circuit 1 and case 2. This means that the XOR scheme 3 carries out the logical operation of the strict alternation with the data received on one of the input terminals, and data coming to the other input terminals with respect to each bit (bit), giving the results of such logical operational steps to input terminals b of the summing device ADD.

The adder ADD addition produces both data received at the inputs a and b, and, in addition, adds one to the results of addition in the case where the terminal transfer signal ADS to the level "H". Next, you indicate that regardless of the results of addition of the 18-bit data is written to the registers FF 16 FF 17, the data on the least significant 11 bits are written into the registers FF 9 FF 10, 10-bit data - in registers FF 18 FF 19, and the data on the least significant eight bits in the registers FF 21.

When a signal "H" at the terminal transfer on shemitta SW 4 of their output switching device SW 3. In turn, with the advent of the mentioned terminal of the signal "L" is the inverse operation of the logical XOR circuit 3 and the operation of adding 1 to the adder ADD is not carried out. Instead, the surgery is performed adding the output of the switching device SW 3 with the output of the switching device SW 4. In the present embodiment, CPU multiplier die and the adder ADD perform repeatedly the operation of multiplication or addition of the two data (this coordinate is given by the constant or given by the results of previous operational steps) entering when switching from the switch SW 1, switch SW 4 time division and synchronization for subsequent operations calculations by formulas (17) - (24) and in the conclusion of transactions by the formulas (15) and (16) on the relevant operating cycles with the activation of its corresponding functional blocks. It is noteworthy that the information processing by turning and/or increase or decrease the image background can be performed using a common operating circuit when changing the constant data.

Register FF 18 latches entering desethylatrazine data, forming the output data Ycthe most significant seven bits as address data on the least significant seven bits of the address bus 15b with the passage of these data through the buffer amplifier vases; in addition, the register FF 20 delivers the data X on the least significant three bits in the register FF 22.

Register FF 21 latches the 8-bit data sign code received from the storage device vtupv 7b via the data bus 16b, giving them further in the form of the address data from the third to the seventh bit in the most significant digit of the address bus 15b via the buffer amplifier WA. In turn, the register FF 22 latches two trehsetovyh data Y and X , arriving at its input, producing output address data on the least significant six bits of the address bus 15a through register FF 23 and the buffer amplifier WA.

It is noteworthy that the input terminals of the two digits of the buffer amplifier BA1 connected to ground, while its output terminals (2 digits) the rows of the buffer amplifier A connected to ground, while the output terminals (2 digits) associated with the most significant two bits of the address bus 15a.

In Fig. 10-12 are shown timing diagrams (histograms) explaining the algorithm of information processing by increasing, decreasing and/or rotate the image background in the present apparatus the system. In the histogram of Fig. 10 shows the period of the horizontal and the line period quenching pulse; Fig. 11, 12 shown periods data preprocessing and processing in real-time when the counting value of H in the example is equal to 9 - 17,5.

Below when considering the dynamics in Fig.1 - 12 provides a detailed description of the data processing to increase, decrease and/or rotate the image background, i.e., the information processing, which is the essence of the claims of the invention, predetermining its novelty. Description formulated with regard to the operation of the control unit 24 of the addressing data of the image background in the implementation of the processing of one line scan in the case where the above-mentioned zadefinovat image, limited in area 41 of the display screen on the total working area (region) 40 Yoat the corner of and increases or decreases the scale in the X direction and the scale in the Y direction (see Fig.7).

With the implementation of this processing video data constants A, B, C and D calculated in advance in the CPU, the CPU 2 according to the above formulas (2) to (5) on the basis of , and , and parametric data that depend on these constants and calculated in advance in the above-mentioned processor, introduced in the trigger registers FF 1 - FF 4 from the CPU 2 via the interface 21 and the data bus 14, where and are latched. In addition, output from the CPU 2 to the inputs of trigger registers FF 1, FF 12, FF 14 FF 15 FF 6 FF 7 via the interface processor 21 and an information bus 14 receives the above data offset (shift) Hpand Vpon the screen, the data Xoand Yorepresenting the previously mentioned reference coordinates, and H-inverted data HF and V - inverted data VF image background; these registers these data are fixing to snap.

Next is the inversion of the data Hccoming from the HV counter 31; this operation is performed rectifier circuit XOR 1 XOR, the output of which stores the data on the inputs of the switching device is building from the HV counter 31 to input terminals of the switch SW 2 pass through logic XOR 1 without change, when HF data are at the level "L". Further, the data Vccoming from the HV counter 31 and snaps in the trigger register FF 5 during processing of interlaced lines, are reversed logic gate XOR XOR circuit 2 is fed to the register FF 8, which makes them a snap when V - inverted data VF is at the level "H". On the other hand, the above data Vcby acting on the trigger register FF 8, is conducted through the circuit XOR 2 XOR without any changes and are latched in the register, if V - inverted data VF have the level "L". The operation of the H - and V-triggerevent (level invert) of the image background is implemented by reversing the state of the above-mentioned logic XOR 1 and case 2. The data output from these schemes, indexed as Hcand Vcregardless, they were reversed or not (this is done to simplify the description).

Additionally, you should specify that in advance before carrying out a processing of video data in turn, increase or decrease the image background in the area 52 corresponding to the area displaying the specified image on the screen, in memory vtupv 7b (VRAM 7b) and in the sign area 51 tidnevnogo from the touch image background.

In Fig.11, 12 for clarity, the points in time when the output clock 30 you receive the master clock pulse 10 GMT with a repetition frequency of 10, 739 MHz (on the histogram instead of an apostrophe above and behind the character used the "/" character before the character), denoted as t1, t2, t3,...,t20,... In this case, during the period from time t1until t2pre-processing of data, the meaning of which is the computation of the constants E1 - E8 and which is carried out during the period damping reverse vertical scan and prior to the period of forming and outputting the video signal with videoprocessing block 1. Processing after a time t9- processing in real-time, ongoing sinhronizovano with the formation and display of the image signal, which is essentially a digital RGB signal replica signal; the contents of this processing is the computation of the coordinates Q (X2, Y2images background during his turn, increase or decrease in accordance with the parameters calculated during pre-processing, and account information Hcand Vc; conclusion and the address record area 52 of the display background in memory vtupv 7a on the basis of the sign code, read from zone 52.

In the time period from time t1and until t2both the switch SW 3 and SW 4 are connected at their input terminals a. At this time, the input terminals of a summing device ADD from the trigger register FF 1 through the switching device SW 3 receives data Hp. In turn, the b inputs of the adder ADD from the trigger FF 14 through the switch SW 4 and the logical cell XOR XOR 3 receives data Xo. When this signal ADS is at the level "H". In this mode, the logical XOR gate circuit and the adder ADD perform visitatelo data processing algorithm, discussed above, to obtain the result data in the form E1 = (Hp- Xo), which is processed further. Data E1 is fed to the input of trigger register FF 9 where are latched on the leading edge of reference signal lock LA 9, at time t2.

In the time interval from t2to t3the switching device SW 1 and SW 2 are connected at their input terminals a and c, respectively. At this time, the inputs of a multiplier die from register FF 1 through the switching device SW 1 receive data A. In turn, to the input terminals b of the same multiplier die from registration is mirua corresponding output data, received by the trigger circuit FF 13, where and are latched on the leading edge of a master clock pulse /10 MSC at time t3.

Then you should specify that during a time interval starting from time t2and before time t3both the switching device SW 3 and SW 4 skommutirovany on their input terminals b. In this mode, the input terminals a of the adder ADD from the trigger register FF 11 through the switch SW 3 is receiving data Vp. On the other hand, to the inputs b of the same accumulator from register FF 15 through the switching device SW 4 and the valve (diagram) XOR XOR 3 received data Yo. At this time, the signal ADS is "H"level. In accordance with this logic XOR 3 and summing device ADD exercise visitatelo data processing according to the above algorithm, forming the output data E2 = (Vp- Yo). Data E2 is entered in the register FF 10 and snapped it at time t3with the arrival of the leading edge reference signal lock-LA 10.

In the next time period t3- t4both the switching device SW 1 and SW 2 skommutirovany on their input terminals d. At this time, the input terminals of a multiplier die from t is noites from the trigger circuit FF 10 through the switching device SW 2 receive data E2. The multiplier die produces the multiplication data DE2, forming an output corresponding to the multiplicand. Data DE2 are entered in the register FF 13, where they are latched with the arrival of the leading edge master clock pulse /10 MSC at time t4.

Additionally, it should be stated that during the time interval t3- t4the switches SW 3 and SW 4 skommutirovany respectively to the input terminals c and a. To input terminals of a summing device ADD from the trigger circuit FF 13 through the switching device SW 3 receive data AE. Simultaneously to the inputs b of the specified accumulator from the trigger circuit FF 13 through the switching device SW 4 and the logical XOR XOR circuit 3 serves data Xabout. At this time, the signal ADS is level "L". Under this condition XOR gate circuit 3 and the adder ADD perform additive processing data according to the algorithm described earlier, forming the output data EZ = (AE1) + Xothat is fed to the input of register FF 16, where they are snapping on the leading edge of the clock pulse /16 SK at time t4.

In the next period of time t4- t5the switching device SW 1 and SW 2 are connected at their input terminals bSW 1 receive data B. In turn, to the input terminals b of the same multiplier from register FF 10 through the switching device SW 2 data come E2. The multiplier die produces a multiplication operation BE2, the output from which is entered in the register FF 13, are latched on the leading edge of the clock pulse /10 GMT received at time t5.

In the same time interval t4- t5the switching device SW 3 and SW 4 skommutirovany on their input terminals c and b, respectively. When such a network switching at the input terminals of a summing device ADD from the trigger circuit FF 13 through the switching device SW 3 receive data D2. In turn, the b inputs of the adder ADD from the trigger FF 15 through the switch SW 4 and logic gate EXCLUSIVE OR circuit XOR 3 come data Yo. At this time, the signal AD is level "L". In accordance with this scheme XOR 3 and the adder ADD perform the summation according to the algorithm described earlier, forming as a result of such processing data E4 = (D2) + Yaboutthat is fed to the input of trigger circuit FF 17, which latches the data on the leading edge of the clock pulse /17 SK at time t5.

In the next time interval t5-multiplier die from the trigger register FF 3 through the switch SW 1 is receiving data C. In turn, to the input terminals b of the same multiplier from the trigger register FF 9 through the switching device SW 2 data is input E1. The multiplier performs the multiplication operation data CE1, the output of which is fed to the input of trigger circuit FF 13, where these data are fixing to latch with the arrival of the leading edge of the clock pulse /10 Ás at time t6.

In the same time interval t5- t6two other switching device SW 3 and SW 4 are connected at their input terminals c. The inputs of a summing device ADD from the trigger circuit register 13 through the switching device SW 3 data come BE2. In turn, the inputs b of the specified accumulator from register FF 16 through the switching device SW 4 and valve logical XOR XOR circuit 3 receives data E3. At this time, the signal AD is level "L". In accordance with this logic-gate XOR 3 and the adder ADD perform additive processing data according to the above algorithm, forming the output operating data E5 = (VI) + E3, which is fed to the input of trigger register FF 16, in which the data are latched with the receipt of the leading edge of the clock SUB>7both the switching device SW 1 and SW 2 skommutirovany on their input terminals b. The inputs of a multiplier die from the trigger circuit register FF 2 through the switching device SW 1 data come B. In turn, to the input terminals b of the specified multiplier from the trigger circuit FF 8 through the switch SW 2 is receiving data Vc. A multiplier device die results in a multiplication operation data BVc, the resulting data which is entered in the register FF 13 where are latched on the leading edge of the clock pulse /10 MSC at time t7.

In the same period, t6- t7the other two switch SW 3 and SW 4 are connected at their input terminals c and d, respectively. Under this condition, the inputs of a summing device ADD trigger from the register circuit FF 13 through the switching device SW 3 receive data CE1. In turn, to the input terminals b of the specified accumulator from register FF 17 through the switching device SW 4 and gate logic XOR 3 XOR data come E4. At this time, the signal DS is at "L" level. In accordance with this scheme XOR 3 and the adder ADD perform the operation of adding the data previously reviewed by calculating algorithm, formerum fixing snap these data at time t7with the arrival of the leading edge specifies the pulse 17 SC.

In the next time interval t7- t8the switching device SW 1 and SW 2 are connected at their input terminals d and b, respectively. To input terminals of a multiplier device die from the trigger circuit register FF 4 through the switching device SW 1 receives the data D. In turn, to the input terminals b of the specified multiplier register FF 8 through the switching device SW 2 data is input Vc. The multiplier die performs the operation of the multiplier data DVcthe results of which are entered in the trigger circuit FF 13. This circuit latches the incoming data DVcat time t8on the leading edge of the clock pulse /10 GMT.

At the same time, during the interval t7- t8two other switching device SW 3 and SW 4 skommutirovany on their input terminals c. The inputs a of the adder ADD from the trigger register circuit 13 through the switching device SW 3 data received BVc. In turn, the inputs b of the specified accumulator from register FF 16 through the switch SW 4 and a logical gate circuit XOR 3 XOR data come E5. At this time, the signal DS has the level "L". Where is the algorithm forming the operational data E7 = (BVc) + E5, which are entered in the trigger register FF 16, where the data are latched on the leading edge of the clock pulse 16 SK at time t8.

In the next time interval t8- t9both the switching device SW 1 and SW 2 are connected at their input terminals a. At the input terminals of a multiplier device die from the trigger block FF 1 through the switch SW 1 A. the data came In turn to input terminals b of the specified multiplier from the HV counter 31 through valve logical XOR XOR circuit 1 and the switching device SW 2 receives data Hc. The multiplier die performs the operation AHc, the output of which is fed to the input of register FF 13, which latches the data with the advent of the leading edge of the clock setting pulse /10 MSC at time t9.

In the same period of time t8- t9two other switching device SW 3 and SW 4 are connected at their input terminals c and d, respectively. The inputs of a summing device ADD from the trigger circuit FF 13 through the switching device SW 3 enter data DVc. In turn, the inputs b of the specified accumulator from the region to the E6. At this time, the signal DS has the level "L". Therefore, the XOR scheme 3 and the adder ADD perform the operation of addition on the above algorithm, forming data E8 = (DVc) + E6, which are entered in the register FF 17 where are latched on the leading edge of the clock pulse 17 SK at time t9.

This pre-processing data is completed. Thus, the data E7 fixed snap in the register FF 16, and the data E8 - register FF 17.

In the next over the time interval t9- t10the switching device SW 1 and SW 2 skommutirovany on their input terminals c and a, respectively. Under this condition, the input terminals of a multiplier device die from the trigger circuit FF 3 through the switch SW 1 is receiving data C. In turn, to the input terminals b of the same multiplier from the HV counter 31 through gate logic XOR 1 XOR and switching device receives data Hc. The multiplier die carry out the operational effect of CHc, Susila output to the trigger register FF 13, where the data are latched on the leading edge of the clock pulse /10 MSC at time t10.

Simultaneously, during the temporary Internet is ri on input terminals a of the adder ADD from the trigger circuit FF 13 through the switching device SW 3 data arrives AHc. In turn, to the input terminals b of the same accumulator from register FF 16 through the switch SW 4 and gate circuit XOR 3 XOR data come E7. At this time, the signal DS has the level "L". In accordance with this logic XOR 3 and the adder ADD implement the addition operation data (AHc) + E7, resulting in data X2. Data X2come on trigger scheme-register FF 19, which latches the data on the leading edge of the clock pulse /10 GMT, after which these data are entered in the register FF 20 and snapped into it at time t11synchronously with the arrival of the leading edge of the clock pulse /5 GMT.

In the next time interval t10- t11the switching device SW 1 and SW 2 skommutirovany on their input terminals a. The inputs of a multiplier device die from the trigger circuit register FF 1 switch SW 1 is receiving data A. In turn, the inputs b of the specified multiplier from the HV counter 31 through gate logic XOR 1 XOR and switching device SW 2 data come Hc. The multiplier die produces the multiplication data AHc. The result of such operational steps is fed to the input of register FF 13, which is prorata clock pulse / 10 GMT.

Simultaneously, over the time period t10- t11two other switching device SW 3 and SW 4 are connected at their input terminals c and d, respectively. At the input a of the adder ADD from the trigger circuit FF 13 through the switching device SW 3 data arrives CHc. In turn, the inputs b of the above-mentioned accumulator from register FF 17 through the switching device SW 4 and logic XOR 3 entered E8. At this time, the signal ADS is level "L". In accordance with this logic XOR 3 XOR and the adder ADD perform summarizing data processing in the form (CHc) + E8, forming the resulting data Y2. These data are entered in the register FF 18 where from snapping at time t11on the leading edge of the clock pulse / 5 GMT.

When Hc= 0 data X2are calculated within the above-mentioned time interval t9- t10and the data Y2in the interval t10- t11. Over the time interval after time t11data X2and Y2when data Hc= 1 - 255, are calculated in exactly the same way as the calculation for a single line scan.

At time t11H amplifiers BA1 - BA6. Next, in time period t11and t13from the output of the buffer amplifier BA1 in memory vtupv 7b via the address bus 15b is the address SAAO a total of 16 bits containing data on the most significant two bits "00"; similarly in the case when Hc= 0, the specified memory receives data Ycand Xcon the respective most significant seven bits of the data Y2(10 bits) and the data X2(10 bits), which locks into the trigger registers FF 18 FF 20. The memory selects address SAAO with its input at time t13. When Hc= 0 data Y and X on the least significant three bits of the data Y2and X2respectively, which are snapped in registers FF 18 FF 20, are passed through the register FF 22 and are latched in the register FF 23.

During the time interval after t13made periodic reproduction address CAA1 - SEA, including data Ycand Xcwhen Hc= 1 -255; these addresses are displayed on vtupv 7b via the address bus 15b in each period of the clock pulse / 5 MSC. Further, the data X and Y that correspond to specific data values Hcthat locks into the trigger cell FF 23, acting through the trigger FF 22 usersmotorola from the control circuit 24 addressing image background through the address bus 15b, throwing on output 8-bit signed codes SA - SA, "recorded" in the respective addresses in the register FF 21 in the addressing scheme 24 via data bus 16b for each period of clock pulses / 10 GMT. The specified 8-bit signed codes SA - SA are latched in the register FF 21.

In turn, the data Y and X (total - 6 bits), the corresponding symbolic codes are latched in the register FF 23, as discussed above. Under this condition, the time period t15- t17sixteen-bit address SSA containing data on the most significant two bits "00", the eight-bit sign code, not in the case of the FF 21, and the data Y and X (total - 6 bits) when Hc= 0 are displayed on the storage device vtupv 7a (VRAM 7a) via the three-position buffer amplifiers VA - VA and address bus 15a. Address SAA introduced in vtupv 7a at time t17.

In the next time interval, starting with t17in vtupv 7a similarly receives address SSA - SSA; input address data is performed during a time interval when Hc= 1 - 255, from addressing scheme 24 image background through the address bus 15a.

Storage device vtupv 7a, sensing address SSA - SSA,255, recorded at appropriate locations, the processor 25 processing image data of a background via data bus 16b for each period of clock pulses (pulse) / 10 GMT.

The above processing turn, increase or decrease image background concerning transformations of one scan line, is carried out generally at 244 rows, consisting of 28 characters or symbols (see Fig. 2), allowing you to eventually make these changes image background on the entire working area 41 of the display screen.

As noted above, the circuit 24 addressing image background computes addresses SEA - SEA, in which the rotation process, increase or decrease the specified image introduces symbolic codes, which are formed in accordance with a constant data A, B, C and D on these transformations coming from the CPU 2. Based on the generated address complex numbers SSA - SSA, each of which contains symbolic code (8 bits) taken from the output of the storage device vtupv 7b, and the data Y and X , which allows you to view data in color at a rate of 8 bits per pixel directly in the implementation process of information processing by clause is specified image. In subsequent data color (8 bit) image background snapped into the video processor 25, and then introduced into the circuit 26 to control priorities.

In turn, unit 23 of the information processing on perednebokova moving image in scheme 26 control priorities are introduced seven-bit video data at the specified moving image. The priority scheme 26 when data on the above image determines the priority between moving and tidnevnogo images; this is done on the basis of digit priority data included in image data of moving images, with the supply of higher priority data of the moving image and the image background on the generator 28 of the chroma signal. Generator color 28 is triggered when data of a relatively high priority, converting the incoming data is a moving image or image data of a background in the digital RGB signal (trehtsvetkovaya signal) in 5 bits for each color. Thus formed the digital RGB signal is supplied to the display device (display unit) 8 and the encoder 29 NTSC standard that is based on the account data, Hc

Consider hardware and algorithmic option allows you to display more suited to the image background, for example screwless the road (see Fig. 14-18), on the basis of a single reference, the original two-dimensional image (see Fig. 13). Further, in the case where the present invention is applied, for example, simulation games, in the exercise of magnifying swivel handle with the prevailing rotate the image background when playback of the rear view (like from the driver's cab car or cockpit during rotation of the rolling road, takeoff or landing), proposed Videoprocessor system allows you to visually simulate a three-dimensional situation, ultimately contributing more visual reproduction of the image background.

This is illustrated below in more detail. When converting the original isoprostane. In this case, it is only necessary to produce the increase in scale factor (linear increase) in the X-direction on the parameter A in the formula (10) to the bottom of the screen. However, the increase or decrease of the image in the Y direction is not performed, i.e., the scaling factor in the Y direction by the parameter D in equation (12) remains constant.

When converting the original (source) image background, shown in Fig. 13, the video image shown in Fig. 15, produces a change in the value of Hproaming shift in the X direction on each row and processing of data by increasing the size of the image in the same direction. In this case, it is necessary to make a step by step sequential change of the parameter in equation (13) and the increase of the scale factor in the X direction on the parameters A and B in equations (2) and (3) for the lower parts of the screen. However, the increase or decrease of the image in the Y direction on the parameters C and D in the formula (4) and (5) may remain constant.

When converting the original image of the original background, as shown in Fig. 13, in the image shown in Fig. 16, is the increase in the line is the parameter D in the equation (12) for the lower parts of the screen. However, the increase or decrease in the X-direction is not performed, i.e., the scale factor in the X direction by the parameter A in the formula (10) may remain constant.

When converting a two-dimensional initial image background, shown in Fig. 13, in a three-dimensional image shown in Fig. 17, produced jointly rendering shown in Fig. 15, and the rendering shown in Fig. 16. More specifically, in this case, it is necessary to increase the scale factor in the X direction by the parameter A in the expression (10) for the lower parts of the screen, changing simultaneously is moved offset Hpfor each row with the corresponding sequential change of the parameter X1in the formula (13), and in addition, to increase the scale factor in the Y direction on the parameters C and D in the formula (4) and (5) for the lower parts of the screen.

Next focuses on turning the image processing background. For this purpose it is desirable to divide the screen into several parts (Fig. 18 - three) vertically within the human period, and sequentially steps to change at 45othe direction of rotation of the individual parts pervonachalnogo variation of the angle of the parameter A in the formulas (2) - (5) on each boundary of the screen vertically.

At the same time, it is desirable to rotate the original image background, shown in Fig. 13, without any distortion, so that the angle parameter A in the above formula could be changed gradually to a constant value for each frame. To illustrate this fact graphically it is extremely difficult, and therefore, the illustrative information on this issue is not performed.

As mentioned above, the memory address vtupv 7 in the case where the original image background, the corresponding reference image data recorded (stored) in vtupv 7 is rotated, the increase or decrease is calculated by addressing scheme 24 tidnevnogo image, and directly during the turn, increase or decrease the specified image from the memory vtupv 7 reads color data of the converted image, and then generates a corresponding signal that is output and displayed on the display 8. Thus, the Central processing unit CPU 2 should only be set to constants, but not to calculate data corresponding to the positions (coordinate positions), picture in order to conduct additional processing of some other image. Therefore, the present invention has the advantage that it allows to increase the throughput of the CPU compared with the known technical means used for rotary-magnifying-diminutive convert video. An additional advantage is that the addresses of the video data in the image background in the storage device 7, the relevant provisions of the specified image horizontally and vertically during its rotation, enlargement and reduction, calculated driving block addressing 24 in the form of switching device switches SW 1 and SW 4, a multiplier device die and the adder ADD, as outlined above. This allows faster data processing for rotation, enlargement and reduction of image in comparison with the known technical means of considered assignments. In addition, various circuits included in the block addressing 24, are used as circuits for General use, performing data processing, rotate, or increase or decrease the image background in the split time mode. This, of course, contributes to the simplification of the circuitry of this unit and the private scheme.

Further, due to the fact that videoprocessing unit 1 calculates the address of a video image background exposed turn, increase or decrease, with the aim of sampling the data, there is a real possibility to save data on the original image to the original. Therefore, in this case excludes the possibility of the accumulation of computational errors in the implementation of their respective turns, what fundamentally distinguishes the image from the known device is a prototype, the operation of which the image background turns disposable and is displayed in a position different from the position of the original image, this will change and its geometric shape.

Although in the description above options videoprocessing block 1 was used to rotate and enlarge or reduce the image background and display it, this extended functional exclusiveness should not be viewed as mandatory essential feature of the invention. In principle, the specified videoprocessing block can be oriented in its performance to exercise while bicine or decrease the video. But the design of the addressing scheme 24 remains unchanged. Constants and calculated the CPU 2 may be equal to 0, if you are only turning the processing of data; in turn, constant , calculated the same Central processor may be 0 if the meaning of the conversion image is its increase or decrease.

Further it should be noted that although the description above versions of the invention sformulirovano applied to the video data processing device of signed type, the amount of the claims of the invention is significantly wider. In particular, the invention is applicable to processors so-called dot-mapping type, the principle of action which involves the identification of addresses for each point of the image formation based on the color data using a storage device with a random sample containing color data corresponding to the region 40 is considered vtupv.

In conclusion it must be emphasized that the above detailed description is merely illustrative in nature and should not be interpreted as information, limitrule defines the essential features invented is novania.

1. The imaging device for processing the background image to generate an output image containing the Central processor, first memory means for storing the representation of the background image, processing means for processing the stored representation of the background image in accordance with the parametric data (A, B, C, D) provided by the CPU to generate an output image that contains rotated, enlarged and/or reduced version of the background image, characterized in that it is Videoprocessor device for the Autonomous control of the moving image and the background image, and contains the first storage means for storing the representation of the background image as iconic codes representing a multitude of characters, each of which is composed of multiple image elements, the device of the raster of a television display for displaying the output image, the second storage means for storing color data of the respective picture elements that make up these characters, and means for generating first positional data (HcVc) background izobrazite with scan device television raster display in the horizontal and vertical directions, moreover, the processor means is configured to processing the stored representation of the background image without changing the stored representation and contains a control circuit address of the background image, which operates after processing the turn, increase and/or decrease in order to generate a second positional data of the background image (Xc, Yc), which are in the first storage means address sign, which should be placed in the output image at the position corresponding to the first positional data (HcVc), the imaging device also includes a first reading means for reading the sign code from the first storage means in accordance with the second positional data of the background (Xc, Yc), second reading means for reading color data from the second storage means on the basis of symbolic code read by the first reading means, and means for generating a video signal for display on a raster device television display based on the data read by the second reading means.

2. The device under item 1, characterized in that the means for generating positional dansor - to generate the reference coordinate data (X0, Y0for at least one of the operations of rotation, enlargement and reduction, the processor means to perform a matrix operation in accordance with the following equation on the basis of the first positional data (X1, Y1), parametric data (A, B, C, D) and the reference coordinate data (X0, Y0to estimate the second positional data (X2, Y2elements of the image after performing at least one operation from the operations rotate, zoom in and out on the screen of this display:

< / BR>
and so that, if the scaling factor in the horizontal direction to increase or decrease equal to the scaling factor in the vertical direction to increase or decrease equal to the angle of rotation are equal , then the parametric data (A, B, C, D) respectively given by the following equations:

A = 1/cos,

B = 1/sin,

C = -1/sin,

D = 1/cos.

3. The device under item 1 or 2, characterized in that the means for generating first positional data is configured to generate the first positional data (X1, Y1) represented by the equations X1= Hp+ Hcand Y1pand the positional data of the picture element in the horizontal and vertical directions is Hcand Vc.

4. The device under item 2 or 3, characterized in that the processor circuit can perform part of the matrix operations required for the next period of the line scan raster display period blanking the beam during the reverse course in rows, and perform the rest of the matrix operation for each picture element in the next period of the line scan.

5. Device according to any one of paragraphs.1 to 4, characterized in that the first storage means includes a memory area exceeding the size of the screen of a raster display, and means for generating positional data includes means for generating data to indicate data relating to the sign, which must be displayed from the number of characters stored in the first storage device.

6. Device according to any one of paragraphs.2 to 5, characterized in that the processor circuit may generate the second positional data (X2, Y2in accordance with the following equations:

X2=[X0+(Hp-X0)B+VcB]+HcA,

Y2=[Y0+(Vp-Y0)C+VcD]+Hc
A and HcC equations for each picture element during the period of the line scan of the raster display and calculate the rest of the equations required for the period of the line scan, during blanking the beam during the reverse course on the field before blanking the beam during the reverse course by row.

 

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