The device for calculating the convolution

 

(57) Abstract:

The invention relates to the field of computer engineering and can be used in specialized computer systems to calculate swerski. The device contains P processing units 1, where L = P + R, P = max(P0P1), P0and P1- dimension vector of weight coefficients, R is the number of redundant processing units 1, two summation block 2 and 3, L combinational adders 4, (L -1) register 5, a group of L nodes comparison 6, node comparison, 7, (L -1) group And 8 (L -1) group elements And 9, L groups of elements And 10, (L -1) a group of items, OR 11, (L -1) a group of 12 items OR groups of items OR 13 and 14, element OR 15 and block 16 signal failure. The basis of operation of the device based on parallel-sequential organization of computing hardware control, bypass and replacement of the failed processing units. 4 tab., 7 Il.

The present invention relates to the field of computer engineering and can be used in specialized computer systems to calculate the convolution.

Closest to the present invention is a device containing a group of P computing modules and a group of items, OR [2].

In conveying device for processing information containing the P processing units 1, where P = max (P0P1), P0and P1- the dimension of the vectors of weights, the first group of elements OR 14, and quantum groups 17 are connected respectively to the first inputs of the elements OR 14 of the first group, the outputs of the first and second groups of the i-th processing unit 1 (where i = 1, ..., P) are connected respectively to the information inputs of the first and second groups (i + 1)-th processing unit 1 entered (P + 1)-th to L-th processing units, where L = P + R, R is the number of redundant processing units 1, the first 2 and the second summation block 3, L combinational adders 4, (L - 1) register 5, a group of L nodes comparison 6, site comparison 7, (3L - 2) groups of elements 8, 9, and 10, 2L groups of elements OR 11, 12, 13 and 14, the element OR 15 and the forming unit fault signal 26, and a clock input 28 of the device is connected to the clock inputs of the processing units 1 to (P + 1)-th to the L-rd, to the clock inputs of the first and second summation blocks 3 and to the inputs of a read/write register 5 with the first (L - 1)-th, the outputs of the elements OR of the first group are connected respectively to the information inputs of the first group of the first processing unit, the information inputs of the second group which are connected respectively to the information inputs of the second group of devices, the outputs of the first summation block connected respectively to the second inputs of the elements OR of the first group and respectively to the outputs of the device, the outputs of the first and second blocks summation connected respectively to the information the AC signal failure 16, the output of which is connected to the output 30 of the sign of failure, the information inputs of the third group 19 which are connected respectively to the first inputs of the first to a-th elements And 9 (where a is the width of information) from the first (L - 1)-th group and to the information inputs of the third group of L-th processing unit 1, the control input 21 of the first group are connected respectively to the information inputs of the first group of nodes 6 comparison group, control inputs of the second group 20 are connected respectively to the control inputs of the group of the first processing unit, the outputs of the third group of the j-th processing unit (where j = 1, ..., L - 1) are connected respectively to the first inputs of the elements OR 11 (j + 1)-th group, the outputs of which are connected respectively to the control inputs of the group (j + 1)-th processing unit 1, the outputs of the fourth group of the k-th processing unit 1 (where k = 1, . . . , L) are connected respectively to the information inputs of the group of k-combinational adder 4, the outputs of the j-th combinational adder 4 is connected to information inputs of the second group of the j-th node 6 comparison group and to the information inputs of the j-th register 5, the outputs of which are connected respectively to the second inputs of elements OR 11 (j + 1)-th group, outputs L-gervy and second control inputs 22 and 23 are connected respectively to the first and second control inputs of the L-th processing unit 1 and respectively to the first inputs (a + 1)-th and (a + 2)-th elements And 9 groups from the first to the (L - 1)-th, the outputs of the fifth group and the first output of the m-th processing unit 1 (where m = 2, ..., L) are connected respectively to the first inputs of elements And 8 from the first to the (a + 1)-th (2L + m - 1)-th group, the second output of the m-th processing unit 1 is connected to the first input (a + 2)-th element AND 8 (2L + m - 1)-th group, the outputs of the fifth group and the first output of the first processing unit 1 is connected respectively to the first inputs of elements And 10 (L + 1)-th group, the outputs of the elements And 9 j-th group and elements AND 8 (2L + j)-th group are connected respectively to the first and second input elements, OR 12 (L + j)-th group, the output of the j-th node 6 comparison group connected to the second inputs of elements And 9 j-th group elements And 10 (L + j)-th group, to second (inverted) inputs of elements AND 8 (2L + j)-th and j-th information input group forming unit fault signal 16, the output of the L-th node 6 comparison group connected to the second inputs of elements AND 10 2L-th group and the L-th information input group forming unit fault signal 16, the third output of the k-th processing unit 1 is connected to the information input of the k-th combinational adder 4 and k-th output 29 groups sign of failure, the outputs of the elements OR 12 (L + j)-th group are connected respectively to the information inputs of the third group to the first and second upgo element OR 13 2L-th group, the outputs of which are connected to the l-inputs of the first 2 and second 3 blocks summation, the outputs (a + 1)-x items And groups with (L + 1) th to 2L-th connected to the inputs of the OR element 15, the output of which is connected to the control inputs of the first and second summation blocks 2 and 3, the k-th control input of the first group 24 of the device connected to the first deployment entry of the k-th processing unit, k-th control input of the second group of 25 devices are connected to the second installation to the input of the k-th processing unit, the k-th control input of the third group 26 are connected to the third installation to the input of the k-th processing unit, the k-th entry lock device 27 is connected to the input block of the k-th processing unit. Each processing unit 1 includes first and second compute nodes 32 and 33, the trigger 34, node comparison, 35, from the first to the third trigger 34, the element nodes And 36 - 38, the And gate 39 and the node elements OR 40, with each processing unit 1 information inputs of the first group 41, the second group 42, the third group 43, the first control input 44, the second control input 45 and the control inputs of group 46 processing unit connected respectively to the inputs of the groups of the first node elements And 36 respectively to the inputs of the groups of the second node Lamela elements OR 40, the outputs of which are connected respectively to the outputs of the first group 54, the second group 55, the fifth group 56 to the first 57 and second 58 outputs of the processing unit 1, the outputs of the second group of the first node elements And 36 are connected to the outputs of the third group 53 processing unit outputs the first group to the second node elements And 37 connected respectively to the information inputs of the first, second, and third groups, the first and second control inputs of the first computing node 32 and accordingly to the information inputs of the first, second and third groups, the first and second control inputs of the second computing node 33, the outputs of the second group to the second node elements And 37 connected respectively to the outputs of the fourth group 52 of the processing unit, the first input set 49 which is connected to the inputs of the installation to its original state of the first and second computing nodes 32 and 33, the outputs of the first, second, and third groups, the first and second outputs of the first computing node 32 connected respectively to the input groups of the third node elements And 38 and accordingly to the information inputs of the first node group comparison 35, the information outputs of the second group which are connected respectively to the outputs of the first, second, third group, therefore, its to the inputs of the second group of node elements OR 40, the output node of the comparison 35 is connected to the information input of the trigger 34, the output of which is connected to the input of the third node elements And 38, to the input of the second node elements And 37, to the inverted input of the first node elements And 36 and to the third output of the processing unit, input block 50 and the clock input 51 which are connected respectively to the first (inverse) and the second inputs of the element And 39, the output of which is connected to the clock inputs of the first and second computing nodes 32 and 33 and to the clock input of the trigger 34, the inputs installed in the zero and unit which are connected respectively to the second and to the third input of the unit processing. Each compute node 32 (33) contains from first to fifth registers 69 and 73, the first and second triggers 74 and 75, combinational adder 76, the multiplier 77, the first and second groups of elements And 78 and 79, the first and second elements 80 and 81 and a group of items OR 82, and each compute node information inputs of the first group 83 are connected respectively to the information inputs of the first register 73, the outputs of which are connected to information inputs of the first multiplier and to the outputs of the second group 90 computing node, the information inputs of the second group 84 computing at uceni respectively to the first inputs of elements And the first group 78, the second group 79 and to the outputs of the third group 91 computing node, the information inputs of the third group 85 which are connected respectively to the information input of the fifth register 71, the outputs of which are connected to information inputs of the first group of combinational adder 76, the outputs of which are connected to the outputs of the first group 89 computing node, the first control input 86 of which is connected to the information input of the first flip-flop 74 and to the first inputs of the first and second elements 80 and 81, the outputs of which are connected respectively to the inputs of the read/write 69 second and third registers 70, the output of the first flip-flop 74 is connected to the first output 92 of the computing node, the second control input 87 which is connected to the information input of the second trigger 75 to the second input of the first element 80 and the second (inverted) input of the second element And 81, the output of the second trigger 75 is connected to the second inputs of elements And the first and second groups 78 and 79 and to the second output of the computing node, the clock input 88 which is connected to the inputs of the recording-reading out of the first 73, 72 fourth registers to the inputs of the synchronization of the first and second triggers 74 and 75, and to a third input of the first element And 80 and to the third input VM input elements OR 82 group, the outputs are connected respectively to the information inputs of the second group of the multiplier 77, the outputs of which are connected respectively to the information inputs of the second group of combinational adder 76. Each unit summation 2 (3) contains the first and second registers 60 and 61, combinational adder 62, the element AND-NOT 63 and the element 64, with each unit summation 2 (3) informational inputs 63 unit 2 summation (3) connected to information inputs of the first and second registers 60 and 61, the outputs of which are connected respectively to the information inputs of the first and second groups of combinational adder 62, the outputs of which are connected to the outputs 68 unit summation, control input 66 which is connected to the first inputs of elements AND NOT 63 and 64 outputs. The block signal failure 16 contains the element OR NOT 94 and the element OR 95, and information input 96 and information inputs group 97 block signal failure connected respectively to the first input element OR 95 and to the inputs of the element OR NOT 96, the output of which is connected to the second input member OR the output of which is connected to the output of the processing unit failure.

In Fig. 1 - 3 presents the structural scheme and, R - the number of redundant processing units of Fig. 4 is a block diagram of the processing unit of Fig. 5 is a structural block circuit diagram of the summation in Fig. 6 is a structural diagram of a computing node of Fig. 7 is a structural block circuit diagram of a signal failure.

Device for conveying information processing contains L processing units 1, where L = P + R, P = max(P0P1) where P0and P1- dimension vectors of weights, the summation blocks 2 and 3, L combinational adders 4 (L - 1) register 5, a group of L nodes comparison 6, node comparison, 7, (L - 1) group elements And 8, (L - 1) group elements And 9, L groups of elements And 10, (L - 1) group elements OR 11, (L - 1) group elements, OR 12, groups of items OR 13 and 14, the element OR 15, the processing unit failure 16, group of information inputs 17 to 19, the group of the control inputs 20 and 21, the control inputs 22 to 26, the inputs of the block 27, the clock input 28, a group of outputs of the sign of failure 29, the output characteristic failure 30 and outputs the result of 31.

Each processing unit 1 includes compute nodes 52 and 33, the trigger 34, node comparison, 35, member nodes And 36 - 38, the And gate 39, the node elements OR 40, the group of information inputs 41 and 43, a group of control inputs 44, control inputs 45 - 49 is 61, combinational adder 62, the element AND-NOT 63, the And gate 64, a group of information inputs 65, the control input 66, a clock input 67 and 68 outputs.

Each compute node 32 and 33 contains registers 69 - 73, triggers, 74 and 75, combinational adder 76, the multiplier 77, group of items, And 78 and 79, the elements 80 and 81, a group of items OR 82, group of information inputs 83 and 85, the control inputs 86 and 87, the clock input 88, the outputs 89 - 93.

The processing unit failure 16 contains an element OR-NO 94, item, OR 95, the outputs 96 and 97 and release 98.

The basis of operation of the device based on the algorithm for computing the convolution

< / BR>
P0and P1- dimension vector of weights ; I - dimensionality of the output vector

Use the following recurrence relation:

Zi,1= 0, Si,0= 0, i = 0, 1...I-1;

Zi,p= Zi,p-1+P-1-pX-P+1+i+pp = 0,1..., P-1 i = 0,1..., I-1

Si,p= Si,p-1+ rP-p+1Y-P+i+p-1p = 1, 2...P, i = 0, 1...I-1;

Yi= Si,p+ Zi,P-1, i = 0, 1...I-1

where

P = max (P0P1). P0> P1, ri= 0, i = P1+ 1, P2+ 2,..., P with P1> P0i= 0, i = P0P0+ 1 ...P.

The logic of the computing node 32 (33) the capacity of the node 32 (33) of the processing unit 1 operates in four modes.

In the first mode, the inputs 86 and 87 are served zero signals that set the trigger 74 and 75 in the zero state. This opens up the items And 79 in the registers 71, 73 and 72 are recorded, respectively, the elements of Z, X and U, the registers 70 and 69 respectively store the elements of a and r. The outputs 90 and 91 are issued accordingly, the elements of Z' = Z + X, X and U

In the second mode, the trigger 74 and 75 are respectively zero and one state. In the registers 71, 73 and 72 are recorded, respectively, S, Y, and U registers 70 and 69 respectively store the elements of a and r. Single output trigger 75 opens the elements And 76. The outputs 89, 90 and 91 are issued accordingly, the elements of S' = S + r Y, Y and u

In the third mode, the trigger 74 and 75 are installed in the unit and the zero state, respectively. In the registers 71, 73 and 72 are recorded, respectively, the elements of Z,X,. Element And 81 is opened and the register 70 is recorded items And 79 are opened, the outputs 89, 90 and 91 are issued accordingly, the elements Z = Z+X, X and .

In the fourth mode, the trigger 74 and 75 are installed in one state. In the registers 71, 73 and 72 are recorded, respectively, the elements of S, Y and Z. the Element 80 is opened and the register 69 contains an element r. Single S="ptx2">

The summation block 2 (3) operates in two modes. In the first mode to the output 66 is served a zero signal at the output of element AND-NOT 63 is formed of a single signal, which provides a record of the element Z in the register 60.

In the second mode to the output 66 is fed to a single signal, which opens the item And 64 and provides a record of the item S in the register 61. At the output 68 is formed is Y = Z + s

In table. 3 shows the inputs and outputs of the nodes 2 (3) processing units 1 and unit 2 summation (3), and the status registers and triggers when calculating the values of Y0, Y1and Y2for the case of P0= I = 3 and P = 2 in the absence of failures in the device.

Zero and second cycles of operation the elements of X-2X-1,1and2are fed to the inputs of the respective processing units 1.

The computational process begins at processing block 13at the second clock cycle when calculating the value of Z0,0= Z0,-1+2X-2. On subsequent cycles, the calculation process is performed in accordance with table. 1 and 2.

On the sixth, eighth and tenth cycles in block 2 summation (3) are formed, respectively, the elements of Y0, Y1and Y2the licensing of operations performed by the computational nodes 32 and 33. The results of operations are generated at the output of the combinational adder 76 upon completion of transients in combinational circuits 76 and 77 and are issued on the outputs 89 compute nodes 32 and 33, where these results come on the corresponding input node of the comparison 35. When the coincidence of the information received at the input node 35 comparison of compute nodes 32 and 33, the processing unit 1jis considered healthy and one output node 35 comparison is recorded in the trigger 34, which is used for fixing the sign of the health of this processing unit 1j. Output trigger unit 34 is fed to the corresponding inputs of the elements 37, 38 and inverted inputs of elements And 36, as a result of this information with outputs 89 - 93 computing node 32 through the elements And 38 OR 40 is fed to the outputs 54 - 58 processing unit 1j. Single output trigger 34 is also provided on the inverted inputs of the And elements 36 and blocks bypass this block processing 1j. As a result, the value of g at the input 44 of the block 1j, available at the output 52 of the block 1j. A single value is given also to the output 59 of the block 1jand, accordingly, the output 29jsign of failure. j. If there is a mismatch of information received at the input node 35 comparison of compute nodes 32 and 33, the processing unit 1jis considered faulty and zero output node 35 comparison is recorded in the trigger 34. With the trigger output 34 of the zero signal is applied to corresponding inputs of elements And 37 and 38 and inverted inputs of elements And 36, as a result of this issue with outputs 89 - 92 computing node 32 is blocked. Zero, the outputs of the trigger 34 is also provided on the inverted inputs of elements And 36, as a result, the flow of information in the compute nodes 32 and 33 through the elements And 37 and grant information from node 32 is blocked and offers a way of bypassing this processing unit 1j. In this case, the information coming from the previous processing unit 1j-1through the elements And 36 OR 40, issued respectively to the outputs of 54 to 58 of this processing unit 1j. The value of g at the input 44 of the block 1, available at the output 53 of the block 1j. A zero value available at the output 59 of the block 1jand respectively to the output 29jsign of failure. Zero signal at the output 29 of the device indicates the means of external control on the detected fault block 1j.

For justanobody input device 24. In this case, the external controls on the input 24jthe device is formed of a single signal through the input 47 of the processing unit 1jis supplied to the input set to zero trigger 34. In order to force the processing unit 1jthe structure of the device, for example, after his forced withdrawal or after fixation of false rejection, using input 25jdevice. In this case, the external controls on the input 25ja signal is generated, which through the inlet 48 of the processing unit 1jis fed to the input of the installation unit of the trigger 34. Thus, the operation processing unit 1jcan be blocked by an input 27jdevice single signal. In this case, the unit via an input 27jblock 1jis supplied to an inverse input element And 39, which blocks the passage of clock pulses to the clock inputs of compute nodes 32, 33 and the trigger 34.

To install registers and triggers compute nodes 32 and 33 block 1jin the initial state at the start and restarts the device using input 26jdevice. For unit 1jin the initial state, input 26jdevice modalcontainer nodes 32 and 33. The input set to the initial state of the computing nodes 32 and 33 are connected to the inputs installed in the zero state of all registers and flip-flops of the nodes 32 and 33 (Fig. 3 not shown).

To the input 20 of the installation served zero value for g. In the presence of intact blocks 11, ..., 1Pwith outputs 291, ..., 29Psigns of failure are given individual signals which are fed to the inputs of the corresponding combinational adders 41, ..., 4P. The value of g, arriving at the inputs 44 block 1iwhere i = 1, ..., P, in the case of health blocks 11, ..., 1i-1-equal to (i - 1). In the case of the health unit 1ithis is available at the output 52 of the block 1iand is supplied to the corresponding input of the combinational adder 4ifrom the output of which is removed is g = i, which is recorded in the register 5iand is supplied to one input node of the comparison 6ithe other input of which receives the value of P. Thus, at each step, if the health unit 1iwith output combinational adder 4ireturns the value g = i.

When different values issued with combinational adder 4iwith probability P, output node 6 comparisoniiand opens them. As a result of this information with outputs 89, 92 and 93 of the node 32 (33) block 1ithrough the elements AND 8iand OR 12iarrives at the inputs 85, 86 and 87 of the node 32 (33) block 1i-1and delivery of information from outputs 89 and 92 node 32 (33) block 1ithrough the elements AND 10ithe inputs of the elements OR 13 and 15 is blocked. If the values match, issued with combinational adder 4iwith probability P from the output node of the comparison is given individual signal which is supplied to corresponding inputs of elements AND 9iand 10iand opens them up, and fed to the inverse of the input elements AND 8iand closes them. As a result, the information received at the inputs 19, 22 and 23 of the device, passes through the elements AND 9iand OR 12ithe inputs 85, 86 and 87 of the block 1iand the outputs 89 and 92 of block 1ithrough the elements AND 10iand OR 13 and 15 to corresponding inputs of a summation blocks 2 and 3. When the input processing unit failure 16 of at least one single output node comparison 6, the output unit 16 will be given a single value.

The coincidence of the results obtained at the outputs of blocks 2 and 3 kummerowia signal failure 16.

The zero signals at the inputs 97 unit 16 indicates the exhaustion of the reserve unit. In this case, the output of the element OR NOT 94 is issued to a single signal, which passes through the element OR 95 at exit 98 of the block and, accordingly, the output 30 of the sign of failure. The zero signal at the input 96 of the block 16 also indicates the failure of the device and leads to a single output device 30. In all other cases, the output device 30 will remain zero signal. Zero signal at the output 30 of the device indicates the preservation of the health of the device in this step. In case of failure of the unit 1khappens bypass this block. However, in the case of health the previous blocks 11, ..., 1k-1at the entrance 44 of the block 1kreceives the value of g = k - 1 which goes to the output 51 of the block 1kwith outputs 52 and 59 of the block 1kremoved zero values and, thus, the output of the combinational adder 4kremoved zero g. As a result, output node 6 comparisonpcleared to zero. If block 1P+1OK, to the input 44 of the block 1Q+1receives the value of g = P - 1, from the output 59 of the block 1p+1P+1removed individual signal which is supplied to the corresponding input unit 16. A zero value of g generated by the adder 4kon subsequent cycles, is fed to the corresponding inputs of the elements OR 11kand further does not affect the value of g generated at the input 44 of the block 1k+1. Thus, the processing unit 1kderived from the computational process by bypassing, and the first of defective spare blocks, for example 1P+1enter in the calculation process, the length of the line of well-functioning processing units of 1 device.

Upon detection of a failure of the unit 1k(where k P) and, consequently, the introduction of the line of block 1P+1elements AND 8popen and information from outputs 89, 92 and 93 of the block 1P+1supplied to corresponding inputs 85, 86 and 87 of the block 1pand the elements AND 9pclosed, blocking the flow of information from inputs 19, 22 and 23 of the device in block 1p. Moreover, the elements AND 9P+1open elements AND 8P+1closed and information from the inputs 19, 22 and 23 of the device arrives at the inputs 85, 86 and 87 of the block 1P+1.

Upon detection of S denial of the output 53 of the block 1kwill be given a value of g = Q - S, which is fed to the input 44 of the block 1k+1. Because the block 1k+1is considered healthy, the output 59 of the block 1k+1given a single signal, the output of the combinational adder 4k+1will be given a value of g = Q - S + 1, which is fed to the input 44 of the block 1k+2and so on, When you hit the g-values at the input 44 operable unit 1iat the output of the combinational adder 4iformed a value equal to g + 1. When you hit the G-values to the input 44 of the defective block 1iat the output of the adder 4iformed to zero, and the value of g from the output 53 of the block 1iis fed to the input 44 of the next block 1i+1the ruler. Output combinational adder 4P+Son output node 6 comparisonP+Sis is g = P from the output of the node comparison 6P+Sgiven a single signal, which is supplied to the corresponding input unit 16. Through the open items And 10 items OR 13 and 15 of the result is supplied to the summation blocks 2 and 3. The coincidence of the results at the outputs of blocks 2 and 3 inverted output node comparison 7 is given a zero signal which is fed to the input block 16 and, thus, output 16 output 30 sign of failure is given zero the s of the device 31. When R < S on the outputs of the nodes comparison 6 will be zero, the output of block 16 will be given a single value, which indicates the exhaustion of the reserve blocks 1. When the discrepancy between the outputs of summation blocks 2 and 3, with the inverted output node 7 comparison will be given a single value, which will be transferred to the corresponding input unit 16. Therefore, when R < S, or upon detection of a failure of the summation block 2 (3) from the output unit 16 to the output 30 of the sign of failure will be given a single value, which indicates failure.

Thus, the accumulation of R bounce processing units 1 the efficiency of the device is stored and the length of the line of well-functioning processing units 1 device remains constant. Upon detection of (R + 1)-th failure or refusal of the summation block 2 (3) from the output 31 of the device is given a sign of failure, which then enters the external controls.

When the device is unlocked backup processing units 1 automatically operate in a control mode duplication. In this case, the outputs of the first processing unit 1nwhere n P + 1, located in the reserve, the output of the additional nodes 32 and 33 and the subsequent comparison of results in the node 35 backup processing units 1nupdated values of the triggers 34 these blocks. Then use this backup processing units 1nis happening with regard to their health.

Let on the 7th cycle of the device detected the failure processing unit 12. In this case, for P0= I = 3, P1= 2, L = 4 and R = 1 the organization of the input and output data flows, control signals, registers, and triggers and values generated at the output of the combinational adders processing units 11- 14shown in the table. 3.

At stage t = 7 detected the failure of the unit 12at step t = 8 is locked block 12(further information under its nodes does not affect further processing), obnulenie blocks 11and 13at stage t = 9 restart the device to the inputs of blocks 11and 14started filing the relevant values). With tact t = 8 are crawling block 12and inclusion in the backup block 14. The length of the ruler of the device remains the same.

Possible recovery algorithm computing process after detection of the failure block 1jprovides the following sequence dasii from block 1j-1in block 1j-2zeroing blocks 1j-1, 1j+1, 1j+2, ..., 1P< / BR>
cycle i + 1: read data from block 1j-2in block 1j-3, zeroing block 1j-2.

cycle i + 2: read data from block 1j-3in block 1j-4, zeroing block 1j-4.

cycle i + 3: read data from block 1j-4in block 1j-5, zeroing block 1j-5.

cycle i + k: reading information from block 1j-k-1in block 1j-k-2, zeroing block 1j-k-1< / BR>
If tpthe time (number of cycles) required to prepare for the restart of the device by means of external control, the time reinit line will be (j+tp=) cycles.

All timing diagrams of the filing of the values of the input matrix elements and control signals are generated by means of the external control apparatus or environment.

Due to technological crystal structure of IP health or failure of its various fractions are interrelated. The degree of connection between the failures of different shares the IP is measured by the correlation coefficient, the value of which is greater than the higher level of technology and the degree of integration of the IC 3. The presence of at least 16-bit omnoi the tion and the level of technology, sufficient for the manifestation of a high degree of correlation of failures. When the control duplication of computational nodes need to bounce these nodes were independent. So you want the nodes 32 and 33 of the processing unit 1, and the summation blocks 2 and 3 were implemented on different crystals of IP. Similarly, on the basis of the correlation of failures inside the crystal IP, you need to excess or redundant processing units 1 did not appear on some crystals of IP together with the workers.

Technical and economic effect of the proposed device is as follows.

This device is continuous hardware monitoring throughout time and lock the issuance of erroneous information upon detection of the faulty processing unit. The device implements the most complete hardware control, focused on the detection of all types of failures, the time control is comparable with a clock period. Reliability operation processing unit systolic device will be determined as

Df(t) = PCR=(t) + P0,0(t)

where

PPR=(t)the probability of correct operation of the processing unit 1;

P0,0(t) is the probability PR systolic devices

,

where

Puz(t) - probability computing node 32 (33).

In accordance with the ratio of hardware cost block 1 and block 2 (3) in assessing the reliability of operation of the device will take into account only the blocks 1. Then the reliability of the operation of the entire device will be determined by the expression

Df= (2Puz(t)-P2yC(t))P,

Puz= 0,99, P = 3, Df= 0,996,

Puz= 0,99, P = 10, Df= 0,9891,

Puz= 0,999, P = 3, Df= 0,999997,

Puz= 0,999, P = 10, Df= 0,999989,

Puz= 0,9999 and above Dfalmost equal to 1.

The recovery time of the computational process (obtaining a reliable result on the output device) is proportional to the value of nOTCwhere nOTCP, nOTC- the minimum number among the numbers of failed blocks processing line device.

1. The device for calculating the convolution containing P processing units, where P = max(P0P1), where P0and P1- the dimension of the vectors of weights, the first group of elements OR, with the clock input devices are connected to the clock inputs of the processing units from Pervov is WHETHER the first group, the outputs of the first and second groups of the i-th processing unit (where i = 1. ..P) are connected respectively to the information inputs of the first and second groups (i + 1)-th processing unit, characterized in that it comprises first and second summation blocks, with (P+1)-th to L-th processing units, where L = P+R, R is the number of redundant processing units, L - combinational adders, (L - 1) case, the group of L sites comparison site comparison (3L - 2) group elements AND 2L groups of elements OR (L - 1)-th group of elements OR groups of elements OR element OR unit of a signal failure, and the clock input devices are connected to the clock inputs of the processing units with (P+1)-th to the L-rd, to the clock inputs of the first and second blocks of summation and inputs the read/write registers with the first (L - 1)-th, the outputs of the elements OR of the first group are connected respectively to the information inputs of the first group of the first processing unit, the information inputs of the second group which are connected respectively to the information inputs of the second group of devices, the outputs of the first summation block connected respectively to the second inputs of the elements OR of the first group and respectively to the outputs of the device, the outputs of the first and second blocks summation PADCO connected to the information input processing unit failure, the output of which is connected to the output indication of failure of the device, the information input of the third group which are connected respectively to the first inputs of the first and second elements And a (where a is the dimension of the information), the first through (L - 1)-th group and to the information inputs of the third group of L-th processing unit, the control inputs of the first group are connected respectively to the information inputs of the first group of nodes of the comparison group, control inputs of the second group are connected respectively to the control inputs of the group of the first processing unit, the outputs of the third group of the j-th processing unit (where j = 1, ..., L - 1) are connected respectively to the first inputs of the elements OR (j + 1)-th group, the outputs of which are connected respectively to the control inputs of the group (j + 1)-th processing unit, the outputs of the fourth group of the k-th processing unit (where k = 1, ..., L) are connected respectively to the information inputs of the group of k-combinational adder, the outputs of the j-th combinational adder connected to information inputs of the second group of the j-th node of the comparison group and to the information inputs of the j-th register whose outputs are connected respectively to the second inputs of the elements OR (j + 1)-th group, the outputs of the L-th Raman with the matter inputs connected respectively to the first and second control inputs of the L-th processing unit and respectively to the first inputs (a + 1)-th and (a + 2)-th elements And groups from the first to the (L - 1)-th, the outputs of the fifth group and the first output of the m-th processing unit (where m = 2, .. . ,L) are connected respectively to the first inputs of elements And the first to a-th (L + m)-th group and (a + 1)-th element And the (L + m)-th group and respectively to the first inputs of the And elements from the first to the (a + 1)-th (2L + m - 1)-th group, the second output of the m-th processing unit connected to the first input (a +2)-th element AND the (2L + m - 1)the second group, the outputs of the fifth group and the first output of the first processing unit connected respectively to the first inputs of elements And (L + 1)-th group, the outputs of the elements And the j-th group and elements AND (2L + j)-th group are connected respectively to the first and second input elements, OR (L + j)-th group, the output of the j-th node of the comparison group connected to the second inputs of elements And j-th group, the elements And the (L + j)-th group, the second (inverse) the inputs of elements AND (2L + j)-th group and the j-th information input group forming unit fault signal, the output of the L-th node of the comparison group connected to the second inputs of elements AND 2L-th group and the L-th information input group forming unit fault signal, the third output of the k-th processing unit connected to the information input of the k-th combinational adder and to the k-th output group of the sign of failure, the outputs of the elements OR (L + j)-th group polka processing, the output of the l-th element And (where l = 1, ..., a) (L + k)-th group is connected to the k-th input l-th element OR 2L-th group, the outputs of which are connected to the l-inputs of the first and second blocks of summation, the outputs (a + 1)-x items And groups with (L + 1) th to 2L-th connected to the inputs of the OR element, the output of which is connected to the control inputs of the first and second blocks of summation, k-th control input of the first group of devices connected to the first deployment entry of the k-th processing unit, the k-th control input of the second group of devices connected to the second installation to the input of the k-th processing unit, the k-th control input of the third group of devices are connected to the third installation to the input of the k-th processing unit, the k-th entry lock device connected to the input block of the k-th processing unit, each processing unit contains the first and second computing nodes, trigger, node comparison, the first to the third element nodes And the element And node elements OR, in each processing unit of the information inputs of the first group, second group, third group, the first control input, a second control input and control inputs of the processing unit are connected respectively to the inputs of the groups of the first node elements And respectively knno to the inputs of the first group of node elements OR the outputs of which are connected respectively to the outputs of the first group, second group, the fifth group, the first and second outputs of the processing unit, the outputs of the second group of the first node elements And connected to the outputs of the third group processing unit outputs the first group to the second node elements And connected respectively to the information inputs of the first, second, and third groups, the first and second control inputs of the first computing node and accordingly to the information inputs of the first, second and third groups, the first and second control inputs of the second computing node, the outputs of the second group to the second node elements And connected respectively to the outputs of the fourth group of the processing unit, the first input set which is connected to the inputs of the installation to its original state of the first and second computing nodes, the outputs of the first, second, and third groups, the first and second outputs of the first computing node connected respectively to the input groups of the third node elements And accordingly to the information inputs of the first node group comparison, information inputs of the second group which are connected respectively to the outputs of the first, second, and third groups, the first and second outputs of the second the host cells OR, the output node of the comparison is connected to the information input trigger, the output of which is connected to the input of the third node elements And to the input of the second node elements And to the inverted input of the first node elements And to the third output of the processing unit, input block and the clock input of which is connected respectively to the first (inverse) and to the second inputs of the element And whose output is connected to the clock inputs of the first and second computing nodes and to the clock input of the trigger inputs installation in the zero and unit which are connected respectively to second and third inputs of the unit of processing.

2. The device according to p. 1, wherein each compute node contains between the first and fifth registers, the first and second triggers, combinational adder, multiplier, first and second groups of elements And the first and second elements And group elements OR, in each compute node information inputs of the first group are connected respectively to the information inputs of the first register, the outputs of which are connected to information inputs of the first multiplier and to the outputs of the second group of compute nodes, the information inputs of the second group of compute node Pollyanna to the first inputs of elements And the first group, the second group and to the outputs of the third group of the computing node, the information inputs of the third group which are connected respectively to the information input of the fifth register, the outputs of which are connected to information inputs of the first group of combinational adder, the outputs of which are connected to the outputs of the first group of compute nodes, the first control input of which is connected to the information input of the first flip-flop and to the first inputs of the first and second elements And the outputs are connected respectively to the inputs of the write-read second and third registers, the output of the first flip-flop connected to the first output of the computing node, the second control input which is connected to the information input of the second trigger, to the second input of the first element And the second (inverted) input of the second element And the output of the second trigger is connected to the second inputs of elements And the first and second groups and to the second output of the computing node, the clock input of which is connected to the inputs of the read/write of the first, fourth registers to the inputs of the synchronization of the first and second triggers, to the third input of the first element And to the third input of the second element And the outputs of the elements And the first and vtoro accordingly to the information inputs of the second multiplier, the outputs are connected respectively to the information inputs of the second group of combinational adder.

3. The device under item 1, characterized in that each block summation includes first and second registers, combinational adder element AND-NOT element And, with each unit summation of information inputs summation block connected to information inputs of the first and second registers, the outputs of which are connected respectively to the information inputs of the first and second groups of combinational adder, the outputs of which are connected to the outputs of the summation block, the control input of which is connected to the first inputs of elements AND and And whose outputs are connected respectively to the inputs of the read/write of the first and second registers, the clock input of the summation block is connected to the second inputs of elements AND and And.

4. The device under item 1, characterized in that the processing unit of refusal contains the element OR NOT, and the member OR, with the information input and information inputs of the group of block signal failure connected respectively to the first input element OR to the inputs of the element OR NOT, the output of which is connected to the second input member OR the output

 

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FIELD: computer science.

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