Cell non-volatile memory and method of programming

 

(57) Abstract:

The invention relates to non-volatile memory and method of programming. The aim of the invention is the creation of a non-volatile memory and method of programming, in which control is carried out simultaneously with multi-level programming. The field programming and control are completely separate. The non-volatile memory cell includes a floating gate, the program area, which has a first current path to the floating gate. Using the invention it is possible to carry out the programming of the filing of the charge carriers in the floating gate electrode along the first path of current or removing charge carriers accumulated in the floating gate. The scope of control has a second current path, separated from the first path of current. Control of the quantity of charge on the floating gate through the second current path when programming. 9 C. and 45 C.p. f-crystals, 18 ill.

The invention relates to non-volatile memory and method of programming non-volatile memory.

The most difficult to overcome the disadvantage of the non-volatile semiconductor memory devices) to the storage medium information verbal the flash EEPROM, is the high cost of memory is based on one bit. To respond to this problem in recent studies have been conducted memory capacity of several bits.

The areal density of conventional volatile memory corresponds in one-to-one with the number of memory cells. The memory cell in a few bits store more than two bits in one memory cell, thereby increasing the data density in the same region of the crystal, without reducing the size of the memory cell.

For memory capacity in a few bits in the corresponding cell should be programmed more than three threshold voltage levels. For example, if each cell is kept case of double-bit data corresponding cell should be programmed for 22, i.e., four threshold levels. There are four threshold level correspond to the logical States 00, 01, 10 and 11, respectively.

In a multi-level program the main problem is that the respective threshold voltage levels have a statistical distribution. The size distribution of about 0.5 V.

Since the distribution decreases due to the precise control of the respective threshold level is. Reducing the stress distribution can be made known programming technique, which uses repeated programming and control.

According to this method, a sequence of voltage pulses is applied to the cell to program the cell to the volatile memory at the appropriate threshold levels. To monitor the achievement of the cell a certain threshold level reads between the respective programmable voltage pulses.

During the monitoring, when scanned threshold level reaches the intended threshold level, the programming stops. This way, repetitive programming and control is difficult to reduce the distribution of error thresholds, because of the limited duration of the voltage pulse programming. In addition, the algorithm is repeated programming and control is carried out by means of additional circuitry which increases the area of the peripheral circuits of the crystal. Moreover, repeating the method lengthens the time of programming. To overcome this limitation, the company "SanDisk Co., Ltd." (the author P. Carnea) was proposed ways is my memory, proposed P. Carnea. As shown in Fig.1,a non-volatile memory cell comprises a control gate is 1, the floating gate 2, source 3, the channel region 4 and drain 5.

Upon application to the control gate 1 and the drain 5 voltage sufficient to initiate the programming current flows between the drain 5 and source 3. This current is compared with a reference current and, when it reaches the value equal to or lower than the reference voltage, generates a signal programming is complete.

The above method is illustrated by using Fig.1,b. According to this known method, the control is automatically performed simultaneously with programming and this compensates for the disadvantages of the method with repetition, in which the programming and control are repeated alternately.

However, in the method of Cernea do not use a separate logic programming to implement programming. In addition, this method does not use tools that allow for the separation of the paths of current programming and path of the current control. For this reason, in the method of Cernea difficult to optimize separately the programming and control. Current programming and current control are not separated and poet of the e programming runs thus, the voltage applied to the respective parts of the memory cell are fixed and the magnitude of the reference current, relevant levels change. In this way, as shown in Fig.1,b, the reference currents detection does not have a clear relationship with the threshold voltage of the cell and are not linear in relation to them.

The structure of the cell of the EEPROM or flash EEPROM can be divided roughly into two parts, depending on the location of the floating gate in the channel region. The first structure is a simple structure layered gate, in which the floating gate electrode completely overlaps the channel region of the cell. The second structure is a structure with split channel, in which the floating gate electrode overlaps only part of the channel region between source and drain.

In the channel area of the portion where the floating gate electrode is not present, is called by the transmitting transistor, which is introduced to avoid problems of excessive erasing. For its size cell with a split channel larger than the structure with a simple multi-level shutter, which is undesirable.

Another classification type flash oinoi polysilicon gate is typically used in a simple layered structure. Triple polysilicon gate is used in the cell with a split channel. Cell EEPROM or flash EEPROM are described in detail in U.S. patent N 5268318. Typically, the third gate in the triple polysilicon gate is erasing and is used only for data Erasure. In the flash EEPROM erasing is performed in groups of blocks composed of multiple cells.

In Fig. 2, presents a diagram of the conventional volatile memory cell with a simple multi-level gate; Fig.2,b - diagram of the conventional volatile memory cell having a structure with a split channel. Fig.2a and b illustrate the procedures for programming and erasing, and also the structure of normal cells volatile memory.

As shown in Fig.2,a, usually the memory cell with the stacked gate includes a control gate 6, the floating gate electrode 7, the source 8, the drain 9, the channel region 10 and the erase gate 11. As shown in Fig.2,b, a normal cell with a split channel includes a control gate 13, the floating gate electrode 14, the source 15 and the drain 16, the channel region 17 and the erase gate 18.

In Fig.2, a and b erase gates 11 and 18 for programming is not needed. Therefore, when programming a conventional cell of Fig.2, a and b have essentially the same structureall through the control gate, electrodes of the source and/or drain, so it is difficult to separate the path of the current programming from the path of the current control memory cell for simultaneous programming and control. Accordingly, it is difficult to directly and effectively control several levels.

The invention is created taking into account the above circumstances and has as its objective the creation of a non-volatile memory and method of programming a nonvolatile memory in which control is carried out simultaneously with multi-level programming, and programming and control are completely separate.

Another objective of the invention is to provide a nonvolatile memory and method of programming the nonvolatile memory, wherein in the multi-level programming of the respective threshold levels are controlled by the voltage applied to the control gate, and the respective threshold levels and voltage respectively applied to the control gate line with respect to each other.

Another aim of the invention is to provide a nonvolatile memory and method of programming the nonvolatile memory, in which the problem too stiansen for compactness.

Additional objectives and advantages of the invention will be set forth in part in the following description, and will partly be obvious from the description, or may be identified in the practical application of the invention. Objectives and advantages of the present invention may be realized and attained by the means and combinations specifically listed in the attached claims.

To achieve the objectives of the invention and in accordance with this invention the non-volatile memory cell in this invention consists of a floating gate; programming, having a first current path to the floating gate for programming by means of a flow of charge carriers in the floating gate electrode through the first current path or by extracting charge carriers accumulated in the floating gate; and a control region having a second current path, separated from the first path of current for controlling the amount of charges of the floating gate through the second current path when programming.

In addition, for the purposes of this invention provides a non-volatile memory cell comprising a floating gate; gate programming for supplying charge carriers in the floating gate electrode in tsei shutter for programming; field-effect transistor including a floating gate, source, drain and channel region between source and drain and controlling the charge carriers supplied to the floating gate during programming.

In addition, to achieve the objectives of the invention for the non-volatile memory cell comprising a control gate, floating gate, the gate of the programming transistor having a threshold voltage and comprising a floating gate, source, drain and channel region between the drain and source, is proposed a method of programming non-volatile memory cell, which consists of the following steps: applying a first voltage to the control gate and the second voltage to the gate of programming to charge carriers for programming was applied to the floating gate electrode with a gate programming and inversion layer formed in the channel region; controlling conductivity of the inversion layer during programming and stop feeding at least one of the voltages of the first and second control gate and a control gate programming, when controlled conductivity reaches a reference value.

Also for the thief, divided into first and second areas; programming field-effect transistor that includes a first region on a portion of the floating gate, a first drain and a common source, channel region between the first drain and a common source and having a first threshold voltage for supplying charge carriers in the floating gate for programming; a control valve for controlling the quantity of charge carriers supplied to the floating gate for programming; and controlling field-effect transistor comprising the second region of the floating gate, excluding the first region, a second drain and a common source, channel region between the second drain and a common source and having a second threshold voltage to control the number of charge carriers supplied to the floating gate during programming.

In addition, to achieve the objectives of the invention for the non-volatile memory cell comprising a control gate, floating gate, is divided into first and second area provided by the programming field-effect transistor including the first floating gate, a first drain, common source and a first channel region between the first drain and a common outlet, and having a first PRA drain and common source, a second channel region between the second drain and a common outlet, and having a second threshold voltage; proposes a method of programming non-volatile memory cell, comprising the following steps: applying a first voltage to the control gate and the second voltage to the first drain, so that the charge carriers for programming was done in the floating gate electrode through the first channel region for programming and the formation of the inversion layer in the second channel region; and controlling the conductivity of the inversion layer during programming and stop feeding at least one of the voltages of the first and second control gate and the first drain, when controlled conductivity reaches a reference value.

The accompanying drawings illustrate the implementation of the invention and together with the description serve to explain the purposes, advantages and principles of the invention.

In Fig. 1, a schematic diagram of conventional non-volatile memory cell;

in Fig. 1 b is a graph explaining the principle of automatic control/programming of a conventional non-volatile memory of Fig. 1, a;

in Fig. 2, a schematic diagram of a conventional anorganizational memory structure with split channel;

in Fig. 3,a block diagram of the non-volatile memory cell according to this invention;

in Fig. 3,b - schematic diagram of the first implementation of the non-volatile memory according to this invention;

in Fig. 4 is a diagram illustrating a programming method using the detection current in accordance with the first embodiment of the invention;

in Fig. 5,a-i - time diagrams of signals present at the respective points of the circuit of Fig. 4;

in Fig. 6 is a block diagram of multilevel programming in accordance with the first embodiment of the invention;

in Fig. 7,a - equivalent schematic diagram of the capacities of non-volatile memory of Fig. 3, b;

in Fig. 7 b is a graph depicting the relationship between the programmable threshold levels and respectively applied to the control gate voltage;

in Fig. 8,a diagram illustrating the procedure for programming in accordance with this invention using a detection voltage according to the first variant implementation of the invention;

in Fig. 8,b - schematic diagram of another variant of implementation of the circuit for detecting voltage according to Fig. 8,a;

in Fig. 9,a first Structorian section of the first structure non-volatile memory along the line A-A in Fig. 9,a;

in Fig. 10,a second structure of the nonvolatile memory in accordance with the first embodiment of the invention;

in Fig. 10, b - cross section of the second structure non-volatile memory along the line B-B in Fig. 10,a;

in Fig. 11,a third structure of the nonvolatile memory in accordance with the first embodiment of the invention;

in Fig. 11, b - cross section of a third structure of the non-volatile memory along the line C-C' in Fig. 11,a;

in Fig. 12,a fourth structure of the nonvolatile memory in accordance with the first embodiment of the invention;

in Fig. 12,b - cross section of a fourth structure of the nonvolatile memory line D-D' in Fig. 12,a;

in Fig. 13, a schematic diagram of the nonvolatile storage device that uses non-volatile memory cell according to Fig. 3,b;

in Fig. 13,b - table of voltages supplied to the respective bus of Fig. 13,a during operation;

in Fig. 14 is a schematic diagram of a second variant implementation of the non-volatile memory according to the invention;

in Fig. 15,a diagram explaining a programming method in accordance with the second embodiment of the invention;

in Fig. 15,b - circuit detector is ATI in accordance with the second embodiment of the invention;

in Fig. 16,b - cross-section structure of the nonvolatile memory at line E-E of Fig. 16;

in Fig. 17 is a schematic diagram of the nonvolatile storage device that uses non-volatile memory cell according to Fig. 14;

in Fig. 18 is a table of voltages supplied to the corresponding lines in Fig. 17 during operation.

The first option

As shown in Fig. 3,a non-volatile memory cell comprises a floating gate, programming, having a first current path to the floating gate for programming the flow of charge carriers in the floating gate electrode through the first current path or removing charge carriers accumulated in the floating gate and the control region, having a second current path, separated from the first path of current to control the magnitude of the charge on the floating gate via the second current path when programming.

As shown in Fig. 3 b, the non-volatile memory cell consists of a floating gate 31, the shutter programming 32 for supplying negative charges (electrons) or positive charges (holes) in the floating gate 31 for multi-level programming, the control gate 33 for supplying voltage to the floating gate electrode 31 amasawa in the floating gate electrode 31 from the shutter 32 for programming programming and transistor 34 to control (or identification) of charges flowing into the floating gate 31 during the multi-level programming. In Fig. 3,b, the transistor 34 includes the floating gate electrode 31, the source 35 and the drain 36 and the channel region 37 between the source 35 and the drain 36.

As shown in Fig. 3 b, the non-volatile memory in accordance with this invention is designed to implement multi-level programming using the third gate programming 32 and to control the programming is complete by checking the number of charges filed in the floating gate electrode 31 in the multi-level programming.

The control gate 33, the floating gate electrode 31, the gate programming 32 can only perform multi-level programming. On the contrary, the transistor 34 may be performed only by controlling the number of charges of the floating gate 31 to the control end or continue programming. The program area is separated completely from the control. These two areas are connected via the floating gate electrode 31. The floating gate electrode 31 and the gate programming 32 related to programming, can be considered as components, forming a tunnel diode. Prog is"ptx2">

As described above, in the prior art do not know the use of shutter programming 32 and as the programming and control are carried out through drain 36 and the channel region 37 of the transistor 34. In this respect the invention differs from the current level of technology.

The following describes the method for multilevel programming of non-volatile memory of Fig. 3, a and b. The programming method in this invention includes the detection voltage and the detection voltage.

First will be explained the detection current. In Fig. 4 shows the first voltage source 38, a second voltage source 39, the third voltage source 40, the fourth voltage source 41, the detector current 42 and the non-volatile memory 100, similar to those shown in Fig. 3. The symbol PSrefers to signal the beginning of the programming coming from external devices. Symbol VSTindicates the stop signal programming.

The first voltage source 38 applies a voltage VC,i(i=0, 1, 2,...,n-1) to the control gate 33 non-volatile memory 100 for programming the i-th threshold level in the multi-level programming. Voltage VC,iPthe shutter 32 for programming multi-level programming. Voltage VPalways has a fixed negative value.

The third voltage source 40 induces a voltage VDto drain 36 for controlling the state of programming, i.e., the drain current ID,i(t), in the multi-level programming. The fourth voltage source 41 applies a voltage VSin the source 35. For example, the voltage VSmay be the voltage of the earth. ID,i(t) denotes the current flowing in the drain 36 at the time (t).

The detector current 42 has a value of threshold current Ithand generates a signal VSTstop programming when the current ID,i(t) flowing through the drain 36, reaches the threshold current Ithwhen programming the i-th threshold level. In other words, the signal VSTstop programming generated when ID,t(t)Ith(at t=tP,i). Time tP,irefers to the time when programming the i-th threshold has been completed. Here the i-th threshold current detector current 42 may be defined by the magnitude of the near-threshold region of the transistor, which may be greater than zero or equal to zero.

Arbitrary reference current IRBFthat is not the ako, if the reference current IREFhas a large value, a large value should have initial voltage on the floating gate 31 VF,i(O) to satisfy the inequality ID,i(O) > IREFat the initial stage of the multilevel programming. In addition, to increase the initial voltage VF,i(O) must be also increased the voltage VC,i.

Current ID,i(t) indicates the amount of current flow 36, due to the voltage VF,i(t) on the floating gate 31 when programming the i-th level. The magnitude of the current is greatest at the initial stage of the programming and decreases during programming. When the reduced value reaches the value of the ith threshold current detector current 42, the detector current generates a signal VSTstop programming.

In accordance with the above condition multilevel programming with detection of current flow will be described with reference to Fig. 4, 5, a-i and 6. Fig.5, a-i illustrates a timing chart of signals at respective points in Fig. 4. In Fig. 6 presents a flowchart of the algorithm, illustrating a two-level or multi-level programming, according to that izobreteniya mean zero, i.e., the lowest. This alternative implementation described assuming that the FET floating gate has an n-type channel formed on the substrate is p-type. Of course, you may apply field-effect transistor floating gate, which uses the channel p-type substrate n-type. In this case, if the supplied voltage is set with opposite polarities and their respective voltages and threshold voltages reversed values, you can perform the same steps as in the previous case.

First, when the external signal PSstart programming, as shown in Fig. 5, a, is fed to begin implementing multi-level programming, a positive voltage VC,iset for programming the i-th level.

When the signal PSstart programming, Fig. 5, a positive voltage VC,iFig. 5, b and a negative voltage VpFig. 5, c and serves on the control gate 33 and the shutter programming 32 respectively from the first and second voltage sources 38 and 39. Then tunneling voltage Vtun,i(t) Fig. 5, g is supplied between the gate programming 32 and plavusa 31 from shutter programming 32. After application of the VC,iand Vpthe detector current 42 is enabled to control the changes of charge in the floating gate 31.

As shown in Fig. 5, d, the voltage VF,i(t) for programming the i-th threshold level supplied to the floating gate 31, and a channel region 37 of the FET 34 is formed inversion layer. Because the source 35 and the drain 36 and the channel region 37 located in the semiconductor substrate, when forming the inversion layer currents flowing from the drain 36 in the source 35 through the channel region 37. Voltage are served from the third and fourth voltage source 40 and 41, causing the tension drain VDand the voltage source VSinduced in the drain 36 and the source 35, respectively. Here the current ID,i(t) flows through the drain 36. As shown in Fig. 5, e, current ID,i(t) at the initial stage has the largest value and decreases in the programming process, because the electrons injections in the floating gate electrode to lower the voltage of the floating gate.

During programming of the i-th threshold level detector current 42 controls the drain current ID,i(t). When this value reaches the value of the i-th threshold voltage, as depicted in Fig. 5,e, programs Above explained, the detector current 42 controls the current ID,i(t) on the drain 36. However, you can also say that the detector current 42 controls the change of the voltage and charge on the floating gate 31 during programming (Fig. 5,d). The control current ID,i(t) can be considered as controlling the conductivity of the inversion layer formed in the channel region 37.

In Fig. 4 signal VSTstop programming is applied to the first and second voltage sources 38 and 39. The first and/or second voltage sources 38 and 39 stop applying a positive voltage VSTand negative voltage VPthe control gate 33 and the shutter programming 32 in response to the signal VSTstop programming, as shown in Fig. 5,b and c. When it is detected that the current ID,i(t) was below the threshold current Ithat that moment, when t = tP,ithe programming of the i-th threshold level is completed. Time tP,ishows when programmed i-th threshold level. The I-th threshold current is set in advance as a value, mainly corresponding to the threshold voltage VFTNin the floating gate 31. The threshold voltage Vth is defined for an arbitrary value of Iththreshold current.

In other words, in Fig. 3 for the reason that the FET 34 is formed with a floating gate 31, the inlet 35 and the outlet 36, the threshold voltage VFTNbasically corresponds to the threshold voltage of the channel region 37. It should be noted that the programming of any threshold level is completed when the voltage of the floating gate reaches the value VFTN. This is a sign that this invention differs from conventional technologies. Fig. 5, h, is a graph depicting the threshold voltage VCTN,1and VCTN,2in the control gate 33, which belong to the first and second threshold levels, respectively. In Fig. 5,h, threshold voltage VCTN,1on the control gate 33 is increased by increasing the level of programming in the multi-level programming. This is done by increasing the voltage VC,iwhen programming. Here the time tp,1and tp,2the first and second levels are different for the reason that the offset voltage of the control gate and the threshold voltage of the respective different levels.

Fig. 5, i - a graph depicting the magnitude of the change for Rhino programming the first threshold level, and to a value of QF,2(tp,2) when finished programming the second threshold level, in the case when the i-th threshold levels correspond to the first and second levels. In Fig.5, i it should be noted that, when the voltage VF,1(t) and VF,2(t) on the floating gate 31 reaches the threshold voltage VFTN(t=tp,lt=tp,2), the amount of charge in the floating gate 31 c increases the initial value of QF,0(0) to a value of QF,1(tp,1and the value of QF,2(tp,2).

With reference to Fig. 7,a explain the relationship between voltage Vc,iattached to the control gate 32 from the first voltage source 38, and the threshold voltage at an appropriate level, which is a significant result of the present invention. In Fig. 7,a designation Ccrepresents the capacitance between the control gate 33 and the floating gate 31; Cprepresents the capacity between the gate programming 32 and floating gate 31, CDrepresents the capacitance between the drain 36 and the floating gate 31, and Csrepresents the capacitance between the source 35 (including the substrate) and a floating gate 31.

The amount of CTthese containers can be expressed in sootvetstvujushij capacities determined by the following equations (2):

aC= Cc/CT, aP= CP/CTand aD= CD/CT... (2)

In Fig. 7, a voltage on the floating gate 31 when programming can be expressed by the following equation (3):

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where

QF(t) denotes the amount of charge in the floating gate 31. In equation (3) assumes that the source and substrate are grounded.

When programming the threshold voltage VCTH(t) on the control gate 33 is defined by the following equation:

< / BR>
In other words, equation (4) VCTH(t) denotes the shift of the threshold voltage measured at the control gate 33 at time t. The shift of the threshold voltage refers to the threshold voltage measured at the control gate and is caused by the charges accumulated in the floating gate.

The threshold voltage VCTH(t) measured at the control gate 33, is defined as the voltage of the control gate 33, when the drain current ID(t) reaches the threshold current Iththe voltage detector 42. The threshold current Ithmay be arbitrarily defined above. For example, the current Ithcan be equal to 1 mA.

The threshold is a mere field-effect transistor, consisting of a floating gate 31, the source 35 and the drain 36 of Fig. 3, which is determined by such conditions of production, as a channel ion implantation and the thickness of the isolation gate in the manufacture of the nonvolatile memory 100 in Fig.3. Therefore, the threshold voltage VFTHthe floating gate 31 is always constant. The threshold voltage VCTHthe control gate 33 is determined by the magnitude of the charge QFin the floating gate 31.

As mentioned above, the programming at the appropriate levels is stopped when the voltage VF(t) on the floating gate 31 is lowered until then, until it reaches the value of the threshold voltage VFTH. This point corresponds to the time when the current ID(t) drain 36 reaches the threshold current Ithand time tFwhen completed programming. When programming the respective threshold voltage levels VF(tP) floating gate 31 at the completion of programming can be expressed by the following equation (5):

VF(tP)=VFTH=aC[VC-VCTH(tP)]+aPVP+aDVD(tP)... (5)<33 from the first voltage source 38, gives the following equation (6):

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where

V1is determined by the following formula:

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It is important that the value of V1at time t = tPdetection is relatively constant voltage VC,ithe control gate at the appropriate levels.

The value of V1is determined by the tension drain VD(tp) when t = tpvoltage Vpattached to the shutter programming 32, and parameters such as VFTH, aC, aDand aPthat are defined in the manufacturing process. The circuit can be designed in such a way that the tension drain VDwill be constant. Values of aDand VDrelatively small in relation to other members. When programming the corresponding threshold voltage VD(tP) when programming has been completed (when t=tP) is a constant.

Using equation (6) voltage VC,ithe control gate 33, required for programming the i-th threshold level can be expressed by the following equation (7):

VC,i=VCTH,i+V1... (7)

where

i=0, 1, 2, 3, ... , n-1.

And is engaged in the shutter have a linear dependence with slope, equal to 1. In Fig. 7,b shows this result. Similarly, according to equation (4), the amount of charge in the floating gate are linear with respect to voltage of the control gate.

Since the value of V1as described above, the constant, the i-th shift VC,ithe voltage applied to the control gate 33 in the multi-level programming, can be expressed by the following equation (8):

VC,i=VCTH,i... (8)

According to equations (7) and (8), when in the multi-level programming is determined by the shift VCTH,ifrom the erase state (i.e., low level) to one of the appropriate level thresholds, the programming of the appropriate level can be accomplished by application to the control gate voltage corresponding to a shift of the threshold level VCTH,ifolded with the known value of VC,0programming low level; then you need to wait for the automatic programming is complete.

As shown in Fig. 5, g when programming the appropriate level voltage tunneling Vtun,iattached between the floating gate 31 and the shutter 32 for programming the tunnels of this threshold voltage VFTHin the floating gate 31, that is, when completed programming.

Max Vmaxtunitunneling voltage can be expressed by the following equation (9) as the difference between the initial voltage VF,i(0) floating gate 31 and the voltage VPattached to the shutter programming 32.

< / BR>
In equation (9), if the magnitude of the initial charge QF(0) floating gate 31 is equal to zero, equation (9) can be rewritten as the following equation (10)

Vmaxtuni= aCVC,i+(aP-1)VP+aDVD(0)... (10)

Still taught description multilevel programming. The erase process using non-volatile memory according to Fig. 3 will be lower.

Erasing is performed by applying a voltage to the respective components to create between the floating gate and the source, drain or channel region, the electric fields of sufficient strength to erase the charge carriers accumulated in the floating gate. Thus, the charge carriers are erased on the source, drain or channel region by tunneling. In this invention erased state means lower threshold brovarnia are programmed at the lowest level. Erasing is performed according to the stages outlined below.

First, the threshold levels of all cells in the selected block are erased, so that they become "below zero", i.e. VCTH,0. Then, having zero level, in which the voltage of the control gate 33 is equal to VC,0all the selected cells are programmed. Here the value of VC,0can be fixed arbitrarily. Erasing is performed basically according to the method of programming, thereby eliminating the problem of excessive erasing. Finally, the requirements for the voltage VC,ithe control gate 33 and the voltage VPshutter programming 32 required for programming the i-th threshold level, are as follows.

In order to control the change of the charge in the floating gate during programming, the voltage VC,ishould be applied so that at the initial stage of programming the channel of the transistor shown in Fig. 4, was inverted to reduce the flow of current flow and the conductivity of the inversion layer (when programming). For this purpose shall be satisfied the following equation (11):

VF,i(0) > VFTH, ID,i(0) > Ith(11)

Values V

The value of VPis a fixed negative value, so that the tension of the tunneling electric field increases when the value of VC,ibecomes high. Programming speed also increases with shear VCTHthe threshold voltage of the control gate 33.

So the above was described programming method based on the detection current.

Next with reference to Fig. 8 will be explained a method of programming based on the detection voltage. The programming method based on the detection voltage is basically the same as programming on the basis of the detection current.

The scheme of Fig. 8 explains the programming of the present invention, by using the detection voltage. Fig. 8 is basically identical to Fig. 4, with the exception of the voltage detector 43, which is used instead of the detector current 42 in Fig. 4.

The voltage detector 43 may be formed by a source of reference voltage 44 and a resistor 45 connected between the source of reference voltage 44 and the outlet 36. Resistor 45 can be replaced by a diode and those who t the tension drain 36 when programming. During the monitoring, when the voltage VF,ithe floating gate 31 reaches the threshold voltage VFTHand if the detected voltage drain VD,THthen output the signal VSTstop programming. The value of VD,THis constant relative to the programming level.

As in the method of detecting the current programming is completed, when in response to the signal VSTstop programming the first and/or second voltage sources 38 and 39 are cut off voltage VC,ithe control gate and the voltage VPshutter programming.

Other components are essentially the same as in method with detection current, and they will not be described.

As shown in Fig. 9,a and b, the first version of the implementation structure of the nonvolatile memory accordingly the invention includes a semiconductor substrate 50 of the first conductive type, having on its surface channel region formed on the channel region, the floating gate electrode 51 is formed over the floating gate 51 and the control gate 52 formed in contact with the floating gate 51, the shutter programming 53 and formed between the gate prolabium shutter 51 and the shutter programming 53 thin enough to implement tunneling between them.

Referring to Fig. 9, a and b, you can see that the insulation protective oxide layer 55 is formed on the surface of the substrate 50 that surrounds the channel region. Part of the floating gate 51 goes to the surface of the insulating protective oxide layer 55. In Fig. 9, b shutter programming 53 is placed near one side of the control gate 52. An insulating layer of gate 56 is formed thin enough to implement tunneling between the channel region and a floating gate 51.

As shown in Fig. 10, a and b, the second option exercise patterns corresponding to the invention, similar to the first. In this embodiment, the portion of the bolt programming 53 is placed next to the bottom surface of the floating gate 51. Referring to Fig. 11, a and b, a third option exercise patterns corresponding to the invention, shown in Fig. 11, a and b, similar to the first. In this third embodiment, the shutter programming 53 is placed on top of the floating gate 51.

In Fig. 12, a and b presents the fourth variant of the structure of the nonvolatile memory corresponding to this invention, containing a semiconductor substrate 50 of the first conductive type having a channel region on its own is the first conductive type, on each side of the channel region in the surface of a semiconductor substrate; formed over the floating gate 51 and the control gate 52; placed next to the floating gate 51, the shutter programming 53 and the insulating layer 54 formed between the floating gate 51 and a floating gate 52. The insulating layer 54 between the floating gate 51 and the shutter programming 53 thin enough that you can make between tunneling. Insulating protective oxide layer 55 surrounds the channel region. The insulating gate film 56 is formed thin enough to implement tunneling between the channel region and a floating gate 51.

As shown in Fig. 13, a nonvolatile memory device according to this invention comprises a semiconductor substrate 60, many code tire 61 located with the division by the specified distance on the substrate 60; set bit buses 62, perpendicular to code the tire and forming many squares or rectangles, which are located at intervals with a specified distance; many programming tires 63 located in the same direction, the corresponding bit bus; and multiple cells Energon Fig. 13, a, as shown in Fig. 3, each of the nonvolatile memory cells 64 consists of a floating gate 65, the shutter programming 66 for supply for programming purposes, of charges in the floating gate electrode 65, a control gate 67 to control the number of charges filed for programming the floating gate electrode 65, and a field-effect transistor 68 to read (or control) of the quantities of charge carriers supplied during programming, the floating gate electrode 65. Field-effect transistor 68 is composed of the floating gate 65, the source 69, drain 70, the channel region 71 between the source 69 and the outlet 70.

The control gate 67 of the respective memory cells connected to the nearby code bus 61, and the gate programming 66 is connected to the nearby programming bus 63. Source 69 memory 64 is typically connected to a nearby bit bus 62 with the flow 70 cell non-volatile memory 64, located in a nearby or adjacent square.

As shown in Fig. 13 b, when the non-volatile memory device operates in the programming mode, the voltage 8-15 B is served in the selected programming bus 63, 0 B - in unselected programming bus 63, 3-12 B - selected codony 62, to the left, for example, from the selected cell of 0.5-2 B - in more than one bit of the bus is located, for example, to the right of the selected cell, and 0 V on the substrate 60.

When non-volatile storage device is in erase mode, voltages are applied in two ways.

First, to erase the bit buses 62 voltage 0-12 B is served on all the programming bus 63 selected block erase, 7 - 12 B - all code bus 61 selected block erase, 0-6 B - all bit bus 61 selected block erase and 0 B - on a substrate 60.

To erase the through substrate 60 voltage 0 - 12 V is supplied to all the programming bus 63 selected block erase, 7 - 12 B - all code bus 61 selected block erase. The bit outputs of the tire 62 of the selected block are transferred to the third state. Voltage 0-6 B is supplied to the substrate 60.

When the non-volatile memory device operates in the read mode, a voltage of 0 V is supplied to the programming bus 63, the supply voltage VCC- on the selected code bus 61, 0 B - unselected code bus 61, 0,5-2 B - selected bit bus 62, 0 B - unselected bit bus 62, is placed, for example, left; 0,5-2 B - on time is, 13, b may change the structural characteristics electrical characteristics of the memory cells, for example, the coupling coefficient or the thickness of the insulator tunnel.

The second option exercise

What follows is a description of the second variant implementation of the cell and the non-volatile memory device made according to this invention, and method of programming with reference to Fig. 14, 15, a, b, 16, a, b, 17 and 18.

As shown in Fig. 14, the nonvolatile memory comprises a floating gate 81, divided into the first area 81a and the second area 81b; programming field-effect transistor that includes the first region 81a floating gate 81, the first drain 82 and the common source 83, a channel region between the first drain 82 and a common source 83, and having a first threshold voltage VFTH1for supplying charge carriers in the floating gate 81 for programming; a control gate 84 for supplying voltage to the floating gate through capacitive coupling between the floating gate and control gate to control the number of charge carriers supplied for programming the floating gate electrode 81; and controlling field-effect transistor including the second area 81b PL is the current 85 and a common source 83, and having a second threshold voltage VFTH2to check the number of charge carriers, filed in the floating gate 81 when programming. In the circuit of Fig. 14 the second threshold voltage VFTH2exceed the first threshold voltage VFTH1.

As shown in Fig. 14, in contrast to the first variant of the second variant of implementation of the non-volatile memory cell according to this invention has no shutter programming and instead, there are three areas dopant (drain control transistor, the common source and the drain of the programming transistor) on the surface of the substrate.

In addition to the components in Fig. 14, the memory of Fig. 15,and includes a first voltage source 88 for applying voltage to the control gate 84, the second voltage source 89 to the supply voltage VPDon the first drain 82 programming field-effect transistor for programming, the third voltage source 90 for feeding to a common source 83 voltage VSthat is lower than or equal to the voltage VPDsupplied to the first drain 82; and the detector current 91A to detect the current ID,i(t), which flows through the second the key programming on the respective voltage sources 88, 89 and 90, when proyektirovanii the current reaches a given value of the threshold current Iththis signal interrupts the supply voltages VC,i, VPDVS. In Fig. 15,and the common source 83 is grounded on a substrate (not shown).

In Fig. 15, and the voltage VC,isupplied to the control gate 84 from the first voltage source 88 is positive and varies according to the programming of the corresponding threshold level in a hierarchical programming. Voltage VPDserved in field programming transistor from the second voltage source 89 is positive. The detector A in Fig. 15,and can be replaced by voltage detector 91B in Fig. 15, b.

As follows from Fig. 15,and, in addition to the components in Fig. 14, the non-volatile memory cell in addition to the above includes the first voltage source 88 to the supply voltage VC,ithe control gate 84, the second voltage source 89 to the supply voltage VPDon the first drain 82 programming field-effect transistor for programming, the third voltage source 90 for feeding to a common source 83 voltage VSthat is lower than or equal to the voltage VPD, applied to the funding and for the signal VSTstop programming the first and second voltage sources 88 and 89, when the controlled voltage VMDi(t) of the second drain 85 reaches a given reference voltage VD,THto trim the voltage VC,iand VPD.

Even when the voltage detector 91B in Fig. 15,b is used instead of the detector current 91A in Fig. 15,and the voltage VC,isupplied to the control gate 84 from the first voltage source 88 is positive and varies according to the programming of the corresponding threshold level in a multilevel programming. Voltage VPDsupplied to the first drain 82 programming field-effect transistor from the second source voltage 89, is a positive voltage in the programming, using the mechanism of the hot injection of carriers. As shown in Fig. 15,b, detector 91B can be configured with a voltage source VDDto induce a voltage in the second drain 85 and a resistor connected between the source voltage VDDand the second drain 85 controlling field-effect transistor.

Voltage VPis set to the value smaller or equal to zero (0), and the programming field-effect transistor instead of the shutter programming.

In the non-volatile memory cell comprising a control gate 84; floating gate divided into first and second areas 81a and 81b; programming field-effect transistor having a first threshold voltage VFTH1and including the first region 81a floating gate 81, the first drain 82, a common source 83 and the first channel region 86 that is located between the first drain 82 and a common source 83; and controlling field-effect transistor having a second threshold voltage VFTH2and including the second area 81b floating gate 81, the second drain 85, a common source 83; and a second channel region 87 between the second drain 85 and a common source 83, the method of programming for the second variant of implementation of the non-volatile memory cell, according to this invention, includes the following steps: applying a first voltage VC,ithe control gate 84 and the second voltage VPDon the first drain 82, resulting charge carriers arrive at the floating gate electrode 81 through the first channel region 86 for programming and inversion layer is formed in the second channel region, 87; and controlling the conductivity of the inversion layer at programmera theDon the first drain 82, when controlled conductivity reaches a reference value.

In Fig. 14, 15,a and b, the supply of charge carriers in the floating gate electrode 81 of the first channel region 86 for programming can be done by hot injection of carriers or tunneling, Fowler-Norheim (KHF is no). In the case of programming using a tunneling mechanism the voltage applied to the first drain, less than or equal to zero, and the voltage applied to the common source, is equal to the voltage of the first drain.

As shown in Fig. 16,a and b, the non-volatile memory cell comprises a semiconductor substrate 92 of the first conductive type (P-type), the first dopant region 93 of the second conductive type (n+), the second dopant region 94, the third dopant 95, sequentially formed on the substrate surface 92 spaced at specified distances, the first insulation layer 98 shutter on the first and second regions 93 and 94 of the dopant on the substrate 92, a second insulating layer 99 shutter on the second region 94 dopant and the third area 95 dopant, the thickness of which is different from the thickness of the first insulating slay impurities on the surface of the substrate 92, the second channel region 101 defined by the area between the second and third regions 94 and 95 dopant on the surface of the substrate 92; floating gate 96 formed on the first and third regions 93 and 95 dopant on the first and second insulating layers 98 and 99 of the gate; a control gate 97 is formed over the floating gate 96; and a layer 102 of insulation, and the insulation layer 102 is formed to isolate the floating gate 96 to the control gate 97.

Here, as shown in Fig. 16 b, the second insulating layer 99 shutter thicker than the first insulating layer 98 shutter. The first insulating layer 98 of the shutter defined thin enough that carriers could be erased in the first channel region 100 from the floating gate 96 through tunneling.

Although in Fig. 16,a and b is not shown in detail, the field insulating layer 103 is formed on the surface of the substrate 92, excluding the first insulating layer 98 shutter and the second insulating layer 99 shutter. In Fig. 16,a and b, the floating gate electrode 96 is formed on the first and second channel regions 100 and 101. Part of the floating gate 96 goes to the surface of the insulating layer 103.

As shown in Fig. 17, the non-volatile memory wadenya distance; set bit buses 105 of the second conductive type, located perpendicular to code the tire 104 and thereby forming many squares or rectangles spaced at specified distances; tire 106 common source, dividing the appropriate squares and rectangles in the same direction as bit bus 105, the left and right pane, between the bit busses 105; and an array of nonvolatile memory cells having a control gate 84, the floating gate electrode 81, divided into first and second areas 81a and 81b, the programming field-effect transistor, which is, for example, to the right of the squares and the input charge carriers in the floating gate electrode 81 for programming and controlling field-effect transistor, which is, for example, to the left of the squares and controlling the number of charge carriers floating gate 81 when programming. Programming field-effect transistor includes a first region 81a floating gate 81, the first drain 82, the total flow 83 and the first channel region 86 between the first drain 82 and a common source 83. Controlling field-effect transistor includes a second region 81b floating gate 81, the second drain 85, the total flow of 83, the second channel region 87 between the second drain 85 and a common source 83. The first drain 82 is connected to the adjacent bit bus 105 with the second drain 85 non-volatile memory, in the square, for example, the right of the first drain and the second drain 85 is connected to the first drain 82 non-volatile memory in the square, for example, to the left of the second drain 85.

The non-volatile memory device of Fig. 17 operates in the programming mode using the mechanism of hot injection of carriers. As shown in Fig. 18, a voltage of 6 - 13 B can be attached to the selected code bus 0 V to unselected code bus, 5 - 9 B - to the selected n-th bit bus, 0,5 - 2 B - selected (n - 1)-th bit bus, 0 B - other bit bus, 0 V to the selected n-th bus of the source; and conclusions unselected (n + 1)-th bus of the source are transferred to the third state, the unselected (n-1)I tire of the source is equal to the selected (n-1)-th bit bus; and O (B - to the substrate. When the non-volatile memory device operates in the programming mode using the tunneling mechanism, the operating voltage of 10 - 20 B is attached to the selected code bus, O B - to unselected bus, O B - to the selected n-th bit bus, 5 - 10 B - other bit tyres, O B - to the selected n-th bus of the source, 5 - 10 B - other tyre source and O B to the substrate.

When the nonvolatile storage device according to Fig. 17 operates in the erase mode, the voltage revogada in the third state, VCCattached to all tires of the source and O B to the substrate.

When the nonvolatile storage device according to Fig. 17 operates in the reading mode, VCCcan be attached to the selected code bus voltage O B - to unselected code bus voltage from 0.5 B to 2 B to the selected n-th bit bus, O B - other bit tyres, O B - all tire source and O B to the substrate.

Voltage according to Fig. 18 you can change the structural characteristics or electrical parameters of the memory cells, for example, the coupling coefficient or the thickness of the tunnel insulator.

As indicated above, this invention has advantages in the following respects.

First, the programming of the corresponding threshold level is performed only by changing the voltage of the control gate, resulting in a facilitated multi-level programming.

Secondly, the respective levels of the threshold voltage and the corresponding voltage of the control gate line, and the shift of the threshold voltage coincides with a shift voltage of the control gate, just by adjusting the offset of the respective voltage threshold level.

Thirdly, the state of stirnerite which the problem of excessive erasing eliminated.

Fourthly, programming and control are carried out simultaneously in the non-volatile memory cell, without requiring a separate scheme for control of programmed content and accelerating the speed of programming.

Fifthly, before erasing pre-programming is not necessary.

Sixth, requires low voltage - 12B below.

Seventh, to control only requires a small current of less than a few fractions of tenths or 1mA.

Eighth, the non-volatile memory cell is constructed as a simple multi-level gate, and not split the channel, making it more compact.

Ninth, the accuracy of multilevel programming, i.e. the distribution of errors of programming threshold voltage, accurately determined only by the parameters recorded during the manufacture of the nonvolatile memory, and the applied voltage bias. For this reason, the distribution of errors of the respective levels of non-volatile memory of the present invention does not depend on a large number of cycles programming/erasing. Even during programming the memory does not depend on the capture of charges in the oxide layer, p is tov.

Tenth, in the method of programming a nonvolatile memory according to this invention is controlled by a voltage, thus this method performs multilevel programming easier and more accurate than the method with the control current.

Eleventh, the non-volatile memory device according to this invention implements a matrix with contactless virtual ground using simple multi-level structure of the shutter, instead of asymmetric cells, similar to the structure of the split channel, considerably reducing the size of the crystal.

In the twelfth, the source and the drain of the nonvolatile memory according to this invention is used only in the reading, with the application of low voltage required to read-only on the source and drain. Thereby optimized diffusion region of the source and drain.

The above description of preferred embodiments of the invention are given for purposes of illustration and description. His goal is not an exhaustive description or the exact limitation of the invention disclosed here; modifications and variations are possible in light of the above explanations, or about the yli chosen and described to explain the principles of the invention and its practical implementation, to the person skilled in the art could utilize the invention in various implementations and with various modifications as applied to specific cases of its use. It should be borne in mind that the scope of the invention defined by the claims and its equivalents.

1. Cell non-volatile memory containing a floating gate, the program area and the area of the control, wherein the program area has a first current path to the floating gate for programming the filing of the charge carriers in the floating gate electrode in the specified path current or extraction of charge carriers accumulated in the floating gate, and the scope of control has a second current path, separated from the first path of current, to control the amount of charge on the floating gate through the second current path when programming.

2. Cell under item 1, characterized in that the program area includes a tunnel diode, and the scope of monitoring includes field-effect transistor.

3. Cell under item 1, characterized in that the program area includes a first field-effect transistor, and the control includes a second field-effect transistor.

4. Cell EnergoData the drain, characterized in that it contains the shutter programming for supplying charge carriers in the floating gate for programming and above the floating gate electrode, source, drain and channel region to form a field-effect transistor for controlling the charge carriers are supplied when programming the floating gate.

5. Non-volatile memory device with a cell under item 4, characterized in that it contains the first voltage source for applying voltage to the control gate, a second voltage source for supplying voltage to the gate of the programming, the third voltage source for applying voltage to the drain, a fourth voltage source for supplying a source voltage lower than the voltage applied to the drain, and the detector current for detecting current flow during programming and to signal stop programming on one of the first and second voltage sources, when the value prodeklarovanoho current reaches the value specified reference current for disabling at least one of the specified voltage.

6. The device under item 5, characterized in that as a given reference current selected threshold current of the FET.

7. is the voltage of the earth.

8. The device under item 5, characterized in that the voltage applied to the control gate from the first voltage source is a positive value, which changes according to the programming of the corresponding threshold level in the multi-level programming, and the voltage supplied to the gate of the programming from the second voltage source is a fixed value less than zero.

9. The unit cell under item 4, characterized in that it contains the first voltage source for applying voltage to the control gate, a second voltage source for supplying voltage to the gate programming voltage detector for monitoring the voltage of the drain during programming and to signal stop programming on one of these voltage sources when predetection voltage runoff reaches the reference voltage, resulting in disconnects at least one of the voltage of the specified source.

10. The device according to p. 9, characterized in that the reference voltage is selected, the threshold voltage of the FET.

11. The device according to p. 9, characterized in that the voltage applied to the charge is Mirovaya corresponding threshold level in the multi-level programming, and the voltage supplied to the gate of the programming from the second voltage source is a fixed value less than zero.

12. The device according to p. 9, wherein the voltage detector includes a voltage source to induce a voltage on the drain, and a resistor connected between the voltage source and the drain.

13. The device according to p. 9, wherein the voltage detector includes a voltage source to induce a voltage on the drain of the diode connected between the specified source of reference voltage and drain.

14. The method of programming the non-volatile memory cell comprising a floating gate, a control gate, the gate of the programming transistor having a threshold voltage and comprising a floating gate, source, drain and channel region between the drain and source, which are feeding the first and second voltages to the corresponding elements of the cell, characterized in that the supply of the first voltage is carried out on the control gate, and applying a second voltage sustain the shutter programming causing charge carriers to programming served in the floating gate electrode from ZAT is vodnosti inversion layer during programming and stop feeding at least one of the specified first voltage to the control gate and the second voltage to the gate of the programming, when controlled conductivity reaches a reference value corresponding to the threshold voltage of the transistor.

15. The method according to p. 14, characterized in that the reference value is chosen threshold value of the transistor.

16. The method according to p. 14, wherein the first voltage is a positive value, which changes according to the programming of the corresponding threshold level in the multi-level programming, and the second voltage is a fixed negative value.

17. Non-volatile memory device containing a semiconductor substrate of the first conductivity type having a channel region on its surface, a floating gate formed on the channel region, and a control gate formed over the floating gate, characterized in that it contains the shutter programming, placed next to the floating gate, for supplying charge carriers in the floating gate during programming and an insulating layer formed between the gate programming a floating gate and control gate, and the specified insulating layer between the floating gate and the gate of the programming is then contains an insulating layer, formed on the substrate surface surrounding the channel region.

19. The device under item 18, characterized in that the portion of the floating gate passes to the surface of the insulating layer.

20. The device under item 17, characterized in that the shutter programming formed near the side of the floating gate.

21. The device under item 17, characterized in that the shutter programming formed over the floating gate.

22. The device under item 17, characterized in that the shutter programming formed near the bottom of the floating gate.

23. The device under item 17, characterized in that it contains an insulating layer of gate formed between the channel region and a floating gate, thin enough to implement between the tunneling effect.

24. Non-volatile memory device containing a lot of code tires, located at a specified distance, a lot bit of tyres in the second type of conductivity perpendicular to code the tire and arranged with a specified distance with the formation of multiple rectangles, many programming tires that are parallel to the corresponding bit buses, and many used the store shutter, a control gate connected to one of the code of tires, the source, drain and channel region between source and drain, wherein each of the nonvolatile memory cells includes a gate programming, coupled with one of the programming tires to supply charge carriers in the floating gate for programming and above the floating gate electrode, source, drain and channel region to form a field-effect transistor for reading or control the number of charge carriers supplied to the floating gate during programming, the source is connected to one bit of the tire with the flow cell non-volatile memory located in the rectangle adjacent to the specified source, and a drain connected to one bit of the tire together with the source cell non-volatile memory located in the rectangle adjacent to the specified flow.

25. The device according to p. 24, wherein when in the programming mode voltage (-8) - (-15)is applied to the selected programming bus, 0V to the unselected programming bus, 3 - 12V - to the selected code bus, 0 - (-10)to unselected code bus, 0.5 to 2V - selected bit bus, 0V to the unselected bit tyres, located Etivoprosy specified first side, and 0V to the substrate.

26. The device according to p. 24, wherein when in the erase mode by bit bus voltage 0 - (-12)attached to the selected programming tyres, (-7) - (-12)to the selected code tyres, 0 - 6V to the selected bit buses, and 0V to the substrate.

27. The device according to p. 24, wherein when in the erase mode by substrate voltage 0 - (-12)is applied to the selected programming bus, and (-7) - (-12)to the selected code to the tire, the selected bit bus converted into a floating state, and a voltage of 0 - (-6)is applied to the substrate.

28. The device according to p. 24, wherein when in the reading mode voltage 0V is applied to the programming tires, 1 - 6V to the selected code bus, 0V to the unselected code tires, 0.5 to 2V - selected bit bus, 0V to the unselected bit bus on the first side of the selected cell, 0,5 - 2B - multiple bit bus on the second side of the selected cell, specified opposite the first side, and 0V to the substrate.

29. Cell non-volatile memory containing a floating gate, a control gate to control the number of charge carriers supplied to the Yu between the first drain and a common source characterized in that the floating gate electrode is divided into first and second areas mentioned first region of the floating gate, the first drain, common source and the first channel region to form a field-effect transistor to be programmed with the first threshold voltage for supplying charge carriers in the floating gate for programming, with said cell further comprises a field-effect transistor for control, which includes the above-mentioned second region of the floating gate, a second drain, referred to a common source and a second channel region between the second drain and a common source and having a second threshold voltage to control the number of charge carriers, supplied to the floating gate during programming.

30. Cell under item 29, wherein the second threshold voltage is greater than a specified first threshold voltage.

31. Non-volatile memory device with a cell on p. 29, characterized in that it contains the first voltage source for applying voltage to the control gate, a second voltage source for applying voltage to the first drain of the field-effect transistor for programming, the third voltage source for feeding to a common source voltage, IU whom it through the second flow field-effect transistor to control the programming and to signal stop programming at the specified voltage when the value prodeklarovanoho current reaches the set value of the reference voltage, to disconnect the voltage of the first, second and third voltage sources.

32. The device according to p. 31, characterized in that the set value of the reference current selected threshold current FET to control.

33. The device according to p. 31, wherein the common source is grounded to the substrate.

34. The device according to p. 31, characterized in that the voltage applied to the control gate from the first voltage source is a positive value, which changes according to the programming of the corresponding threshold level in the multi-level programming, and the voltage applied to the field-effect transistor for programming from the second voltage source is a positive value.

35. The device according to p. 31, characterized in that the voltage applied to the control gate from the first voltage source is a positive value, which changes according to the programming of the corresponding threshold level in the multi-level programming, and the voltage applied to the field-effect transistor for programming from Deuteronomy is different, however, that contains the first voltage source for applying voltage to the control gate, a second voltage source for applying voltage to the first drain of the field-effect transistor for programming, the third voltage source for feeding to a common source voltage, smaller or equal to the voltage supplied to the first drain, and a voltage detector for monitoring the voltage of the second drain during programming and to signal stop programming the first and second voltage sources when the controlled voltage of the second flow reaches a predetermined set voltage, to turn off voltages of the first and second sources of voltage.

37. The device according to p. 36, characterized in that the voltage applied to the control gate from the first voltage source is a positive value, which changes according to the programming of the corresponding threshold level in the multi-level programming, and the voltage supplied to the first flow field-effect transistor for programming from the second voltage source is a positive value.

38. The device according to p. 36, characterized in that the voltage applied to the control gate from the lane is stuudio threshold level in the multi-level programming, and the voltage supplied to the first flow field-effect transistor for programming from the second voltage source is set to a value less than or equal to zero.

39. The device according to p. 36, wherein the voltage detector comprises a voltage source to induce a voltage on the second drain resistor between the specified voltage source and the second drain of the FET to control.

40. The method of programming the non-volatile memory cell comprising a control gate, floating gate, is divided into first and second region, the field-effect transistor for programming, which includes the aforementioned first region of the floating gate, the first drain, common source, and a first channel region between the first drain and a common source and having a first threshold voltage, and the field-effect transistor for control, which includes the above-mentioned second region of the floating gate, a second drain, common source and a second channel region between the second drain and a common source and having a second threshold voltage, at which carry out the supply of the first and second voltages to the corresponding elements of the cell, characterized in that the supply of OK, allowing charge carriers to programming served in the floating gate electrode through the first channel region for programming, and the second channel region is formed inversion layer, control the conductivity of the inversion layer during programming and stop feeding at least one of the specified first voltage to the control gate and the second voltage to the first drain, when controlled conductivity reaches a reference value.

41. The method according to p. 40, characterized in that the reference value of the selected threshold value of the FET to control.

42. The method according to p. 40, characterized in that the supply of charge carriers in the floating gate electrode from the first channel region to perform programming by either hot injection of carriers, or tunneling, Fowler-Nordheim.

43. The method according to p. 40, wherein the first voltage is a positive value, which changes according to the programming of the corresponding threshold level in the multi-level programming, and the second voltage is a positive value.

44. The method according to p. 40, characterized tatouage threshold level in the multi-level programming, and the second voltage is a value less than or equal to zero.

45. Cell non-volatile memory containing a semiconductor substrate of the first conductivity type, a floating gate and a control gate, characterized in that it contains the first dopant, the second dopant and the third dopant region, formed on the surface of the substrate and located at a specified distance, and each of the said first, second and third dopant regions is a region of the second conductivity type, a first insulating layer of gate formed on the first and second dopant regions in the substrate, the second insulating layer of gate formed on the second and third dopant regions and having a thickness, different from the thickness of the first insulating layer of a gate, a first channel region defined by the area between the first and second dopant regions on the surface of the substrate, the second channel region defined by the area between the second and third dopant regions on the surface of the substrate, a floating gate formed on the first and third dopant regions on the first and veromi managing shutter is formed of an insulating layer.

46. Cell under item 45, wherein the second insulating layer of the gate is thicker than the first insulating layer shutter.

47. Cell under item 45, wherein the first insulating layer shutter thin enough to implement tunneling for erase.

48. Cell on p. 45, characterized in that the surface of the substrate is formed of an insulating protective oxide layer surrounding the first and second insulating layers shutter.

49. Cell under item 45, wherein the portion of the floating gate passes to the surface of the insulating protective layer of oxide.

50. Non-volatile memory device containing a lot of code tires, located at a specified distance, a lot bit of tyres in the second type of conductivity perpendicular to the specified code to the tire and at a given distance with the formation of multiple rectangles, many of the non-volatile memory cells, each of which includes a floating gate, a control gate connected to one of the code of tires, the first drain, common source and channel region located between the first drain and a common source, characterized in that it contains bus common source, dividing correspond to the data bit tyres, and each of the nonvolatile memory cells has a floating gate that is divided into first and second region, the field effect transistor for programming, located on the first side of the rectangles and the input charge carriers in the floating gate for programming, and field-effect transistor to control, located on the second side of the rectangle, specified opposite the first side, and controlling the number of charge carriers accumulated in the floating gate during programming, and field-effect transistor for programming includes the aforementioned first region of the floating gate, a first drain, a common source connected to one of the tires of the common source, and the first channel region between the first drain and a common source field effect transistor for controlling includes the above-mentioned second region of the floating gate, a second drain, referred to a common source and a second channel region between the second drain and a common source, the first drain is connected to one bit of the tire with the second flow cell non-volatile memory located in the rectangle adjacent to the specified first drain and the second drain is connected to the first drain of the memory location is I, that when in the programming mode using the mechanism of hot injection of charge carriers, a voltage of 6 - 13V is applied to the selected code bus, 0V to the unselected code bus, 5 - 9V to the selected n-th bit bus, 0.5 to 2V - selected (n-1)-th bit bus, 0V to the other bit buses, 0V to the selected n-th bus of the source, the conclusions unselected (n-1)-th bus of the source are converted into a floating state, unselected (n-1)I tire of the source corresponds to the selected (n-1)-th bit bus and 0V to the substrate.

52. The device according to p. 50, wherein when in the programming mode using the mechanism of tunneling voltage 10 - 20V is applied to the selected code bus, 0V to the unselected code bus, 0V to the selected n-th bit bus, 5 - 10V - other bit buses, 0V to the selected n-th bus of the source, 5 - 10V - other tyre source and 0V to the substrate.

53. The device according to p. 50, wherein when in the erase mode voltage (-7) - (-12)is applied to the selected code bus and unselected code bus, bit buses converted into a floating state, a voltage is applied to all tires of the source and 0V to the substrate.

54. The device p is the code bus, 0V to the unselected code bus voltage of 0.5 - 2V - selected n-th bit bus, 0V to the other bit tyres, 0V - all tire source and 0V to the substrate.

 

Same patents:

The invention relates to a method of programming a memory device and enables the simultaneous control of threshold levels when performing a two-level or multi-level programming

FIELD: semiconductor memory devices.

SUBSTANCE: device has a lot of memory elements, each of which contains input and output areas, isolating film, channel area, shutter electrode, area for storing electric charges, device also contains large number of periphery circuits, containing reading amplifier, register for storing recorded data of memory elements, register, which preserves the flag, indicating end of record during its check, and circuit, which after recording operation compares value, read from memory cell, to value, fixed by flag at the end of record, and overwrites value indicated by the flag.

EFFECT: higher reliability of operation.

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FIELD: information technology.

SUBSTANCE: flash memory element for electrically programmable read-only memory is meant for data storage when power is off. On a semiconductor base with a source and drain between the latter, there is a tunnelling layer, an auxiliary tunnelling layer, a memory layer, blocking layer and a switch. The auxiliary tunnelling and blocking layers are made from material with high dielectric permeability, from 5 to 2000, exceeding the dielectric permeability of the material of the tunnelling layer made from SiO2.

EFFECT: as a result there is reduction of voltage (4 V) and time (10-7 s) for recording/erasing information and increase in data storage time (up to 12 years).

7 cl, 1 dwg

FIELD: information technology.

SUBSTANCE: memory cell for high-speed controlled gate-region potential EEPROM, the electric circuit of the memory cell having an n(p)-MOS transistor, first and second diodes, a capacitor, a number, an address and a bit line, wherein the cathode (anode) of the first diode is connected to the number line and the source of the n(p)-MOS transistor, its anode is connected to the anode of the second diode, the region under the gate of the n(p)-MOS transistor and the first lead of the capacitor, the second lead of which is connected to the gate of the n(p)-MOS transistor and the address line, and the cathode of the second diode is connected to the drain region of the n(p)-MOS transistor and the bit line, wherein the electric circuit of the memory cell additionally includes a p(n)-field-effect transistor, a common and control line, wherein its source is connected to the region under the gate of a MOS transistor, the gate is connected to the control line and the drain is connected to the common line.

EFFECT: higher reliability of memory cell work.

2 cl, 6 dwg

FIELD: electronics.

SUBSTANCE: invention relates to microelectronics. Restoring memory element has a substrate with a conducting electrode located on its working surface. Said conducting electrode has an active layer of dielectric. Second conducting electrode is located on the active layer. Conducting electrode located on the working surface and/or the second conducting electrode are made from metal. Dielectric layer is metal oxide from which conducting electrode located on the working surface and/or the second conducting electrode is made.

EFFECT: technical result is lower voltage of reprogramming, as well as reduction of consumed power for reprogramming.

14 cl, 1 dwg

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