The method of programming the nonvolatile memory cell

 

(57) Abstract:

The invention relates to a method of programming a memory device and enables the simultaneous control of threshold levels when performing a two-level or multi-level programming. The method is intended for programming the non-volatile memory cell, which has a control gate, a floating gate, drain, source and channel region. The method includes applying a first voltage to the control gate, the second voltage to the drain of the third - to the source. The second voltage exceeds the third. The method provides control of the current between drain and source. When the current of a given value of the complete programming of the first two levels. 3 C. and 15 C.p. f-crystals, 5 Il.

The invention relates to a method of programming a memory device, in particular to a method of programming a non-volatile semiconductor memory.

The cost of the non-volatile semiconductor memory devices such as electrically erasable programmable permanent memory (EEPROM) and flash EEPROM, is used as a medium extra-large capacity, sledovanie memory capacity of several bits.

The areal density of the non-volatile memory corresponds to the number of memory cells in a ratio of one to one. The memory cell in a few bits stores at least two bits of data in one memory cell, thereby greatly increasing the density of information in the same region of the crystal, without reducing the size of the memory cell.

To implement the memory capacity of several bits for each memory cell should be programmed more than three levels of threshold voltage. For example, to store two bits of data in one cell, the corresponding cells are programmable in four stages threshold level, i.e., 22= 4. As a result, four of the threshold level logically belong to the respective logical States 00, 01, 10 and 11.

In the above-mentioned multi-level programming is particularly important that the appropriate level of the threshold voltage had a statistical distribution about 0.5 Century.

Therefore, decreasing distribution by precisely controlling the respective threshold levels can be programmed more levels, thereby creating the possibility of increasing the number of bits in odno accepted way repeated programming and control. According to this method, a sequence of voltage pulses applied to the cell for programming the non-volatile memory cell to a desired threshold level. Reading occurring between the respective voltage pulses, controls, did the correct threshold level. During this control, when the value of the checked threshold level reaches the desired threshold level, the programming process stops.

In the system of repetitive programming and control is difficult to reduce the distribution of errors threshold levels due to pulse voltage programming. In addition, the implementation of the algorithm repetitive programming and control requires the use of additional circuits, resulting in a region of the peripheral circuit of the crystal increases. Moreover, this method leads to an increase in programming time.

To eliminate the above disadvantages P. Carnea of the company "SanDisk" proposed method for simultaneous programming and control (U.S. patent N 5422842). In Fig. 1A depicts a conventional electric circuit EEPROM proposed by P. Carnea. The EEPROM cell samostatnou for the implementation of the programming voltage applied on the control gate 1 and the drain 5, the current flows between 5 and source 3. This current is compared with a preset reference current to generate the signal of the programming is complete, when this current is equal to the reference current or less.

In this method, the state of the programming automatically controlled simultaneously with the programming to eliminate the disadvantages of the method repetitive programming and control. However, the level of the threshold voltage applied to the control gate 1 of the memory cell cannot be adjusted.

U.S. patent N 5043940 name Harari performs multilevel programming by measuring the reference currents corresponding to respective levels. As shown in Fig. 1B, the reference currents to control not relate explicitly or linearly with the threshold voltage of the cell. Therefore, multilevel programming cannot directly and effectively monitored with the method of the current control.

Accordingly, this invention is directed to a method of programming a non-volatile memory, which would greatly help to solve one or more problems due to limitations and disadvantages of the existing level of technological development in the Dan is ATI, which will provide simultaneous control of threshold levels when performing a two-level or multi-level programming.

Another objective of the invention is to provide a method for programming non-volatile memory to control the respective threshold voltage levels supplied to the control gate when performing a two-level or multi-level programming, in which the respective threshold levels and the voltage applied to the control gate corresponding to respective threshold levels have a linear relationship.

Additional characteristics and advantages of this invention will be set forth in the following description and will partly be obvious from the description, or may be identified in the practical use of the invention. The objectives and other advantages of this invention will be realized and attained by the structure specified in the description and the claims, and also to illustrate the invention the drawings.

To achieve the above advantages and in accordance with the image - in the form in which it is implemented and described in detail, a method of programming the national region, located between the drain and source, and the method includes the following operations: application of the first voltage to the control gate for the formation of the inversion layer in the channel region, and the first voltage is changed to implement programming at least two threshold levels of memory cells, the application of the second voltage to the drain of the third - to the source, and the second voltage exceeds the third voltage, the control current flowing between the drain and source, when programming in at least two threshold levels, and the supply of one of the voltages of the first, second, third - when a controlled current of a given reference current, thereby completing the programming of the at least two threshold levels.

Cell non-volatile memory, such as EEPROM cell in accordance with this invention includes a control gate, a floating gate, a drain, a source and a channel region located between the drain and source.

Proposed programming method according to this invention is accomplished by application of the first voltage, measured in accordance with the relevant threshold levels when programmery the formation of the inversion layer in the channel region. After that, the second voltage and the third voltage are applied respectively to the drain and the source in such a way that shipped with the drain voltage is higher than that which is attached to the source. Then the current flowing between drain and source is controlled by programming the corresponding threshold levels of the EEPROM cell, and feed one of the voltages (first, second, third), respectively, supplied to the control gate, the drain and the source, stops to stop programming when the monitored current reaches a predetermined reference current.

It should be noted that as the above General description and the following detailed description are examples and explanatory and are intended to provide further explanation of the invention in the form in which it is set forth in the claims.

The accompanying drawings are intended for further explanation of the invention, are an integral part of the description, illustrate embodiments of the invention, and together with the description serve to explain the principles of the present invention. In Fig. 1A shows a schematic diagram of conventional non-volatile memory cell of Fig.1B is a graph from the - the Hema explaining a programming method using the detection current in accordance with the implementation of the invention; Fig. 3A - 3G are timing chart of signals for the respective nodes in Fig. 2; Fig. 4 is a block diagram of the process of two-level or multi-level programming in accordance with the preferred implementation of the invention; Fig. 5A is an equivalent schematic diagram of the memory shown in Fig. 1A, illustrating the electrical capacity of Fig. 5B is a graph of the relationship between the threshold levels to be programming, and the respective voltages of the control gate; Fig. 5C is a graph of current flow from start to finish programming appropriate levels.

In Fig. 2 presents a diagram illustrating the structure of the nonvolatile storage device, intended for implementing the method of programming according to this invention. Nonvolatile memory shown in Fig. 2, contains the first voltage source 6, a second voltage source 7, the third voltage source 8, the detector current is 9 and the EEPROM cell 10. Psindicates the signal start programming from external devices,ur EEPROM cell 10. In other words, a typical cell of the nonvolatile memory of various types, such as simple multilevel gate, and the structure of the split-channel, can be simplified to review the operational mode programming to obtain the structure shown in Fig. 1A.

The first voltage source 6 applies a voltage VC,i(where i= 0, 1, 2, . . . and n - 1) on the control gate 1 of the EEPROM cell 10 for programming the i-th threshold level in a multilevel programming. Accordingly, the voltage VC,ihas different values for each level. The source of the second voltage 7 applies a voltage VDto drain 5 and source of the third voltage 8 applies a voltage VSon the source 3. Here, the voltage VSmay have any value, but for convenience of explanation it is suggested that Vs- the voltage of the earth, ID,i(t) denotes the current flowing to the table 5. The detector current 9 has a reference value of current IREFand generates the stop signal programming VSTwhen the current ID,i(t) flowing through the drain 5, reaches the value of reference current IREFwhen programming the i-th threshold level.

Time tP,imeans mo is determined electrical characteristic of the cell of the EEPROM 10, which uses a programming method according to the invention.

When re-determining the current ID,i(t) flow 5 current ID,i(t) the flow is time-dependent. This value of ID,i(t) denotes the current value of the current flow of 5, due to the voltage VF,i(t) on the floating gate 2 when programming the i-th level. Current ID,i(t) is maximum at the beginning of the programming period and decreases in the programming process. The signal VSTstop programming is generated by the detector current 9, when the current decreases below the reference current IREFdetector current 9.

Under the above conditions, the process is two-level or multi-level programming will be described with reference to Fig. 3 and 4. In Fig. 3A - 3G shows the timing chart of signals at respective points of the circuit of Fig. 2, and Fig. 4 is a block diagram depicting the process of two-level or multi-level programming in accordance with this image. Next, the method of programming the EEPROM cell 10 of Fig. 2 in accordance with this invention will be described in detail with reference to the block diagram of the algorithm is shown in Fig. 4.

For programmer is applied according to the programming of each threshold level during programming of at least two threshold levels, attached to the control gate 1 and the second voltage and the third voltage are attached respectively to the drain 5 and source 3, while attached to the drain 5 voltage exceeds that which is attached to the source 3. Then the current flowing between the drain 5 and source 3 is controlled by programming the corresponding threshold levels of EEPROM cell 10, and feed one of the voltages (respectively first, second, third) attached to the control gate 1, the drain 5 and source 3, is stopped to stop programming when the current reaches a preset reference current.

This method will be described in detail below. It is assumed that the corresponding cell before performing the programming is in the erased state. Here erased state corresponds to a zero level, which is the lowest level. It is also assumed that the FET floating gate has a structure with n-type channel on the substrate is p-type.

First, as shown in Fig. 3A, when the external signal Psbeginning programming served for two-level or multi-level programming, the voltage VC,iattached to the control gate 1, set degenia VC,idepicted in figs. 3B, and VDserved from the first voltage source 6 and the second source voltage 7 to the control gate 1 and the source 5, respectively.

Under these conditions in the floating gate electrode 2 serves electrons for programming the i-th threshold level. In this case, for the filing of the charge in the floating gate 2, you can use any programming mechanism, but it is typically a hot injection of charge carriers or the tunneling mechanism.

After application of the voltage VC,iand VDrespectively to the control gate 1 and the drain 5 is activated detector 9 for controlling the voltage at the floating gate 2. After application of the voltage VC,iand VDto the control gate 1 and the drain 5, as shown in Fig. 3C, the voltage VF,i(t) for programming the i-th threshold level is supplied to the floating gate 2 and the channel region 4 field-effect transistor is formed inversion layer. In fact, since the source 3, the drain 5 and the channel region 4 are placed on a semiconductor substrate (not shown), the current after the formation of the inversion layer is from drain 5 to the source 3 through the channel region 4. At this time, the current ID,i(t) flowing the ode programming to lower the voltage of the floating gate, and therefore the current ID,i(t) also decreases.

As described above, the detector current is 9 controls the current ID,i(t) drain during programming of the i-th threshold level.

When the monitored value reaches the reference current IREFas shown in Fig. 3D, the programming of the i-th threshold level is completed and the output signal VSTstop programming, as shown in Fig. 3E. The detector current is 9 controls the current ID,i(t), as shown in Fig. 3C and 3G, can be described by a control voltage or the amount of charge in the floating gate 2 during programming.

As shown in Fig. 3C, the voltage of the floating gate reaches the reference voltage VFREFin the floating gate 2, the corresponding reference current IREFwhen the drain current reaches the reference current IREF. In addition, the control current ID,i(t) can be described by controlling the electric conductivity of the inversion layer formed in the channel region 4 of Fig. 2.

As shown in Fig. 2, the signal VSTstop programming is supplied to the sources 6 and 7, first the current 5 in response to the signal VSTstop programming, as shown in Fig. 3B. In other words, if the current ID,i(t) is less than the reference current IREFat t = tP,ithe programming of the i-th level of the threshold is terminated. Therefore, the time tP,iindicates the time of programming of the i-th threshold level.

In Fig. 3F shows the variation in the threshold voltages VCTH,1and VCTH,2on the control gate 1 relative to the time for programming the first and second threshold levels.

In Fig. 3F shows the increase of the threshold voltage VCTH,1on the control gate 1 with increasing level during multi-level programming. This is obtained by increasing the voltage VC,iwhen programming. Here the moments programming tP,iand tP,2the first and second levels are different due to the different values of the voltage of the control gate and the threshold voltage related to the appropriate levels.

In Fig. 3G shows a graph of the change of charge in the floating gate 2 from the initial amount of charge QF,0(O) in the floating gate 2 to a value of QF,1(tP,1when the programming of the first threshold ureshino, in the case of the first and second threshold levels. As shown in Fig. 3G, the amount of charge in the floating gate 2 is increased from the initial value of QF,0(0) to the corresponding values of the charge QF,1(tP,1) and QF,2(tP,2), when the voltage VF,1(t) and VF,2(t) (where t = tP,1and t = tP,2) on the floating gate electrode 2 reaches the reference voltage VFRERcorresponding to the reference current IREF.

With reference to Fig. 5A will be described the relationship between the voltage VC,1applied to the control gate 1, and the threshold voltage of the corresponding level; this relationship appears to be a significant result in the claimed invention.

In Fig. 5A shows the equivalent schematic diagram depicting the electrical capacity of the EEPROM cell of Fig. 1A. In Fig. 5A, Ccdenotes the capacitance between the control gate 1 and the floating gate 2: CD- the capacitance between the drain 5 and the floating gate 2, and CSthe capacitance between the source (including the substrate) and a floating gate 2.

The amount of CTtanks can be written as follows:

CT= CC+ CD+ CS(1)

Coeff>D/CT, aS= CS/CT(2)

According Fig. 5A, the voltage on the floating gate 2 when programming in General form is written as follows:

< / BR>
where the symbol QF(t) denotes the amount of charge in the floating gate 2 at time t.

When programming the threshold voltage VCTH(t) on the control gate 1 is defined as follows:

VCTH(t) = -QF(t)/CC(4)

In other words, VCTH(t) in equation (4) corresponds to the shift of the threshold voltage measured at the control gate 1 at time t. The shift of the threshold voltage VCTH(t) denotes the threshold voltage measured on the control gate 1 after it was due to the charge accumulated in the floating gate 12.

The threshold voltage VFTHin the floating gate 3 is the threshold voltage inherent to the field effect transistor consisting of the floating gate 2, drain 5 and source 3 (Fig. 1).

VFREFis determined by the conditions of manufacturing the field-effect transistor, such as ion implantation of the channel and the thickness of the insulating layer of the gate in the manufacture of ball always constant.

The threshold voltage VCTHthe control gate 1 is determined by the magnitude of the charge QFin the floating gate 2. Programming the respective threshold levels is stopped when the voltage VF(t) on the floating gate 2 reaches the reference voltage VFREFon the floating gate 2. That is, this point corresponds to the time when the current ID(t) flow 5 reaches the value of reference current IREFand also corresponds to the time tPwhen programming is complete.

Thus, the voltage VF(tP) floating gate 2, when the programming threshold level completed, is written as follows:

VF(tp) = VFREF= aC[VC-VCTH(tp)]+aDVD+aSVS(5)

After transformation of equation (5) voltage VWITHsupplied from a first voltage source 6 to the control gate 1, is defined by the following formula:

VC= VCTH(tp)+[VFREF-aDVD-aSVS]/aC= VCTH(tp)+V1 (6)

where

V1 = [VREF- aDVD- aS and the reference voltage VFREFso that the values of V1 is fixed at the interval you have finished programming the appropriate level, the voltage VWITHthe control gate and the shift of the threshold voltage VCTHare linear with respect to each other. According to the most simple method of fixing V1 corresponding voltage VDthe drain voltage VSsource and reference voltage VFREFfixed relative to the programming of the respective levels.

However, as can be seen from equation (5), the tension drain VDand the voltage source VSmust have the same value at the final programming of the respective levels. In other words, although the voltage VDflow and voltage VSthe source can be variables that differ from each other in accordance with the time of programming, this goal can be achieved only when it is ensured that these values will be equal in the final programming.

In equation (7), if the coupling coefficients aDand aSsignificantly less coupling coefficient aCthen two members with coefficientsin the shutter appropriate levels may change over time. In this case, the voltage VCappropriate levels is a finite value after programming the appropriate levels.

The value V1 is set constant for each level of programming, as described above, therefore, the voltage VC,ia control gate that is required for programming the i-th threshold level, is expressed by equation (8) by equation (7):

VC,i= VTH,i+ V1 (where i= 0, 1, 2, 3,...n - 1) (8)

From equation (8) implies that the programmable threshold levels and the voltage of the control gate corresponding to them, have a linear dependence with a slope equal to one. Fig. 5B illustrates the result. From equation (4) also implies that the magnitude of the charge on the floating gate 2 are linear with respect to voltage of the control gate.

Because the value of V1, as indicated above, the constant, the value of Vc,ii-th shift of the voltage applied to the control gate during the multi-level programming, is expressed in the following form:

Vc,i= VCTH,i(9)

According to equations (8) and (9), when the shift value VCTH,iout of the erased state, i.e., from the lower eurorevenue, the programming of the appropriate level is performed so that the value obtained by adding the values of VCTH,ithe required shift of the threshold and the value of VC,Opreviously known low level programming, is applied to the control gate. Then wait for the automatic programming is complete.

Since the reference voltage VFREFconstant, and the voltage of the control gate VC,iincreases when it reaches a higher level relative to the programming of the respective levels, the initial value of IDi(0) current flow increases when it reaches a higher level. This process is illustrated in Fig. 5C. When programming is complete, appropriate levels changed in accordance with the electric characteristics of the memory cells and the voltages applied to the respective points of the circuit.

Below will be described a method of determining the value of the voltage VC,Oand the reference current IREFto perform programming of the lowest level.

First, if it is determined desired value of the lowest level VCTH,OC,0and the reference current IREFin the floating gate 2. Since the voltage of the drain of VDand the voltage source VSto be constant, the reference voltage VFREFcorresponds to the magnitude of the reference current IREFin the ratio of one to one.

The memory cell is adjusted to the desired value of the lowest level VCTH,O/and the voltage VC,0VDand VSserved in a memory cell. Then the initial value of the current flow ID,0(0) is measured and becomes the reference current value. Here, the voltage VC,0is based programming time and the maximum voltage VC,n-1the control gate. After determining the voltage VC,0the magnitude of the reference current can be obtained by the above method. The magnitude of the reference current can also be measured in other ways.

In the above description, the value V1 of equation (7) is fixed relative to the programming of the respective levels. If the parameters of equation (7) adjust for changing the value V1 for programming the appropriate levels, the voltage VC,ithe control gate and the corresponding threshold n is in the offset voltage of the control gate and the shift value corresponding to the threshold voltage are different. In this case, the reference IREFproperly regulated at the desired value for each level to allow the programming threshold voltage corresponding to each level. Just because the voltage VC,ithe control gate and the corresponding threshold voltage VCTH,ihave a linear relationship, their relationship can be determined experimentally.

Present the principles of the present invention are explained regardless of the mechanism of programming. Thus, it is possible to conclude that the principles of the present invention is applicable to the mechanism of programming any system described by equation (3).

If the system is hot injection of charge carriers, the voltage source is grounded, and the voltage of the drain and the control gate supplied with a positive potential that is high enough to provide programming hot injection of charge carriers. When this current flows between the drain 5 and source 3, and the current programming is controlled to complete the programming when the current reaches the reference current.

When using the system modelirovaniya pologaetsa to the drain 5 and source 3. As a result of this applied electric field sufficient for the occurrence of the effect modelirovaniya between the floating gate 2 and the drain 5, the source 3 or channel 4. In this case, the voltage of the drain exceeds the voltage source, thereby creating a current of the possibility of leakage between drain 5 and source 3. The current is controlled to complete the programming, when the current reaches the reference current IREF. If the drain 5 or the source 3 is supplied with a negative voltage when the drain 5 and source 3 are areas of semiconductor dopant of n-type and the substrate is a semiconductor p-type substrate is served less than or equal to the voltage.

Still described a two-level or multilevel programming method. Next is explained a method of erasing using the above system programming.

When erasing corresponding points of the cell are served voltage for the application of the electric field strong enough to erase the charge carriers between the floating gate 2 and source 3, drain 5 or channel region 4, and thus by tunneling to erase the charge carriers to the source 3, the drain 5 or channel region 4. In line . In other words, all cells of the EEPROM in this block erase programmed at the lowest level. The erase process is easily performed by the following steps.

First, the threshold levels of all cells in the selected block are erased to the level below zero, i.e., lower VCTH,O. Then all of the selected cell is programmed by the value of the zero level, i.e. the voltage of the control gate 1 is equal to VC,0< / BR>
Here the value of VC,0can be set to the desired value, as described above. Since erasing is achieved by the above mechanism, programming, can be solved the problem of over-Erasure.

The above programming method in accordance with this invention has the following advantages.

First, multilevel programming is easily accomplished, since for each programming the respective threshold levels change only the voltage of the control gate.

Secondly, the respective levels of the threshold voltage and the corresponding voltage of the control gate, related to them, have a linear relationship with each other, and the amount of shift of the threshold voltage is the same as in rogovogo voltage to appropriate levels.

Third, since the erased state is regulated by additional voltage of the control gate programming low-level problems of excessive erasing in fact does not occur.

Fourth, the EEPROM cell is characterized by the simultaneous implementation of programming and reading, and therefore, a separate circuit for controlling the programmed contents are not needed, and consequently, the programming speed is increased.

Fifthly, the pre-programming before performing the erase is not required.

Sixth, the accuracy of multilevel programming, i.e., the distribution of errors of programming threshold voltage, is accurately determined by the parameters set when manufacturing the non-volatile memory, and the application of a bias voltage. Therefore, the distribution of errors of the threshold voltage of the respective levels of non-volatile memory in accordance with this invention does not depend on repeated cycles of programming/erasing. In addition, programming is performed regardless of the charge capture, mobility of charge carriers in the channel, the resistance of the bit bus and instability, or is mate in accordance with this invention is carried out by way using voltage control, through the application of voltage to the control gate, the multi-level programming can be performed easier and more accurate than in the case of the method using the current control.

Specialists in this field will be obvious that the method of programming the nonvolatile memory in accordance with this invention can be carried out in various modifications and changes within the scope and without changing the essence of the present invention. The invention includes modifications and variations provided that they are within the claims and its equivalents.

1. The method of programming the non-volatile memory cell having a control gate, drain, source and channel region located between the drain and source, which supply the first voltage to the control gate and control the magnitude of the flowing current, wherein the first voltage applied to the control gate for the formation of the inversion layer in the channel area changing for programming at least two threshold levels of memory cells, perform supply of the second voltage to the drain of the forward flowing current control current, flowing between the drain and source during programming of at least two threshold levels, and stop the flow of one of the voltages of the first, or second, or third, when the monitored current reaches a predetermined reference current to complete the programming of at least two threshold levels.

2. The method according to p. 1, characterized in that the reference current has a fixed value during programming of at least two threshold levels.

3. The method of programming the non-volatile memory cell having a gate, a floating gate, a drain and a source, for which the supply of the first voltage to the control gate and control the magnitude of the flowing current, wherein when applying the first voltage to the control gate shall change supplied first voltage, perform supply of the second voltage to the drain and the third voltage to the source, for controlling the magnitude of the flowing current control the current between drain and source when applying the first voltage to the control gate and stop filing any of the voltages of the first voltage to the control gate, the second voltage to the drain of the third notable when controlling the magnitude of the flowing current control voltage on the floating gate.

5. The method according to p. 3, characterized in that for controlling the magnitude of the flowing current to control the magnitude of the charge in the floating gate.

6. The method according to p. 3, characterized in that when applying the first voltage to the control gate form an inversion layer in the channel region located between the drain and source.

7. The way the method according to p. 6, characterized in that for controlling the magnitude of the flowing current control conductivity of the inversion layer.

8. The method according to p. 3, characterized in that the first voltage changing linearly relative to at least two threshold levels of the memory cell.

9. The method according to p. 3, characterized in that the second voltage exceeds the third voltage.

10. The method according to p. 3, characterized in that the reference current is a fixed reference current.

11. A method of programming at least two threshold levels of the memory with a control gate, a floating gate, drain and source, which submit produce first voltage to the control gate perform supply of the first voltage, related to the corresponding one of the at least two threshold levels, perform supply of the second voltage to the drain and the third voltage to the source, for controlling the magnitude of the flowing current to control the magnitude of the current flowing between drain and source when applying the first voltage to the control gate, and stop the supply of any voltage, the first voltage on the control gate, the second voltage to the drain and the third voltage to the source when the monitored current reaches the reference current.

12. The method according to p. 11, characterized in that for controlling the magnitude of the flowing current control voltage in the floating gate.

13. The method according to p. 11, characterized in that for controlling the magnitude of the flowing current to control the magnitude of the charge in the floating gate.

14. The method according to p. 11, wherein when applying the first voltage to the control gate form an inversion layer in the channel region located between the drain and source.

15. The method according to p. 14, characterized in that for controlling the magnitude of the flowing current control conductivity Inversiones dependence on at least two threshold levels.

17. The method according to p. 11, wherein the second voltage exceeds the third voltage.

18. The method according to p. 11, wherein the reference current is a fixed reference current.

 

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