Device for switching messages

 

(57) Abstract:

The invention relates to computing and can be used to provide machine-to-machine exchange in distributed computer systems and computer networks. The technical result is improved performance of the device by processing the input stream of messages by channel group processing. Device for switching messages comprises a generator 1 clock pulses, a first counter is 2, the second counter 3, a decoder 4, block 5 of the agreement, the group receiving blocks 6.1--0.4, a group of transmission units 7.1-7.4, the group of blocks routing 8.1-8.3, the matrix load 9, the response matrix 10, the address matrix 11, the filtering unit 12, an information matrix 13, the matrix control 14, a matrix of pair 15, a group of information inputs 17.1-17.4, group signal outputs 18.1-18.2, group signal inputs 19.1-19.4, the group of information outputs 20.1-20.4, a group of query inputs 21.1-21.4, a group of query outputs 22.1-22.2, internal communication 16,23-44. 13 Il.

The invention relates to computing and can be used to provide machine-to-machine exchange distribution in computer systems and computer networks.

It is known device [1] what about the drive, unit firmware control, arithmetical-logical unit, block messages, two of the switching unit and the block-grant message, and the output of the firmware control connected to control inputs arithmetical-logical unit, the Central unit of the drive unit of the input buffer, the output of which is connected to the first information input arithmetical-logical unit and input block decode headers, the output of which is connected to the input of the header block of the firmware control.

However, this device has low productivity, which is due to the fact that at any time it processes (commutes) not more than one message.

The closest in technical essence and the achieved positive effect is the device [2] for switching messages containing blocks mate with channels having tires of acceptance and control, which are the inputs-outputs of the device, the unit firmware control, the first output of which is connected with United first inputs of interface unit, the memory block, information, and address bus, the priority block, the block select route and unit maintenance turn the STV, and the third input-output with the first input-output memory block, the other input of which is connected to the fourth output unit queueing, the fifth output and the fourth input of which is connected to the second input and output unit firmware management, third and fourth outputs of which are connected respectively to the address bus and the first input of the priority block, the output of which is connected to the first input unit firmware control, and the second input is connected to the first combined output blocks mate with channels, second and third inputs and outputs which are connected respectively to the address and data bus device, connected also to the second input and to the input-output block of route selection, the first output of which is connected with United first input of the block mate with the channels, and the third input is connected to the fifth output of the firmware control.

However, this device adopted for the prototype also has low performance, because it does not allow simultaneous switching of more than one message. This is because the device has only one block of route choice, and therefore cannot achieve proizvoditel, that known device cannot find enough wide application.

The purpose of the invention is to improve the performance of the device by processing the input stream of messages by channel group processing.

The goal is achieved in that the device for switching messages containing each of K (K is the number of full-duplex communication channels) output block register receive, and the K-th information input device connected to the information input of the output register of the K-th output block, and the block select route persistent storage device, the register group item And the group of outputs of the DC storage device is connected respectively with a group of information inputs of the register, the group of information outputs of which are connected respectively with a group of information inputs of the group element, And the group of outputs of which are connected respectively with the group of outputs of the block routing, introduced additional clock pulses, first and second counters, decoder, block matching, a group of K transmission blocks, the group of M-1 blocks routing (M - total number of blocks routing), matrix loading, the response matrix, the address Matri of clock pulses is connected with the first inputs receiving, the transducer blocks and with a counter input of the first counter, the output of which is connected to the counting input of the second counter, a group of information outputs of which are connected respectively with a group of inputs of the decoder, A first output of which is connected to the first input of the A-th block of route selection, the second input is connected to the A-m output the first group of outputs of the filtration unit, A group of inputs of the first group of inputs of which are connected respectively with the group of outputs of the A-th block of route selection, the group of inputs which are connected respectively with the A-th group of outputs of the address matrix, B-I group of inputs of the first group of inputs which are connected respectively with the group of outputs of the B-th output unit, A first output of the first group of outputs of the filtration unit is connected with A-m entrance of the first group of inputs of the response matrix and matrix download, group of outputs which are connected respectively with the second group of inputs of the response matrix, the address of the matrix, the filtration unit and block matching, the group of outputs of which are connected respectively with the second group of inputs of the matrix load, the output of which is connected to the input of block matching, B-th output of the second group of outputs of which are connected respectively with the fourth of whadaya group of inputs which are connected respectively with a group of outputs response matrix, B-th information signal and the input device are connected respectively with the second and third inputs of the B-th output unit, the first output of which is connected to B-m signal output device, B-y information and request the outputs of which are connected respectively with the first and second outputs of the B-th transmitting unit, a second input connected to B-m request from the input device, the third output of the B-th transmitting unit is connected to the B-th input of the first group of inputs of the matrix pair, the B-th output of which is connected to the fifth input of the B-th output unit, the third output of which is connected with the B-th input of the first group of inputs of the information matrix, B-th output of which is connected to the third input of the B-th transmitting unit, the fourth output of which is connected to the B-input of the third group of inputs of matrix management, B-th output of the third group of outputs which is connected to the fourth input of the B-th transmitting unit, the second group of inputs of the information matrix and the matrix pair are connected respectively with the second group of outputs of the matrix control, the first group of outputs which are connected respectively with the third group of inputs of the filtration unit, the second and third group of outputs which are connected respectively with the first and second groove OR two of K triggers and a group of K forming elements, and the B-th input of the first group of inputs connected to the first input of the B-th element And whose output is connected to a single inlet B-th flip-flop of the first group, zero dynamic input connected to the output of the B-th element, OR inputs which are connected respectively to the M inputs of the B-th group of the second group of inputs of block matching, an input connected to the second input of the B-th element, And a third input connected to the inverse output B-th flip-flop of the second group, direct the output of which is connected to the input of the B-th output element, the output of which is connected with the B-th output of the first and second groups of outputs of block matching, B-d input of the third group of inputs which are connected respectively to the M inputs of the B-th group of the second group of inputs of block matching, an input connected to the second input of the B-th element, And a third input connected to the inverse output B-th flip-flop of the second group, the direct output of which is connected to the input B of the second forming element, the output of which is connected with the B-th output of the first and second groups of outputs of block matching, B-d input of the third group of inputs is connected to the zero input of the B-th flip-flop of the second group, a single dynamic the inputs of all elements except B-x, moreover, in each of the K foster blocks put two counters, the six elements And two elements OR five triggers and the item is NOT, the first input receiving unit connected to the first input of the second element And the second inputs of the fourth and fifth elements And with a counter input of the first counter, the output of which is connected to the first input of the first element And whose output is connected with the second output of the receiving unit, a second input connected to the information input of the output register group which outputs corresponding to the direct outputs of the triggers that contains the address of the destination computer, connected respectively with the group of outputs of the receiving unit, a third input connected to the first input of the sixth element, And whose output is connected to the first output of the receiving unit, a fourth input connected to the zero input of the second trigger, and the outlet of which is connected to the second input of the first element And the fifth input receiving unit is connected with a single dynamic input of the first trigger and zero dynamic input of the third trigger, the direct output of which is connected with the control input of the output register, the information output of which is connected with the third output of the receiving unit, direct, OR, the output of which is connected to the first input of the fifth element And whose output is connected to a clock input of the output register, the information of the trigger output of the last discharge of which is connected to a single dynamic input of the fifth trigger, direct the output of which is connected to the first input of the fourth element And the output of which is connected to a summing input of the second counter, the subtractive input connected to the output of the second element And information group of outputs of the second counter connected respectively with a group of inputs of the first element OR the output of which is connected to the zero dynamic inputs of the first and the fourth flip-flop inverted output of which is connected to the first input of the second element OR the direct outputs of the triggers of bits of the second counter receiving unit corresponding to the number of bits in the packet of information, are connected respectively to the inputs of the third element And whose output with a single dynamic inputs of the second, third and fourth trigger and zero dynamic input of the fifth trigger, the output of the first element OR the receiving unit is connected with the input element, the output of which is connected to a second input of the sixth element, And each of K transmitting unit is and is connected to the counting input of the second counter and to the second input of the first element And the output of which is connected to the counting input of the first counter, the output of which is connected to the negative input of the first trigger and the fourth output of the emitting unit, a second input connected to the zero input of the second trigger, the inverted output of which is connected to the first input of the third element And whose output is connected to the third output of the emitting unit, the third input connected to the direct input of the first flip-flop and the first output of the emitting unit, a fourth input connected to the input of the delay element and a single dynamic input of the second trigger, the direct output of which is connected with the second input of the second element, And the output of which is connected with the second output of the transmitting unit, the output of the second counter of the transmitting unit connected to the first input of the second element And the output of delay element emitting unit is connected to a second input of the third element And direct the output of the first trigger transmitting unit connected to the first input of the first element And the group of inputs of the block select route connected respectively with a group of inputs of persistent storage devices block routing, the first and second inputs which are connected respectively with the control of womento OR/NOT, the group of M delay elements, the group of M delay elements, the matrix KM triggers, matrix KM elements And the element OR group of K-1 elements AND IS NOT, and A first input of the first group of inputs of the matrix load is connected to the input of the A-th delay elements, the output of which is connected to the zero input triggers A-th row of the matrix download, B-th entry of the second group of inputs of which is connected with the first inputs of elements And B-th column of the matrix download, inverted output A, B-th flip-flop matrix load is connected to a second input A, B-th element And whose output is connected to a single input A, B-th flip-flop, and the outlet of which is connected to A, B-m matrix output load B-m-log A-th element OR NOT, the output of which is connected with A-m input element OR the output of which is connected to the matrix output load, the output of the first element OR NOT the matrix load connected to the third inputs of elements And the first row, the first and second input element AND to the second input of the second element AND-NOT outputs of the third and second elements OR NOT the matrix load connected respectively with the third inputs of the third and second rows of cells and matrix load, the output of the second element OR NOT the matrix load is connected to the first input of the second ale is subjected to loading, moreover, the response matrix contains a matrix MK elements And the group of K elements OR, with A, B-th entry of the second group of inputs of the response matrix is connected to a second input A, B-th entry of the second group of inputs of the response matrix is connected to a second input A, B-th element And the output of which is connected to the A-m to the B-input element OR the output of which is connected with the B-th output response matrix, A-d input of the first group which is connected with the first inputs of elements And the A-th column of the response matrix, moreover, the address matrix contains a matrix MK group elements And group M group elements OR, with A, B-th entry of the second group of address inputs of the matrix is connected with the control input A, B-th group member And the group of outputs of which are connected respectively to the B-th group of inputs of the A-th group element OR group of outputs which are connected respectively with the A-th group of outputs of the address matrix, B is a group of inputs of the first group of inputs which are connected respectively with a group of information inputs of the B-th column group elements And address of the matrix, and a group element, OR contains S (S is the number of links in each of the R dial-up groups) of elements OR, and S-d input group item OR R-th group is connected with R-m whodunit group M group elements And, the first group of M elements OR a matrix of MK elements And the second and third group of K elements OR, with the B-th entry of A-th group of the second group of inputs of the filtering unit connected to the B-th entry of the A-th group element And the B-th output of which is connected to the A-m to the B-input of the first element OR the second group, the output of which is connected with the B-th output of the second group of outputs of the filtering unit, B-d input of the third group of inputs is connected to the second inputs of the B-th row of the matrix elements And the filtration unit, output A, B-th element And the filtration unit connected to the A-m to the B-input element OR the third group, the output of which is connected with the B-th output of the third group of outputs of the filtration unit, A, B-d input of the first group of inputs is connected to the first input A, B-th element, And the output of which is connected with the B-th entry of the A-th element OR the output of which is connected with the control input of the A-th group element And with A-m output the first group of output filtering unit, and the information matrix contains a matrix KK elements And the group of K elements OR, with B, B-th entry of the second group of inputs of the information matrix is connected to a second input B, B-th element And whose output is connected to B-m B-input element OR the output of which is connected with the B-th output informatioi matrix, moreover, the matrix pair contains a matrix KK elements And the group of K elements OR, with B, B-th entry of the second group of inputs of the matrix pair is connected to a second input B, B-th element And whose output is connected to B-m B-input element OR the output of which is connected with the B-th matrix output pair, B-th input of the first group which is connected with the first inputs of elements And B-th column of the matrix pair, and matrix management contains a matrix KK triggers, matrix KK elements And, the group of K elements OR group of K elements is NOT, and B-1 input of the first group of inputs of the matrix control is connected with the first inputs of elements And B-th column of matrix management, B-th entry of the second group which is connected with the second inputs of elements And B-th row of the matrix control, exit B, B-th element of matrix management is connected with a single entrance B, B-th flip-flop inverted output of which is connected to the third input B, B -, And a direct exit B, B-th flip-flop matrix management is connected with B, B-m the output of the second group of outputs of the matrix control and B-input B-th element OR the output of which is connected with the B-th output of the third group of matrix management and with the release of the B-th element, the output of which is connected with the B-th output of the first group of the line matrix management.

Comparative analysis of the prototype shows that the inventive device is characterized by the presence of new elements: a generator of clock pulses, two counters, decoder, block matching, a group of transmission blocks, groups of blocks routing, matrix loading, the response matrix, the address of the matrix, the filtration unit, the information matrix, matrix management and matrix pair, and relevant connections with other elements of the scheme that meets the criterion of novelty of technical solutions.

In scientific and technical literature is not found, the device described by a set of new features. This allows to conclude that the technical solutions according to the criterion of "significant differences".

In Fig. 1 shows the structural diagram of the device of Fig. 2 is a structural diagram of a block matching; Fig. 3 is a structural diagram of a receiving unit of Fig. 4 is a structural diagram of the transmitting unit of Fig. 5 is a structural block circuit diagram of the routing of Fig. 6 is a block diagram of the matrix of the boot of Fig. 7 is a structural diagram of the response matrix of Fig. 8 is a structural diagram of the address matrix of Fig. 9 is a structural diagram of the group OR element of Fig. 10 is a structural block circuit filtros. 13 is a block diagram of the matrix of control.

Device for switching messages (Fig. 1) comprises a generator 1 clock pulses, a first counter is 2, the second counter 3, a decoder 4, block 5 of the agreement, the group receiving units 6.1 - 6.4, the group transmission units 7.1 - 7.4, the group of blocks routing 8.1 - 8.3, the matrix load 9, the response matrix 10, the address matrix 11, the filtering unit 12, an information matrix 13, the matrix control 14, a matrix of pair 15, a group of information inputs 17.1 - 17.4, group signal outputs 18.1 - 18.2, group signal inputs 19.1 - 19.4, the group of information outputs 20.1 - 20.4, a group of query inputs 21.1 - 21.4, a group of query outputs 22.1 - 22.2, internal communication 16, 23-44.

Unit 5 coordination (Fig. 2) contains a group forming elements 46.1 - 46.4, group of items OR 47.1 - 47.2, the group of items 48.1 - 48.4, the first trigger group 49.1 - 49.4, the second trigger group 50.1 - 50.4.

The receiving unit 6 (Fig. 3) contains the first element 51, the first counter 52, the first trigger 53, the second element 54, the second trigger 55, the second counter 56, the first element OR 57, the third element And 58, the receiving register 59, the third trigger 60, the fourth element And 61, the fourth trigger 62, the fifth trigger 63, item 64, the fifth element And 65,the first trigger 68, the first item 69, the first counter 70, the second counter 71, the second And gate 72, the second trigger 73, the third element And 74.

The block select line 8 (Fig. 5) contains a group element And 75, the register 76, a persistent storage device (ROM) 77.

Matrix download 9 (Fig. 6) contains a group of elements OR NOT 78.1 - 78.3, a group of delay elements 79.1 - 79.3, matrix triggers 80.11 - 80.34, matrix elements And 81.11 - 81.34, item, OR 82, the group of items-NOT 83.1 - 83.2.

The response matrix 10 (Fig. 7) contains the matrix elements And 84.11 - 84.34, group of items OR 85.1 - 85.4.

Address matrix 11 (Fig. 8) contains a matrix group elements And 86.11 - at 86.34, group of items OR 87.1 - 87.3.

Group element OR 87 (Fig. 9) contains a group of elements OR 88.1 - 88.S.

The filtering unit 12 (Fig. 10) contains a group of elements And 89.1 - 89.3, the first group of elements OR standard 90.1 - 90.3, matrix elements And 91.11 - 91.34, the second group of elements OR 92.1 - 92.4, a third group of elements OR 93.1 - 93.4.

The information matrix 13 (Fig. 11) contains the matrix elements And 94.11 - 94.44, group of items OR 95.1 - 95.4.

The matrix pair 15 (Fig. 12) contains the matrix elements And 96.11 - 96.44, group of items OR 97.1 - 97.4.

in OR 100.1 - 100.4, a group of items NOT 101.1 - 101.4.

In the device for switching messages K-th information input device 17 is connected to the information input of the output register 59 K-th output block 6, block select line 8 group outputs a persistent storage device 77 are connected respectively with a group of information inputs of the register 76, a group of information outputs of which are connected respectively with a group of information inputs of the group element And 75, the group of outputs of which are connected respectively with the group of outputs of the block select line 8, and the output 24 of the generator 1 clock pulses is connected with the first inputs receiving 6, transmission 7 blocks and with a counter input of the first counter 2, the output of which is connected to the counting input of the second counter 3, the group of information outputs of which are connected respectively with a group of inputs of the decoder 4, A-th output 31 which is connected to the first input of the A-th block select line 8, the second input is connected to the A-m output the first group of outputs 32 of the filtration unit 12, A group of inputs of the first group of inputs 36 which are connected respectively with the group of outputs of the A-th block select line 8, the group of inputs which are connected respectively with A-the sing of the outputs of the B-th output unit 6, A first output of the first group of outputs 32 of the filtration unit 12 is connected with A-m entrance of the first group of inputs of the response matrix 10 and matrix load 9, the group of 33 outputs which are connected respectively with the second group of inputs of the response matrix 10, the address of the matrix 11, the filtration unit 12 and unit coordination 5, the group of 29 outputs of which are connected respectively with the second group of inputs of the matrix load 9, the outlet 30 which is connected to the input of block matching 5, B-th output of the second group of outputs 26 of which is connected respectively with the fourth input of the B-th output unit 6, the second output 25 of which is connected to the B-th input of the first group of input block matching 5, the third group of inputs which are connected respectively with a group of inputs 28 response matrix 10, B-th information 17 and the signal 19 input devices are connected respectively with the second and third inputs of the B-th output unit 6, the first output of which is connected to B-m signal output device 18, B-th information 20 and request information 22, the outputs of which are connected respectively with the first and second outputs of the B-th transmitting unit 7, the second input is connected to B-m request from the input device 21, the third exit 44 B-th transmitting unit 7 is connected with the B-th input of the first GRU is 40 which is connected with the B-th input of the first group of inputs of the information matrix 13, B-th output 42 which is connected to the third input of the B-th transmitting unit 7, the fourth output 23 which is connected to the B-input of the third group of inputs of the matrix control 14, B-th output of the third group of outputs 16 which is connected to the fourth input of the B-th transmitting unit 7, the second group of inputs of the information matrix 13 and the matrix pair 15 are connected respectively with the second group of outputs of 41 matrix control 14, the first group of gate 37 which are connected respectively with the third group of inputs of the filtering unit 12, the second 38 and 39 third group of outputs which are connected respectively with the first and second group of inputs of the matrix control 14 in each block matching 5 B-d input 25 of the first group of inputs connected to the first input of the B-th element And 48 the output of which is connected to a single inlet B-th flip-flop 49 of the first group, zero dynamic input connected to the output of the B-th element 47, M inputs of which are connected respectively to the M inputs of the B-th group of the second group of inputs 33 of the block matching 5, input 30 which is connected on a second input B-th element And 48, a third input connected to the inverse output B-th flip-flop 50 of the second group, the direct output of which is connected to the input B of the second forming element 46, the output to the passages 28 which is connected to the zero input of the B-th flip-flop 50 of the second group, single dynamic input connected to the direct output of the B-th flip-flop 49 of the first group, the inverted output of which is connected to the inputs of all elements And 48 in addition to B-x, the first input of each receiving unit 6 is connected to the first input of the second element 54, the second inputs of the fourth 61 and 65 fifth element And with a counter input of the first counter 52, the output of which is connected to the first input of the first element 51, the output of which is connected with the second output 25 of the receiving unit 6, the second input 17 of which is connected to the information input of the output register 59, the group of outputs of which, corresponding to the direct outputs of the trigger that contains the address of the destination computer, connected respectively with the group of outputs 34 unit 6, the third inlet 19 which is connected to the first input of the sixth element And 67, the output of which is connected to the first output 18 of the receiving unit 6, the fourth inlet 26 which is connected to the zero input of the second trigger 55, the direct output of which is connected with the second input of the first element 51, the fifth input 43 of the receiving unit 6 is connected to a single dynamic input of the first flip-flop 53 and zero dynamic input of the third trigger 60, direct the output of which is connected with the control input of the output register 59, the information the unit 6 is connected with the second input of the second element And 54 and to the second input of the second element OR 66, the output of which is connected to the first input of the fifth element And 65, the output of which is connected to a clock input of the output register 59, the information trigger output the last digit of which is connected to a single dynamic input of the fifth trigger 63, the direct output of which is connected to the first input of the fourth element And 61 the output of which is connected to a summing input of the second counter 56 a subtractive input connected to the output of the second element 54, the information group of outputs of the second counter 56 are connected respectively with a group of inputs of the first element OR 57, the output of which is connected to the zero dynamic inputs of the first 53 and 62 fourth trigger, inverted output of which is connected to the first input of the second element OR 66, the direct outputs of the triggers of bits of the second counter 56 of the receiving unit 6 corresponding to the number of bits in the packet of information, are connected respectively to the inputs of the third element And 58, the output of which is connected to a single dynamic inputs of the second 55, 60 third and fourth 62 triggers and zero dynamic input of the fifth trigger 63, the output of the first element OR 57 of the receiving unit 6 is connected to the input element 64, the output of which is connected to a second input of the sixth Alamodome first element And 69, the output of which is connected to the counting input of the first counter 70 the output of which is connected to an inverted input of the first flip-flop 68 and the fourth output 23 of the transmitting unit 7, the second input 21 of which is connected to the zero input of the second trigger 73, the inverted output of which is connected to the first input of the third element And 74, the output of which is connected with the third output 44 of the transmitting unit 7, and the third input 42 which is connected to the direct input of the first flip-flop 68 and the first output 20 of the transmitting unit 7, the fourth input 16 which is connected to the input of the delay element 45, and a single dynamic input of the second trigger 73, the direct output of which is connected with the second input of the second element And 72, the output of which is connected with the second output 22 of the transmitting unit 7, the output of the second counter 71 emitting unit 7 is connected to the first input of the second element And 72, the output of delay element 45 emitting unit 7 is connected to a second input of the third element And 74, the direct output of the first flip-flop 68 emitting unit 7 is connected to the first input of the first element And 69, group inputs 35 of the block select line 8 is connected respectively with a group of inputs of persistent storage device 77 of the block select line 8, the first 31 and second 32 inputs which suhad first group of inputs 32 matrix load 9 is connected to the input of the A-th delay elements 79, the output of which is connected to the zero inputs of the triggers 80 A-th row of the matrix boot-9, B-d input of the second group of inputs 29 which is connected with the first inputs of elements And 81 B-th column of the matrix load 9, the inverted output A, B-th flip-flop 80 matrix load 9 is connected to a second input A, B-th element And 81, the output of which is connected to a single input A, B-th flip-flop 80, and the outlet of which is connected to A, B-m output 33 of the matrix load 9 and B-th entry of the A-th element OR NOT 78, the output of which is connected with A-m input element OR 82, the output of which is connected to the output 30 of the matrix load 9, the output of the first element OR NOT 87 78,1 matrix load 9 is connected to third inputs of elements And 81 of the first row, the first and second input element AND-NOT 83,1 and with the second input of the second element AND-NOT 83,2, the outputs of the third 78,3 and second 78,2 elements OR NOT the matrix load 9 connected respectively with the third inputs of the third and second row elements And 81 matrix of the load 9, the output of the second element OR NOT 78,2 matrix load 9 is connected to the first input of the second element AND-NOT 83,2, the output of the A-th element AND-NOT 83 matrix load 9 is connected to the fourth inputs A+1-th row elements And 81 matrix boot 9, A, B-th entry of the second group of inputs 33 holes of the matrix 10 of the United Inen with B-m output 28 of the response matrix 10, A-th input of the first group of inputs 32 which is connected with the first inputs of the A-th column elements And 84 response matrix 10, a, B-th entry of the second group of inputs 33 address matrix 11 is connected with the control input A, B-th group element And 86, the group of outputs of which are connected respectively to the B-th group of inputs of the A-th group element OR 87, the group of outputs of which are connected respectively with the A-th group of 35 outputs the address of the matrix 11, B-I group the first group of inputs 34 which are connected respectively with the group with the group of information inputs of the B-th column group elements And 86 address of the matrix 11, the S-th R-th group input group item OR 87 is connected with R-m-S-th element OR 88, the output of which is connected with S-m output 35 of the group element OR 87, B-th entry of A-th group of the second group of inputs 33 of the filtration unit 12 is connected to the B-th entry of the A-th group element And 89, B-th output of which is connected to the A-m to the B-input element OR 92 of the second group, the output of which is connected with the B-th output of the second group of outputs 38 of the filtration unit 12, B-d input of the third group of inputs 37 which is connected with the second inputs of the B-th row of the matrix elements And 91 of the filtration unit 12, the output of the A, B-th element And 91 of the filtration unit 12 is connected to the A-m to the B-input m-output tre B-th element And 91, the output of which is connected with the B-th entry of the A-th element OR 90, the output of which is connected with the control input of the A-th group element And 89 and A-m output the first group of outputs of the filtering unit 12, B, B-th entry of the second group of inputs 41 of the information matrix 13 is connected to a second input B, B-th element And 94, the output of which is connected to B-m B-input element OR 95, the output of which is connected with the B-th output 42 of the information matrix 13, B-th input of the first group of inputs of which 40 is connected with the first inputs of the B-th column elements And 94 of the information matrix 13, B, B-th entry of the second group of inputs 41 of the matrix pair 15 is connected to a second input B, B -, And 96, the output of which is connected with the B-th output of the B-th element OR 97, the output of which is connected with the B-th output 43 of the matrix pair 15, B-th input of the first group of inputs 44 which is connected with the first inputs of the B-th column elements And 96 matrix pair 15, B-th input of the first group of inputs 38 matrix control 14 is connected with the first inputs of elements And 99 B-th column of matrix management 14, B-th entry of the second group of inputs 39 which is connected with the second inputs of elements And 99 B-th row of the matrix control 14, exit B, B -, And 99 matrix control 14 is connected to a single input B, B-th flip-flop 98, inverted output inen with B, B-th output of the second group of outputs of 41 matrix control 14 and B-m B-input element OR 100, the output of which is connected with the B-th output of the third group of outputs 16 matrix control 14 and B-th element 101, the output of which is connected with the B-th input of the third group of inputs 23 which is connected to the zero inputs of flip 98 matrix management 14.

Device for switching messages is as follows.

Messaging dial-up device is in the form of packets. Each package also transmitted information also contains the address of the destination computer and begins with a single bit. The device allows switching packets of information transmitted over K duplex communication channels and processed using M units of route choice. On the submitted drawings shows a device for switching messages with the number K=4 and M=3, but in General the numbers K and M can be any integer.

Before you begin trigger 49,1-49,4 block 5 of the agreement, the counters 52, 56, triggers, 53, 55, 62, 63 register 59 of the receiving unit 6, the trigger 68, 73, counters 70, 71 of the transmitting unit 7, the register 76 of the block select line 8 triggers 80,1 - 80,34 matrix boot 9, triggers 98,11 - 98,44 matrix management 14 at the ptx2">

Processing the data packet begins with his entrance to the sequential code on one of the information input device 17.1-17.4.

Suppose that on the second information input 17.2 device received a packet of information. The fact of receipt of the package identified with the emergence of a single signal And 1 to direct the output of the last discharge the output register 59 receiving unit 6.2 (Fig. ). The service information received from the information input 17.2 device information input output register 59, bit it is recorded clock pulses from generator 1 clock pulses on connection 24 through the open element And 65 to the clock input of the receiving register 59. The register 59 is similar in design to the register delay data (for example, as chip K555IR9). In the output register 59 is storing package information during its processing in the device. The signal I. 1 arrives on dynamic single input trigger 63 and its leading edge installs it in one state, resulting to direct the output of the trigger 63 shows the potential of a single level P. 1. The potential of P. 1 is supplied to the second input element And 61 and opens it for prob the chick 56 is reversible counter, therefore, the first counting input performs the summation of the clock pulse generator 1 (the contents in this case corresponds to the number of transmitted bits of the packet), and the second counting input it produces the subtraction of the clock pulse generator 1 and its contents in this case is equal to the number of bits of the packet not yet transmitted. When the counting of clock pulses by the counter 56 on its information outputs appear potentials of single level, causing the output of the first element 57 is always the potential of a single level of P. 2. With the output element OR 57 potential P. 2 to the input of the element 64, it is inverted and, when the second input element And 67, closes it. This suggests that the receiving unit 6 (in this case, 6,2) at this time is not ready to receive other packages.

As the direct outputs of bits of the counter 56, corresponding to the number of bits in the packet in binary code, is connected with the input element And 58, the emergence of a potential single level P. 3 output element and 58 indicates that the receiving register 59 took the entire incoming packet of information. The potential of P. 3 goes on dynamic single input trigger 62 and its parenteral zero level. At the output of the OR element 66 also receive a zero potential level, which leads to the closure element And 65 for receipt of clock pulses from generator 1 to the clock input of the receiving register 59. The same potential P. 3, acting on the dynamic single input trigger 55, his front front sets it in one state. To direct the output of the trigger 55 appears the potential of single-level and element 51 is opened. The potential of P. 3 is fed to a single input trigger 60 and its leading edge installs it in one state, causing the potential of a single level with direct access to the trigger 60 is supplied to the control input of the output register 59 and stops it broadcast information.

The first counter 52 performs the functions of the frequency divider pulse. He carries out counting a given number of clock pulses of the generator 1, and then it turns itself is set in the initial state and its output pulse appears And. 2. Impulse And. 2 passes through the opened item And 51 and appears on the communication 25.2 device that indicates the request receiving unit 6,2 to establish switching with arbitrary free block 8 routing.

Communication device 29.2 impulse And. 3 is supplied to the first inputs of the elements And. 81.12, 81.22, at 81.32 matrix download 9 (Fig. 6) and only appears on the output of the element And 81.12, because initially all blocks 8 choice of route is not busy processing packets. Next impulse And. 3 is fed to a single input trigger 80,12 and puts it in one state, resulting in direct and inverse wybodaeth to the second input element And 81.12 and closes it for the passage of other pulses I. 3 on the first input element And 81.12. The potential of P. 7 is supplied to the second input of the element OR NOT 78.1, resulting in its output potential appears P. 9 the zero level, which is supplied to the first and second inputs of the element AND IS NOT 83.1, and its output appears potential P. 10 single level. The potential of P. 10 is supplied to the fourth input elements And 81.21-81.24, opens them and thus preparing for the download processing unit 8.2 routing. In addition, the potential of P. 9 is supplied to the third input elements And 81.11-81.14, blocking them from making other requests block 8.1 routing. The potential of P. 9 from the corresponding elements AND 78 are also input to the OR element 82, and once all the blocks 8 of the choice of route will be loaded by batch processing, the output element OR 82 will appear blocking the zero potential level, which communication device 30 enters the block 5 of the agreement. Thus, at any time, in any column or any row in the matrix load 9 can be located in a single state not more than one trigger 80. The appearance potential of P. 7 connected 33.12 device causes the output element OR 47.2 also appears potential P. 7, which goes to zero, the rigger 49 block matching 5 is in a single state only the settling time switching between the respective receiving unit 6 and the selected block 8 routing.

The potential of P. 7 communication 33.12 device is supplied also to the control input group item And 86.12 address matrix 11 (Fig. 8), opens it, and as a result, the address of the destination computer package came with a group of information outputs of the output register 59 group relations 34.2 via group element And 86.12 is supplied to the second group of inputs of the group element OR 87.1. As the number of items OR 88 group element OR 87 (Fig. 9) corresponds to the number of bits of the address of the destination computer package came and outputs of the group of elements And 86 connected as shown in Fig. 9, the output of the group element OR 87 receive the address of the destination computer package came.

This address group relations 35.1 comes on the ROM 77 unit 8.1 routing (Fig. 5). ROM 77 contains a routing table. On the address side of the package that contains the address of the destination computer, the ROM 77 selects the channel number of the issue (i.e., the number of the transmitting unit 7) which is stored in register 76. As a result, the information outputs of the register 76 and ludowego unit 7. Suppose, for further transmission of the data packet to the selected transmitting unit 7.3 (i.e., the third channel of issue).

The first counter 2 is a divisor of the number of pulses from generator 1 clock pulses. When reaching the stated conversion factor he spontaneously (offline) is in original condition and its output pulse appears, which is supplied to the counting input of the second counter 3. The maximum conversion rate of the counter 3 is selected so that the counter 3 had as many States as the device contains 8 blocks of route choice. In this case, the counter 3 can only be in three States 01, 10, 11 (state 00 in this case, it is forbidden). The decoder 4 performs decoding of the content of the counter 3, resulting in rotation on its outputs appears pulses I. 4. The pulse duration of the I. 4 depends mainly on the repetition period of the clock pulses from generator 1 and the multiplier counter 2 and is determined by the settling time switching between the selected block 8 of the route selection and the corresponding transmission unit 7. From the first output of the decoder 4 impulse that the number of the selected transmitting unit 7.3 comes on group relations 36.1 device to the first inputs of the group of elements 91.11-91.14 filtering unit 12 (Fig. 10). In this case, there will be a pulse So only 4 connected 36.13. If the transmitting unit 7.3 was busy transmitting another packet of information, in this case, there would be prohibiting the zero potential level with matrix management 14 communication 37.3 device, and the pulse And. 4 would not be passed through the element And 91.13. But as initially transmitting unit 7.3 free from transmission of other packets of information, the pulse And. 4 appears at the output of the element T.13, is fed to the first input element OR 93.3 and appears on the communication 39.3 device. Impulse So 4 passes through the element OR 90.1, is fed to the control input group item And 89.1 and rewrites the address of the receiving unit 6 with group ties 33.11-33.14 device via group element And 89.1, through a group of items OR 92.1-92.4 per group relations 38.1-38.4. As the pulse duration And. 4 more total time delay elements OR 90.1 and group element And 89.1, then exits the filtration unit 12 on the links 38.1-38.4 and 39.1-39.4 appear, respectively, and simultaneously the number of the receiving unit 6.2 and the number of the transmitting unit 7.3. In this case, appears impulses And. 5 single level on the relationships and 38.2 39.3 device. In addition, the impulse And. 4 element OR 90.1 comes th element And 84.12 there is the potential of a single level with regard 33.12 device), through the element OR 85.2 response matrix 10 and liaison 28.2 goes to zero input trigger 50.2 and sets it to zero state. With regard 32.1 impulse And. 4 is fed to the input of delay element 79.1 matrix download 9 (Fig. 6), the output of which is fed to the zero inputs of flip 80.11-80.14 and sets the trigger 80.12 in the zero state (triggers 80.11, 80.13, 80.14 confirms the zero state). The amount of delay of the delay element 79 a few more total time of actuation elements And 84 OR 85 and response matrix 10.

After that, the newly arrived packet is received for processing in block 8.2 choice of route, provided that the unit 8.1 routing is still busy processing the package.

Pulses And 5 liaison and 38.2 39.3 enter the matrix control 14 (Fig. 13). In the element And 99.32 is the coincidence of these pulses, resulting in a trigger 98.32 is translated in one state and its direct and inverse outputs appear respectively the potentials of isolated P. 8 P. and zero 9 levels. The potential of P. 9 is supplied to the third input element And 99.32 and block it for other pulses, and the potential of P. 8, you get in touch 41.32 device. When potential P. 8 on-link 41.32 ostogo, the potential of P. 8 output trigger 98.32 matrix management 14 passes through the element OR 100, you receive in touch 16.3 device is inverted and the element is NOT 101.3. The zero potential level of the output element is NOT 101.3 communication 37.3 enters the filtration unit 12 and blocks the establishment of all other possible communication with the transmitting unit 7.3. The potential of P. 8 communications 16.3 device is fed to a single dynamic input trigger 73 and through a delay element 105 to the second input element And emitting unit 74 7.3 (Fig. 4), resulting in a trigger 73 when the potential of P. 8 moves in one state and its potential single level with direct access opens the element I. 72. The amount of delay of the delay element 45 a few more trigger time trigger 73.

The counter 71 of the transmitting unit 7 (Fig. 4) acts as a divisor of the number of clock pulses of the generator 1. When its full, the counter 71 standalone is set to the initial state and its output pulse appears And. 6. Impulse And. 6 passes through the opened item And 72 and appears on the query output 22.3 device that indicates the request transmitting unit 7.3 to transmit the data packet. If the subscriber is ready to receive a package energyrom new impetus to the transfer request of the packet information to the inquiring output 22.3 device. Impulse And. 7 with a request output 21.3 device goes to zero input trigger 73, causing the element And 72 is closed, and the output element And 74 receive a potential P. 9 unit level, which is due 44.3 device passes through the opened item And 96.23, item, OR 97.2 matrix pair 15 and liaison 43.2 fed to a single input trigger 53 receiving unit 6.2. Forward front of potential of P. 9 translates the trigger 53 in one state, resulting in open items And 65, 54. In addition, the forward front of potential of P. 9 translates the trigger 60 in the zero state. To direct the output of the trigger 60, you receive a zero potential level, resulting in the output register 59 is set to the mode of transit information. Clock pulses from the generator 1 through the element And 65 to the clock input of the receiving register 59 is bit perfect the issuing information package on communication 40.2 device, and the contents of the counter 56 is reduced in accordance with the number issued by the bits of the packet.

Package information in sequential code with regard 40.2 device passes through the opened item And 94.32, item, OR 95.3 information matrix 13 on the link 42.3 device, where it enters the information the lending unit 6.2 will be issued to all bits of the data packet, the counter 56 will be set in the initial state and the output element OR 57 will change the potential from a single level to zero. This change of the potential corresponds to the trailing edge of the potential of P. 2. The rear front of potential P. 2, acting on the dynamic zero inputs of the triggers 53 and 62, installs them in the initial (zero) state. After this cycle of operation of the receiving unit 6 is repeated again when receiving a new packet of information.

The transmission of the first bit liaison 42.3 (he is always singular) leads to the fact that the trigger 68 emitting unit 72 (Fig. 4) is set in one state. The capacity of a single level with its direct access opens the item And 69 and the clock pulses from generator 1 arrive at the counting input of counter 70. The maximum conversion rate of the counter 70 is equal to the number of bits in the packet. After reaching maximum multiplier counter 70 is set in the zero state and its output pulse appears And. 8. Impulse And. 8 sets the trigger 68 in the zero state, stopping the supply of clock pulses to the counting input of counter 70, and appears to 23.3 communications device. Communication 23.3 impulse And. 8 is supplied to the zero inputs of flip 98.31-98.34 matricity.

After this cycle of device operation is repeated again.

Technical and economic effect of the proposed use of the device for switching message is that it can significantly improve the total performance processing an input stream of messages. This is achieved by the fact that the input packet stream is processed in a single block of route choice (as in the famous prototype), and their group. Moreover, the structure of the proposed device is that there is the possibility of increasing the number of blocks of the route (the number M can be any integer). This in turn allows the unit (in accordance with the number of blocks routing) to increase the performance and reliability of the functioning of the device. Improving the performance of the device allows to reduce the time delay of the transmitted packets of information that can improve the efficiency of distributed computing and computer networking.

Device for switching messages containing each of K (K is the number of full-duplex communication channels) output block register receive, and the K-th information input device connected with the information input receiving the new item, moreover, the group of outputs of the DC storage device is connected respectively with a group of information inputs of the register, the group of information outputs of which are connected respectively with a group of information inputs of the group member And the group of outputs of which are connected respectively with the group of outputs of the block select route, characterized in that it additionally introduced a generator of clock pulses, the first and second counters, decoder, block matching, a group of K transmission blocks, the group of M-1 blocks routing (M - total number of blocks routing), matrix loading, the response matrix, the address matrix, the filtration unit, the information matrix, the matrix and control matrix pair, and the output of the generator of clock pulses is connected with the first inputs receiving, transmitting blocks and with a counter input of the first counter, the output of which is connected to the counting input of the second counter, a group of information outputs of which are connected respectively with a group of inputs of the decoder, And the third output of which is connected to the first input of And-th block of route selection, the second input is connected to the a-m output the first group of outputs of the filtering unit, And the group of inputs of the first with which are connected respectively with a first group of outputs of the address matrix, In the group of inputs of the first group of inputs which are connected respectively with the group of outputs of the first receiving unit And the second output of the first group of outputs of the filtration unit is connected with a-m entrance of the first group of inputs of the response matrix and matrix download, group of outputs which are connected respectively with the second group of inputs of the response matrix, the address of the matrix, the filtration unit and block matching, the group of outputs of which are connected respectively with the second group of inputs of the matrix load, the output of which is connected to the input of block matching, In-th output of the second group of outputs of which are connected respectively with the fourth entry In the th output unit, the second output of which is connected with In-th input of the first group of inputs of the block matching, the third group of inputs which are connected respectively with the group of outputs of the response matrix In the second informational signal and the input device are connected respectively with the second and third inputs In-th output unit, the first output of which is connected with In-m signal output device, the second information, and inquiring the outputs of which are connected respectively with the first and second outputs In-th transmitting unit, the second input is connected to the In-m query input condition is th output of which is connected with the fifth entry In the th output unit, the third output of which is connected with In-th input of the first group of inputs of the information matrix, nd the output of which is connected with the third entry In th transmitting unit, the fourth output of which is connected with In-th input of the third group of inputs of matrix management, In-th output of the third group of outputs which is connected with the fourth entry In th transmitting unit, the second group of inputs of the information matrix and the matrix pair are connected respectively with the second group of outputs of the matrix control, the first group of outputs which are connected respectively with the third group of inputs of the filtration unit, the second and third group of outputs which are connected respectively with the first and second groups of input matrix control, and block matching contains a group of elements And, To a group of elements OR two groups of triggers and the group from forming elements, and the third input of the first group of inputs connected to the first input In-th element And whose output is connected with a single sign-In-th flip-flop of the first group, zero dynamic input connected to the output-element OR M inputs of which are connected respectively with M inputs In the second group the second group of inputs of block matching, an input connected to the direct output of which is connected to the input of In-th-forming element, the output of which is connected with In-m output the first and second groups of outputs of block matching, In-th input of the third group of inputs is connected to the zero input In-th flip-flop of the second group, a single dynamic input connected direct-th flip-flop of the first group, the inverted output of which is connected to the inputs of all the elements And, in addition to In-x, and To each of the receiving units introduced two counters, the six elements And two elements OR five triggers and the item is NOT, moreover, the first input receiving unit connected to the first input of the second element And the second inputs of the fourth and fifth elements And with a counter input of the first counter, the output of which is connected to the first input of the first element And whose output is connected to a second output of the receiving unit, a second input connected to the information input of the output register group which outputs corresponding to the direct outputs of the triggers that contains the address of the destination computer, connected respectively with the group of outputs of the receiving unit, a third input connected to the first input of the sixth element, And whose output is connected to the first output of the receiving unit, the fourth input connected to the zero input of the second trigger, direct Keskin input of the first trigger and zero dynamic input of the third trigger, direct the output of which is connected with the control input of the output register, informational output of which is connected with the third output of the receiving unit, the direct output of the first trigger receiving unit is connected to a second input of the second element And with the second input of the second element OR the output of which is connected to the first input of the fifth element And whose output is connected to a clock input of the output register, the information of the trigger output of the last discharge of which is connected to a single dynamic input of the fifth trigger, direct the output of which is connected to the first input of the fourth element And whose output is connected to a summing input of the second counter, the subtractive input connected to the output of the second element And information group of outputs of the second counter connected respectively with a group of inputs of the first element OR the output of which is connected to the zero dynamic inputs of the first and fourth trigger inverted output of which is connected to the first input of the second element OR direct outputs of the triggers of bits of the second counter receiving unit corresponding to the number of bits in the packet of information, are connected respectively to the inputs of the third element And whose output is connected to eogo trigger, the output of the first element OR the receiving unit is connected with the input element, the output of which is connected to a second input of the sixth element And To each of the transmitting units contains two triggers, the three elements, two counters and delay elements, and the first input of the transmitting unit is connected to the counting input of the second counter and a second input of the first element And whose output is connected to the counting input of the first counter, the output of which is connected to the negative input of the first trigger and the fourth output of the emitting unit, a second input connected to the zero input of the second trigger, inverted output of which is connected to the first input of the third element And whose output is connected to the third output of the emitting unit, the third input connected to the direct input of the first flip-flop and the first output of the emitting unit, a fourth input connected to the input of the delay element and a single dynamic input of the second trigger, the direct output of which is connected to a second input of the second element And whose output is connected to a second output of the transmitting unit, the output of the second counter of the transmitting unit connected to the first input of the second element And the output of delay element emitting unit connection the speed of the first element And moreover, the group of inputs of the block select route connected respectively with a group of inputs of persistent storage devices block routing, the first and second inputs which are connected respectively with the control input group element And with the input set to "0" of the register, and updates the download contains a group of M items, OR IS NOT, a group of M elements of the delay matrix To M triggers the matrix To M elements And the element OR group of K-1 elements AND IS NOT, moreover, the a-th input of the first group of inputs of the matrix load is connected to the input of the first delay element, the output of which is connected to the zero inputs of flip-th row of the matrix loading, In-th entry of the second group of inputs of which is connected with the first inputs of the elements In the-th column of the matrix download, inverted output And In-th flip-flop matrix load is connected to the second input of the And-element And whose output is connected to a single input, In-th flip-flop, and the outlet of which is connected to A, In-th matrix output loading and In-input-element OR NOT, the output of which is connected with a-m input element OR the output of which is connected to the matrix output load, the output of the first element OR NOT the matrix load connected to the third inputs of elements And the first what about the items OR NOT the matrix load connected respectively with the third inputs of the third and second rows of cells And matrix download the output of the second element OR NOT the matrix load is connected to the first input of the second element AND IS NOT, the output of the And-element AND-NOT matrix load is connected to the fourth inputs And the+1-th row elements And matrix load, and the response matrix contains a matrix m To the elements And To a group of elements OR, and And, In the second entry of the second group of inputs of the response matrix is connected to the second input of the And-element And whose output is connected to a-m input-element OR the output of which is connected with In-m output response matrix, And nd the entrance to the first group which is connected with the first inputs of elements And a-th column of the response matrix, and the address matrix contains a matrix M To group elements And group M group elements OR, and And, In the second entry of the second group of address inputs of the matrix is connected with the control input, In-th group member And the group of outputs of which are connected respectively with the second group of inputs of the A-th group element OR the group of outputs of which are connected respectively with a first group of outputs of the address matrix, In the group of inputs of the first group of inputs which are connected respectively with a group of information inputs In the-th column group elements And address of the matrix, and a group element enta OR R-th group is connected with R-m-S-th element OR the output of which is connected with S-m output group member OR, with the filtration unit contains a group of M group elements And the first group of M elements OR a matrix of M To elements And the second and third groups of elements OR, with-th input And the second group the second group of inputs of the filtering unit connected to the In-input-th group element-th output of which is connected with a-m input-element OR the second group, the output of which is connected with In-m output of the second group of outputs of the filtering unit, the second input of the third group of inputs is connected to the second inputs In the-th row of the matrix elements And the filtration unit, the output of And-element And the filtration unit is connected with a-m input-element OR the third group, the output of which is connected with In-m output of the third group of outputs of the filtering unit, And the d input of the first group of inputs is connected to the first input of And-element And the output of which is connected to the In-input-element OR the output of which is connected with the control input of the A-th group element And with a-m output the first group of outputs of the filtering unit, and the information matrix contains a matrix To the elements And To a group of elements OR, moreover, In the second entry of the second group of inputs full information is which connected with In-m output information matrix, In-th input of the first group which is connected with the first inputs of the elements In the-th column of the information matrix, and the matrix of the pairing matrix contains K elements And a group of elements OR, moreover, In the second entry of the second group of inputs of the matrix pair is connected to a second input, In-th element And whose output is connected to In-m login-th element OR the output of which is connected with In-th matrix output pair, In-th input of the first group which is connected with the first inputs of the elements In the-th column of the matrix pair, and matrix management contains a matrix To trigger the matrix To the elements And, To a group of elements OR group of elements is NOT, and In the-th entry of the first group of inputs of the matrix control is connected with the first inputs of the elements In the-th column of matrix management, In-th entry of the second group of inputs of which is connected to the second inputs of the elements In the th row of the matrix control, output, In-th element And matrix management is connected with a single sign-In, In-th flip-flop, an inverted output of which is connected to the third input, In-th element And direct access To In-th flip-flop matrix control connected with In In-m output of the second group of outputs of the matrix management and In-m login-th element OR whose output with In-m output the first group of outputs of the matrix management In-th input of the third group of inputs of which is connected to the zero inputs of flip-th row of the matrix control.

 

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SUBSTANCE: digital serial transfer of information through interface between electronic device and accumulator connected to it is a transfer of bytes consisting of row of bits. Each bit is determined by one of levels, high level or low level, and first bit of each byte is a first level of said high and low levels. Method includes stage of transfer of other level from said low and high levels during first time span immediately before said first bit.

EFFECT: higher efficiency.

3 cl, 4 dwg

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