Device for the formation of linear-frequency-modulated signal

 

(57) Abstract:

Usage: the invention relates to techniques for radio communication and can be used in transmitting and receiving devices for the formation of linear frequency modulated (chirp) signal. The aim of the invention is to develop a device that generates the chirp signal in a wide frequency band and providing a constant amplitude signal at its output. The purpose of the invention is achieved by designing the device forming the BEAM signal containing three accumulating adder 1, 2 and 3, two multipliers 4 and 5, a digital-to-analogue Converter (DAC) 6, an amplifier 7, an inverter 8 and the controller 9. Ring the inclusion of blocks 1, 4, 2, 5 and 8 provides recurrent calculation of the instantaneous values of the generated signal in a wide band of frequencies, and the use of a multibit DAC and amp with a deep negative feedback provides the ability to get a signal with constant amplitude and high spectral characteristics. 1 C.p. f-crystals, 11 ill.

The invention relates to techniques for radio communication and can be used in transmitting and receiving devices for the formation of linear frequency modulated (chirp) signal is class. H 03 C 3/08, 1991, ed.St. USSR N 1674345, CL H 03 C 3/08, 1991, ed.St. USSR N 1631598, CL H 03 C 3/08, 1991, which are driven generators with different systems of tuning the frequency of the generated signal. However, the use of the proposed devices analog elements (driven generators, sawtooth, bandpass filters, etc) makes them sensitive to external influences (ambient temperature, voltage, power sources and other).

Closest to the proposed device is a device for the formation of the chirp signal auth.St. N 1617621, CL H 03 C 3/08, 1991. This device consists of two accumulative adders NS, combined adder, two blocks of memory, digital-to-analog Converter DAC, switch, switch, block filters, frequency divider by M, meter, generator start-up pulses, pulse generator, frequency divider with variable division factor DPCD, with the release of the first NA is connected to the first input of the combinational adder, the output of which is connected to the input of the second NA. The output of the second NA is connected to the input of the first memory block, the output of which is connected to the input of the DAC. The DAC output is connected to the first input of pietrov, the input which is the output device. The output of pulse generator run is connected with the second inputs of the first NS combinational adder with inputs of the counter and the pulse generator. The output of the pulse generator is connected to the inputs DPCD and frequency divider by M the Output of the frequency divider by M is connected to the third input of the first NA and combinational adder. The output of the counter is connected with the second input of the second memory block. The first, second, third and fourth outputs of the first memory block is connected to the first input of the first of the national Assembly, a second input switch, a second input DPCD and the fourth input of the combinational adder, respectively.

Output DPKG connected with the second input of the switch. In this device codes phase of the generated signal is read from the second memory block is stored in the first NA is converted to a quadratic mean in the second NA and are used as addresses for reading codes instantaneous values of the generated chirp signal from the first memory block. Read from the first memory block codes instantaneous values are converted to an analog signal using a DAC, and through the filter circuitry receives the output device. The extension of the frequency range of formiruemogo.

The disadvantage of the prototype is a distortion of the spectral characteristics of the generated chirp signal in a wide band of frequencies, the instability of the amplitude of the signal at the output of the device, as well as the need to store a sufficiently large number of codes instantaneous values of the generated signal in the first memory block.

The aim of the invention is to develop a device that provides undistorted formation of the chirp signal in a wide band of frequencies and a constant amplitude signal at its output, as well as the simplification of the circuit device.

This objective is achieved in that in the known device, containing the first and second NA, DAC, inputs of the first and second multipliers Mind, power Condition, the third of the national Assembly, the inverter control unit SU, the SU is Input pad input device. The first input of the first NA is connected to the output of the inverter, whose input is connected to the output of the second Mind. The first of the national Assembly, the first Mind, the second of the national Assembly and the second Mind is enabled cascade, with the output of the first NA is additionally connected with the input of the DAC. The DAC output is connected to the input Condition, and the output of the latter is an output device. The first release of CS simultaneously connected to the second inputs of the first, second and third of the national Assembly, and estwenno to the third, fourth inputs of the first national Assembly, the second to fifth inputs of the first Mind, third, fourth inputs of the second national Assembly, the second to fifth inputs of the second Mind and the third and fourth input of the third NA. The output of the third national Assembly connected to the sixth input of the first and second Mind. Ring the inclusion of the first national Assembly, the first Mind, the second national Assembly, the second Mind and inverter allows recurrent calculation of the instantaneous values of the generated signal in a wide band of frequencies, and the use of a multibit DAC and amp with a deep negative feedback provides the ability to get a signal with constant amplitude with high spectral characteristics.

In Fig. 1 shows a block diagram of the device forming linear-frequency-modulated signal of Fig. 2 is a structural diagram of the accumulating adder of Fig. 3 is a structural diagram of the combinational adder of Fig. 4 is a block diagram of the register of Fig. 5 is the circuit of the multiplier of Fig. 6 is a block diagram of the amplifier of Fig. 7 is a block diagram of the inverter of Fig. 8 is a structural diagram of a control device; Fig. 9 is a structural diagram of a binary counter of Fig. 10 is a block diagram of the decoder of Fig. 11 is a timing diagram illustrating the works is about 4 and a second 5 Mind, DAC 6, Intelligence 7, an inverter 8 and SU 9. Entrance SU 9 is a pad input device and the first input of the first national Assembly 1 is connected to the output of the inverter 8, the inlet of which is connected to the output of the second Mind 5. First NA 1, the first Mind 4, the second national Assembly 2 and the second Mind 5 includes a cascade, with the output of the first NA 1 additionally connected with the input of the DAC 6. The DAC output 6 is connected to the input Condition 7, and the output of the latter is an output device. The first outputs SU 9 simultaneously connected to the second inputs of the first 1, second 2 and third 3 NS, and the first input of the latter is connected to the second output YY 9. From the third to the sixteenth output SU 9 connected respectively to third and fourth inputs of the first NA 1, the second to the fifth input of the first Mind 4, third, fourth inputs of the second NS 2, the second to fifth inputs of the second Mind 5, third and fourth inputs of the third NA 3. The output of the third national Assembly 3 is connected to the sixth input of the first 4 and second 5 the Mind.

Included in the overall structural pattern blocks can be implemented as follows.

The first 1, second 2 and third 3 NS identical. In Fig. 2 presents a diagram of the first NA 1, which comprises combinational adder CS 1.1, the first 1.2 and 1.3 second registers, and the first input of the adder 1.1 is the first entrance is ucen to the second input COP 1.1. Second input registers 1.2 and 1.3 are the third and fourth inputs of the first NA 1, and the third inputs of these registers are combined and a second input of the first NA 1.

An example implementation of the COP 1.1 can serve as a functional unit on the chip CIS (Integrated circuits. The Handbook. Ed. by B. C. Tarabrina. M. : Energoatomizdat, 1985, S. 64). When organizing summation shestnadtsatimetrovy numbers, the scheme COP 1.1 represents a parallel connection of the proposed circuits, which are shown in Fig. 3. Thus the inputs A1, A2, A3 and A4 of the respective IC are the corresponding bits of the first input to the COP and the inputs B1, B2, B3 and B4 of the same IC are the corresponding bits of the second input of the IC. In addition, the input of P0the first IC is grounded, and its output P4connected to the input of P0the second IC. Similarly, the outputs of the P4the second and third circuits connected to inputs of P0the third and fourth IC. The output of the P4the fourth IC is not activated. The outputs of the S1, S2, S3, S4are the corresponding bits of the output of the COP.

Registers 1.2 and 1.3 are similar and can be implemented on parallel enabled triggers, for example, eight chips K155TM2, each of which sod is Hema register 1. in Fig. 4. While the D inputs of the triggers are the corresponding bits of the first input register of 1.2, and their direct outputs Q are the corresponding bits of the output register. Inverted outputs of the triggers remain unused. C-usadi triggers are the corresponding bits of the second input register. The third input of the register is setup, and depending on the required initial setup, connected either with R or S-inputs of the triggers, and the connection with the R-input of the trigger matches an entry when you initially set up the logical units in the corresponding category set number, and the connection with the S-input is a logical zero.

The second registers of all the national Assembly, and the first register of the second NS require initial setup corresponding to the number zero (connect S-inputs of the triggers with the second input register). The first register of the national Assembly 1 requires initial setup, one with the second input register of the R-inputs of the triggers). The first register of the national Assembly 3 requires installation of a number corresponding to the starting frequency of the chirp signal on each step, depending on which with the second input of the register are connected to either S or R inputs of the respective flip-flops.

The first and second Mind 2 and 3 according to the automatic control. The Handbook. Ed. by S. T. Horsetail. Leningrad:Mashinostroenie, 1987, S. 339, Fig. 10, 9a). The circuit of the Mind on the proposed IC shown in Fig. 5. Entrance DY this IC is first input of the Mind, and the entrance DX IC - his sixth input. Inputs TCY and TCX shorted to the case, and inputs CLRE and CLKX are connected and are the second entrance the Mind. Inputs STB, CLKP, and OE IC are the third, fourth and fifth inputs of the Mind, and the output of the DP IC is the Mind. The increase in processed Mind numbers up to sixteen possible by combining multiple IMS when using additional adders. The scheme of such associations found in the literature (Microprocessors and microcomputers in automatic control systems. The Handbook. Ed. by S. T. Horsetail. L.:engineering, 187, S. 339, Fig. 10, 9b). At the same time as the release of the Mind are sixteen high-order bits of the output DP of gure schema.

DAC 5 can be implemented on the IC diode keys and described in the literature (D. Bakhtiarov in. A. Malinin, V. P. scalin. Analog-to-digital converters. Ed. by D. Bakhtiarov. M:Soviet radio, 1980, S. 68). As input the proposed DAC is used twelve high-order bits of the output of the national Assembly 1.

Condition 6 can be implemented on the IC CAD. This IM). Here is a diagram of the activation of the IC. Using the proposed IC in the proposed device, you must connect the output 10 IC with negative input 5. In Fig. 6 shows an amplifier circuit for the device to accommodate these changes.

The inverter 8 may be implemented using adders on IC CMOS and items NOT on the IC KLN, which are described in the literature (integrated circuits. The Handbook. Ed. by B. C. Tarabrina. M.: Energoatomizdat, 1985, S. 64, 67). In Fig. 7 shows one variant of the inverter. The corresponding bits of the input of the inverter through the elements NOT connected to inputs A1...A4 adders SM1...SM4 Inputs S1 adders connected to inputs B2, the input S2 of the adders are connected to the inputs B3, inputs S3 adders connected to inputs of B4. The output S4 of the first adder connected to the input of the second adder, the output S4 of the second adder connected to the input B1 of the third adder, and the output S4 of the third adder connected to the input B1 of the fourth adder. On input B1 of the first adder is energized, the corresponding logical unit. In addition, the outputs of the P4first, second and third adders respectively connected to inputs of P0second, third and chetvertogo and fourth adders are the outputs of the inverter 8.

SU 9 shown in Fig. 8, includes clock (GTI) 9.1, the first and second binary counters 9.2 and 9.3, the first and second decoders 9.4 and 9.5, the trigger 9.6, item 9.7 NOT, the item 9.8 And 9.9 register, and sign-SU 9 is first input of the trigger 9.6 and the first output YY 9, and inputs item 9.7 and NOT register 9.9, and the yield of the latter is the second exit SU 9. The outputs of the trigger and 9.6 item 9.7 are NOT the first and second inputs of the element And 9.8, and the output of the latter is the first inputs of binary counters 9.2 and 9.3. Second input of the binary counter 9.2 connected to the output of the GTI 9.1, and its output is the input of the first decoder 9.4. In addition, the upper discharge outlet of the first binary counter 9.2 is the second input of the second binary counter 9.3, and the output of the latter is the input of the second decoder 9.5. The output of the second decoder 9.5 is the second input of the trigger 9.3. From the first to the fourteenth outputs of the first decoder 9.4 are 3-16 outputs YY 9.

The GTI 9.1 can be implemented as described in the literature (I. S. Potemkin. The functional components of digital automation. M. Energoatomizdat, 1988, S. 240, Fig. 7, 9b).

The first and second binary counters 9.2 and 9.3 are identical and can be implemented is goatmeat, 1985, S. 63) Scheme including the proposed counter shown in Fig. 9. The inputs of the element And a counter connected to the first input of the first binary counter 9.2 and input C1 is his second entrance. The input of the counter C2 is connected to the output 1 of the counter, and outputs 1, 2, 4, 8 IC are the outputs of a binary counter.

Trigger 9.6 is a complete, functional site and described in the literature (Chips and their application. The Handbook). M.: Radio and communication, 1983, S. 118), and its first entry is the R input and the second input - 's entrance.

Item 9.7 is NOT functionally complete node and can be implemented on the IC CLN described in the literature (Integrated circuits. The Handbook. Ed. by B. C. Tarabrina. M.:Energoatomizdat. 1985, S. 67).

Item 9.8 And also is a complete, functional site, and can be implemented on the IC CLI described in the literature (Integrated circuits. The Handbook. Ed. by B. C. Tarabrina. M.: Energoatomizdat, 1985. S. 67).

Register 9.9 can be implemented similarly registers 1.2, 1.2 (Fig. 4). The feature is that as it uses only a third input register of 1.2, and the other inputs remain unused. Link is riadenie signal frequency according to the rules described above.

The first decoder 9.3 can be implemented on the IC KID and CLN described in a known literature (Chips and their application. The Handbook. M. : Radio and communication, 1983, S. 70, 67). In Fig. 10 shows a diagram of such a decoder. Wires 2 and 3 inputs of the decoder are connected to the inputs X2 and X3 IC. Inputs X2 and X5 both IC decoder and are connected by wire 1 to the input of the decoder, and the United inputs X1 and X6 are the wires 8 of the input of the decoder, and these inputs the second IC is connected to the wire 8 through the element is NOT. The outputs Y1-Y8 both the IC are connected to the inputs of the elements is NOT, the outputs of the latter are 3-16 outputs YY 9.

The second decoder is 9.5 decoder team the end of the device and may be implemented similarly to the first decoder 9.4 except that its output is the final output of the proposed first decoder 9.4.

The proposed second counter 9.3 and the second decoder 9.5 allow to generate the chirp signal duration sixteen periods. If necessary, the signal with most of the time you must use the binary counter and decoder with a large number of bits.

The proposed device for the formation of the chirp signal/P> The solution to this equation is approximate method in which the differentials are replaced by finite increments the values of the variables. The functions of integration perform the first 1 and second 2 NS. Thus the solution of equation (1) reduces to the solution of the equivalent integral equation of the form:

u(t) = - w(t) u(t)

moreover, other elements, namely the first 4 and second 5 Mind, the inverter 8, completing the feedback loop and provide recurrent calculation codes instantaneous values of the generated chirp signal.

To obtain the code values of the output voltage is used, the initial setting values in the first 1, second 2, third 3 NS and CS 9, and in the first 1 NS records a value of 1, the second 2 NA - 0, third 3 NS is the number corresponding to the initial (lower) frequency of the generated chirp signal, and SU 9 - number corresponding to the increment frequency for each cycle of the calculation of instantaneous values. Subsequent numbers corresponding to the voltage generated by the chirp signal derived from the sequential accumulation of these numbers in the national Assembly on the ring: the first NA 1, the first Mind 4, the second NA 2, the second Mind 5 and the inverter 8.

The proposed device operates as follows. When the settlement of the et on the second inputs of the first 1, the second 2 and third 3 NS. Thus it is recorded: in the first NA 1 number "1"; the second NA 2 numbers "0"; in the third NA 3 numbers that defines the start frequency of the generated chirp signal.

In addition, SU 9 on the second output generates a number that specifies the increment of the frequency of the generated signal in the calculation of the next value of its voltage.

Next, SU 9 begins to form at the outputs (from the third to the sixteenth) control pulses which are fed to corresponding inputs of blocks of the proposed device and make it work. In Fig. 11 shows timing diagrams of the generated control pulses, and U0the voltage at the generator output clock pulses, U1-U14- voltage respectively on the third sixteenth outputs YY 9.

On the first and second cycles of operation of the device by the control pulses on the SU 9 on the third and the fourth input of the first NA 1, the latter carries out the reading recorded during the initial installation number, which is supplied to the first input of the Mind 4 and DAC 6. On the third, fourth, fifth and sixth cycles, at the expense of control pulses coming from the fifth to the eighth output SU 9 on the second to fifth inputs Mind 4, OYe generated signal, served with an output of the third NA 3 at its second input. The result of the multiplication is output through the Mind 4 is supplied to the first input of the second NA 2.

For the next two cycles at the expense of control pulses coming from the ninth and tenth output SU 9 on the third and fourth inputs of the second NS 2, the latter carries out addition received at the first input and the stored numbers. The result of addition is stored in the national Assembly, and is supplied to the first input of the second Mind 5.

For the next four cycles using control pulses coming from the eleventh to the fourteenth outputs SU 9 on the second to fifth inputs of the second Mind 5, the latter produces a multiplication of the number of received output NA 2 at its first input the number corresponding to the code start frequency and the received output NS 3 at its sixth input. The result of multiplication through the inverter 8 is supplied to the first input of the first NA 1.

For the next two cycles at the expense of control pulses coming from the fifteenth and sixteenth outputs SU 9 on the third and fourth inputs of the third NA 3, the latter carries out the addition of the stored number corresponding to a code initial frequency of the generated signal and the number corresponding to the code of nature 3 and goes on his way out.

On subsequent cycles the first NA 1 performs the addition of the stored number and the number coming from the output of the inverter 8. The process is recurrent calculation is repeated according to the above-described sequence.

Formed on the release of the first NA 1 number arrives at the input of the DAC 6, which converts the codes of numbers into an analog signal corresponding to the chirp generator signal. The outputs of the DAC 6 is fed to the input Condition 7, which it amplifies and the absolute negative feedback provides a constant amplitude chirp signal in the output device.

Bit numbers circulating in the circuit of the first NA 1, the first Mind 4, the second NA 2, the second Mind 5, the inverter 8 is selected sufficient (in this case, the number of sixteen bits) to ensure the accuracy of the calculation of the numbers corresponding to the voltage generated by the chirp signal.

Since the outputs of the first 4 and second 5 the Mind is the result of multiplying two sixteen-bit numbers represented tridtsatidvuhletny number, at the entrance of the national Assembly 2 and the inverter 8 is only sixteen high-order bits and low-order bits are discarded.

Since the bit DAC 6 ( in this case twelve) miniso the input is only twelve senior ranks with the release of the first NA 1, and low-order bits are discarded. Use of a larger number of digits in the calculations than is used DAC 6 allows to reduce the calculation error due to accumulation of errors.

As an example, calculations of instantaneous values generated chirp signal when calculating omega = 0,5176 and increment frequency = /324000000 . The results of the calculation are given in table. 1 and 2, and in table. 1 shows the results of samples generated signal at the initial time period of operation of the device, and table. 2 - in the middle of the operating time of the device.

The analysis of the results of the proposed device must be noted that entered during the initial installation of the third NA 3 code start frequency and SU 9 code increment frequency on each step must provide at least six or seven times the voltage generated signal for one period of the highest frequency. In this case, the level of higher harmonic signals will not exceed 60 dB.

The initial frequency generated LMC signal is determined by the frequency of the clock pulses and the initial installation of the third NA 3. The upper frequency of the generated signal is also determined by the frequency of the clock pulses and, in addition to that is">

All NS are similar. As an example, consider the work of the first NA 1 (Fig. 2).

When it arrives at the second input of the first NA 1 pulse initial installation it arrives simultaneously at the second input of the first 1.2 and 1.3 second register. In accordance with their design is carried out in the first register 1.2 number "one", and in the second case the number "zero". When the stored number is the number "one" .

On the first stroke operation of the device at the third entrance of the first NA 1 receives the control pulse, which, coming on the third input register 1.2, provides at its output the number "one". This number from the output of the first register 1.2 is fed to the input of the second register 1.3. On the second quantum device operation control pulse arriving at the fourth input of the first NA 1, is fed to the third input of the second register 1.3 and ensures the formation at its output the number received at its input. Formed at the output of the second register 1.3 number arrives simultaneously at the output of the first NA 1 and the second input of the combinational adder. Coming to the first input of the first NA 1 number arrives at the first input of the combinational adder which performs addition with a number, which is present n the stated order. Storing the cumulative number is in registers 1.2 and 1.3, and cascade connection of these registers prevents back together on one stage of the national Assembly.

Registers 1.2 and 1.3, are part of the first NA 1 are identical, so consider their work on the example of the first case 1.2.

During setup, the momentum of the initial installation, supplied to the second input register 1.2 enters the R and S inputs of flip-flops based on the recorded number. During operation of the device, upon receipt of a control pulse to the third input of the register 1.2, it simultaneously opens the triggers of all discharges and provides for the formation of their Q-outputs of the logic unit (if the momentum of the initial setup was applied to the R input) or a logical zero (if the setup pulse was applied to the S input). The Q-outputs of flipflops are the output of the register, written during setup, the number will be transferred to the output register. In the process, the first input register of 1.2 enters the number that is on the D-inputs of flip relevant bits. At the next stage of the register, the control pulse supplied to the third input of the register, its front open front the or zero depending on the voltage on their D-inputs.

The inverter 8 is as follows. Arriving at its input the number, in the form of a voltage corresponding to the value of a logical unit or a zero for the corresponding discharge is fed to the inputs of the elements is NOT that its invert and served on the A-inputs combinational adder. To the resulting inversion number is added to a logical unit, which is supplied to the first B-input combinational adder. Describes the connection of the respective inputs and outputs provides a logical addition. Get on the S-output combinational adder voltage serves on the corresponding bits of the output of the inverter. Generated by the inverter 8 so the number is opposite in relation to the number applying for his entrance.

SU 9 provides for the operation of all devices and works as follows. When the input device triggering pulse of rectangular shape, he is simultaneously supplied to the input of the register 9.9, input element 9.7 NOT, R-trigger 9.6 and to the first output SU 9 which provides the initial installation of the first 1, second 2 and third 3 NS. While its leading edge triggering pulse writes the number corresponding to the increase of frequency n is the logical unit, and the output of the item 9.7 signal corresponding to the zero. Thus at the first input element 9.8 And receives a voltage corresponding to a logical unit, and the second input is a logical zero. At its output element 9.8 And generates a voltage logical zero, which, on entering the first inputs of the first 9.2 and 9.3 second counters, gives a "ban" on account received on their second input pulse.

At the end of the triggering pulse, his back-to-back forms the input element 9.7 NO voltage logical zero, which, in turn, generates at its output the voltage of the logic unit and delivers at its second input element 9.8 Acting As first and second inputs of the element 9.8 And there is a voltage corresponding to a logical unit, it generates at its output, the voltage of the logic unit that, when the first inputs of the first 9.2 and 9.3 second binary counter is permissive to start working the last.

Generator 9.1 clock pulses generates a sequence of rectangular pulses, which with its output go to the second input of the first binary counter 9.2. When you release the tension on his first entrance, he machineswomen number regarded pulses. Formed the first binary counter 9.2 number with its output fed to the input of the first decoder 9.4, which, depending on the received at its input number, generates the control pulse on one of its outputs. The timing diagram of the sequence of clock pulses and control pulses at the outputs of the first decoder shown in Fig. 11.

The pulses of the high-order digit number formed by the first binary counter 9.2, proceed to the second input of the second binary counter 9.3, which, in the presence of the enabling voltage at its first input, performs account and generates at its output the number corresponding to the number received at its input pulses. Formed by the second binary counter 9.3 number is fed to the input of the second decoder 9.5. When completing the second binary counter 9.3, the second decoder 9.5 generates at its output a pulse of completion of work, which goes to the S-input of the trigger 9.6. Trigger 9.6 generates at its output a voltage corresponding to a logical zero, which is entered at the first input element And 9.8, provides for the formation of the last signal "ban" for the first 9.2 and 9.3 second binary counters. This unit completes what about the device provides for the formation of the chirp signal in a wide band of frequencies with constant amplitude.

1. Device for the formation of linear-frequency-modulated signal containing the first and second accumulating adders and d / a Converter, characterized in that it additionally introduced the first and second multipliers, the amplifier, the third accumulating adder, inverter, control unit, input of which is a trigger input device, information input of the first accumulating adder connected to the output of the inverter, whose input is connected to the output of the second multiplier, the output of the first accumulating adder connected to the first information input of the first multiplier, the output of the latter is connected to the information input of the second accumulating adder, the output of which is connected to the first information input of the second multiplier, the output of the first accumulating adder is additionally connected to the input of digital to analog Converter whose output is connected to the amplifier input and the amplifier output is the output of the device, the installation output control unit also connected to set inputs of the first, second and third accumulative adders, and the information input of the third accumulating adder is connected to the signal output added the second control inputs of the first accumulating adder, to the first to fourth control inputs of the first multiplier, the first and second control inputs of the second accumulating adder, the first to fourth control inputs of the second multiplier and to the first and second control inputs of the third accumulating adder, and the output of the third accumulating adder connected to the second information inputs of the first and second multipliers.

2. The device under item 1, characterized in that the control unit consists of a generator of clock pulses, the first and second binary counters, the first and second decoders, the trigger elements are NOT, AND register, and the first input trigger input element and the input of the register are combined and simultaneously starting the input device and the installation access control unit, the generator output clock pulses is connected to the read input of the first binary counter, the output of which is connected simultaneously to the read input of the second binary counter and to the input of the first decoder, the output of the second binary counter is connected to the input of the second decoder, the outputs of the trigger element is NOT connected respectively to first and second inputs of the element And whose output is connected to the host I is item outputs of the first decoder are clock outputs, and the output of the register is the output signal of the increment of the frequency control unit.

 

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1 cl, 1 dwg

Phase-shifter // 2288532

FIELD: converter engineering; controlling thyristor voltage regulators used, for instance, for stepless start of induction-motor drives.

SUBSTANCE: proposed device has control signal supply labeled PHASE SHIFTER INPUT, voltage-to-frequency converter 1, first 2AND gate 2, binary adding and subtracting counters 3 and 4, respectively, input 5 for connecting pulse supply to set initial conditions in counters 3 and 4, digital comparator 6, second 2AND gate 7, and input 8 for connecting pulse supply to control power thyristors. Proposed device relates to class of systems performing two input signal dependent sweep functions generated in counters 4, 4 under impact of output pulses arriving from pulse voltage-to-frequency converter 1. Thyristor control pulse is generated at moment when numbers in adding and subtracting counters 3 and 4 are equal.

EFFECT: enhanced noise immunity and precision.

1 cl, 5 dwg

FIELD: semiconductor engineering; generating pulsed or continuous-wave control signal by semiconductor switch isolated from input control circuit.

SUBSTANCE: proposed method includes conversion of input-section supply voltage into current pulses through input section of coupling transformer, current pulse amplitude being limited by controlling pulse length and repetition rate, as well as discrimination of semiconductor-switch sawtooth control signal across coupling-transformer output section. To this end rise time of current pulse amplitude is set through output section of coupling transformer to desired level not to exceed critical value and in order to turn on or off semiconductor switch or to maintain it in on- or off-position voltage discriminated in one direction is checked upon expiration of desired time interval counted from moment of first threshold level of voltage across coupling transformer output section for its rising above second threshold level, first threshold voltage being set not to exceed threshold voltage of semiconductor switch and second threshold voltage, to be higher than minimal permissible control voltage for semiconductor switch; check results are used to regulate voltage in one direction discriminated across coupling-transformer output section in semiconductor switch control circuit.

EFFECT: enhanced reliability and stability of semiconductor switch control characteristics.

1 cl, 9 dwg, 4 ex

FIELD: transformation equipment, possible use for systems for impulse-phase control of thyristor transformer with phase adjustment by magnetic amplifier, possible use in conjunction with other phase-shifting devices.

SUBSTANCE: invention allows phase adjustment of control impulses for thyristors, coupled in counter-phase manner, by one-phased magnetic amplifier with self-saturation with necessary spectrum limitations of adjustment angle range independently on value of resulting magnetic amplifier control signal in two-channel and single-channel control circuits, also allows synchronization of operation of impulse generator with magnetic amplifier, independently on power voltage value and circuit of connection of working windings of the amplifier. In accordance to the invention, during control of thyristors with phase adjustment by magnetic amplifier and generation of output impulse of thyristor control by means of relaxation impulse generator on one-transition transistor with RC-circuit by discharging charged capacitor of RC-circuit onto primary windings of impulse transformer, circuits of working winding of magnetic amplifier and relaxation generator are powered by rectified trapezoid shape voltage supply, synchronized with voltage of powering network, in accordance to the invention, on appearance of powering voltage impulse the capacitor of RC-circuit is charged up to value of activation of one-transition transistor with time constant corresponding to maximal control angle and set by resistor of RC-circuit, and on appearance of control impulse from output of magnetic amplifier the capacitor is charged up to transition activation voltage through another resistor with time constant corresponding to minimal adjustment angle.

EFFECT: ensured serviceability of control system with phase adjustment by magnetic amplifier at any value of resulting control signal; expanded arsenal of technical means.

4 cl, 5 dwg

FIELD: engineering of systems for impulse-phase control of thyristors of three-phased converter, made in accordance to zero and bridge, asymmetric or symmetric, circuits of connection of power thyristors with phase adjustment by magnetic amplifier.

SUBSTANCE: using known method for controlling thyristors of three-phased transformer with phase adjustment by magnetic amplifier and generation of thyristor control impulses by means of relaxation impulse generator on one-transition transistor with RC-circuit by discharging charged capacitor of RC-circuit onto primary winding of impulse transformer, in accordance to invention, phase adjustment by magnetic amplifier is performed by thyristors connected to one of transformer phases, circuits of working windings of magnetic amplifier and impulse generator are powered by rectified trapezoid voltage, synchronized with voltage of the phase, while on appearance of powering voltage impulse, RC-circuits of impulse generator are charged up to voltage of activation of one-transition transistor with time constant, corresponding to maximal angle of transformer adjustment and of RC-circuit set by resistor, and on appearance of control impulse from output of magnetic amplifier, capacitor is charged up to transistor activation voltage through another resistor with time constant corresponding to minimal control angle, and impulses for controlling thyristors connected to next two phases are generated 120 el. after appearance of impulse for controlling thyristors of previous phase.

EFFECT: reduced scattering of characteristics of transformer control systems, limited thyristor control angle range in required spectrum, independently of value of magnetic amplifier adjustment control signal.

3 cl, 2 dwg

FIELD: transforming equipment, possible use in systems for impulse-phase control of reverse thyristor transformer with phase adjustment by magnetic amplifier and used for powering anchor circuit of constant current electric motor.

SUBSTANCE: in accordance to the invention, during control of thyristors of reverse transformer with separate control of two mutually-parallel coupled groups of thyristors, phase adjustment of each group is performed by magnetic amplifier with electrical comparison of setting voltage and check connection voltage, proportional to electric motor rotation frequency, and in accordance to invention, in absence of setting by shifting signals, magnetic amplifiers are closed and control impulses of both groups are removed. On appearance of setting, control impulses are sent to corresponding group of thyristors, enabling it in rectifying mode. After brake or reverse command, working group is transferred to inverter mode with maximal adjustment angle, with time delay control impulses for the group are removed and second group of thyristors is enabled also with maximal value of adjustment current, value of which is then decreased until motor EMF exceeds average voltage value of inverter group which begins to let through the braking current of motor, which is limited by current cut-off in the future. At the end of braking at reverse, second group is transferred to rectifying mode, and during transferring to lower speed after the motor reaches given rotation frequency the second group is again transferred to operation with maximal adjustment angle, with time delay control impulses for the group are removed and first group of thyristors is enabled in rectifying mode with new given value of electric motor rotation frequency.

EFFECT: ensured serviceability of reverse thyristor transformer with phase adjustment by magnetic amplifier, used for powering anchor circuit of constant current electric motor, in whole range of adjustment, and expanded arsenal of technical means; control of thyristors of reverse transformer without compensating currents in whole range of adjustment.

3 cl, 2 dwg

FIELD: transformation equipment engineering, possible use for controlling reverse thyristor transformer of constant current or thyristor voltage regulator, for example, to ensure smooth launch of asynchronous electric motors.

SUBSTANCE: device contains control signal source (input of phase-shifting device), adder, amplitude modulator, integrator, 2 relay elements, logical element "XOR", three logical elements "2AND", subtracting "n"-bit binary counter, input for connecting a supply of supporting voltage, generator of stable frequency impulses, adding "n"-bit binary counter, digital comparator, logical element "kAND", where n>k, mono-stable multi-vibrator, logical element "2OR", input for connecting the source of control impulses for power thyristors. Device belongs to the class of integrating systems with two digital scanning functions. One scan is independent and is generated due to generator of stable frequency impulses. The second scan is dependent, which is generated from control signal, and transformed due to impulse signal from output of voltage transformer to impulse frequency. Command for managing power thyristors is generated at the time moments when numeric values of independent and dependent scanning functions are equal or exceeded.

EFFECT: increased interference resistance, increased precision.

4 dwg

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