Discrete-analog sine-generator

 

(57) Abstract:

The invention relates to electronics and can find application in devices for generating a voltage sine wave, for example, as local oscillators for frequency converters or frequency synthesizers kalogiratou and low-frequency ranges. The purpose of the invention is the increase of the operating frequency range while improving the shape of the generated oscillations by eliminating switching noise and reduce the relative share of noise quantization and sampling. The goal is based on specific properties of the gray code used the four-digit pulse counter 2 in gray code to count 32 unit intervals that make up the half period of the voltage sine wave. During and "reflected" cycles account is the generation of each half-wave rectified quasisinusoidal when 7 pulse sequences with outputs four IK triggers significant digits of the counter pulse control signal inputs combinational logical elements 3, which generates a set of eight pulse sequences, each of which during the positive phase connects to score predstavljaet a sequence of pulses of rectified quasisinusoidal, sequentially switched through pollperiod when converting to signal good as utility power form. Discrete-analog sine generator comprises a generator G of pulses of the unit 1, the four-digit pulse counter 2, the combinational logical block elements 3, outputs 1 - 8 eight terminal of which is connected to the anodes of respective pairs of diodes 4.1 - 4.8, forming with them a set of eight switches current for 8 outputs functionally-weighted current sources 5.1 - 5.8, the current source 5.0 zero offset compensation pair of diodes 4.0, ballast resistor 6, a switch 7, the low pass filter 8, the output bus 9, the inverter polarity and mark 10, managing IK-trigger 11, the element matches 4I and 12 and two voltage source 13 and 14. 2 Il., table 1.

The invention relates to electronics and can find application in devices for generating sinusoidal signals, such as local oscillators for frequency converters or frequency synthesizers kHz and low frequency ranges.

Similar to the proposed device can serve as a "Scheme for the formation of sinusoidal oscillations" /1/ providing digital generation of voltage sine is nice account fea 4-bit binary counter pulses MS 14024, combinational logic circuit MS 14030 two XOR, and bipolar functionally-weighted Converter phase in the amplitude element MS 14051 was end-to-end operational amplifier and two different voltage sources.

The closest in technical essence to the proposed device generator subsonic /2/ containing the generator 1 rectangular pulse of unit of account, a four-digit reversible counter 2 pulse, the diodes 3-6 connecting the conclusions of the four weighting resistors from 8-11 set to (20-23the outputs of significant digits of the count pulses, the node currents 7, including the joint conclusions of the weighting resistors 8-11 and the output of the ballast resistor 12, RS-flip-flop 13, which provides forward and reverse direction account when forming each half period of the periodic curve of the accounts D-flip-flop 14, which, by controlling the switch 16, sequentially switches the operation modes of the operational amplifier 15, forming quasisinusoidal, the low pass filter 17, the tire 18 output, resistors 19, 20, 21 and the element 22 that serves as a decoder zero state of the counter 2 counts, the output pulses to the ptx2">

At the beginning of the formation of each half-cycle rectified quasisinusoidal counter 2 pulse mode is a direct account from the initial state 0000, which is caused by the installation of the RS-trigger 13 in "1" state, a positive pulse is received at the S-input from the output element 22 OR NOT. In the process account to the ballast resistor 12 is formed stepwise increasing voltage corresponding to the front half of quasisinusoidal, and the voltage corresponding to the downturn, when the transition counter mode count from the intermediate state 1000 to 0000 source, after switching RS-flip-flop 13 is in state "0", a positive pulse is received at its R input 23output counter 2 pulse.

The positive pulses at the beginning of each half-cycle of the generated oscillations from the output of the counting D-flip-flop 14 to E-switch input 16, connect the signal output of the ballast resistor 12 to the not inverting input of the operational amplifier 15, working in repeater mode. Thus at the output generated positive half good as utility power curve. Negative half-wave is formed at the output of the operational amplifier 15 with a closed switch 16, when the conditions is that the action of the feedback circuit R20/R19.

The generated signal is good as utility power form, smoothed by the filter 17 of the lower frequencies is supplied to the bus 18 to the output device.

Considered a prototype /2/ is a device with limited performance, increase range of operating frequencies which rests against the technical limitations inherent in the reversible counter 2 pulse with a serial circuit controls the direction of counting. In such a structure that uses positional binary code (MPC), with continuous removal of the data set of weighting resistors 8-11 and decoder 22 of the zero state of the counter at the signal output of the ballast resistor 12 and the output element 22 arise switching noise of a small time - "needles" generated events through the transfer unit of account in the pulse counter and the switching of the invoice without its stop.

The level of these noise increases considerably if you want to use the element base of high performance and neutralization of impacts will require additional technical solutions, complicating the device.

The purpose of the invention is the increase of the operating frequency range of the discrete and analog devices with improved f the project.

The goal is based on specific properties of the gray code used four-pulse counter for counting 32 unit intervals that make up the sum of the half period of the sinusoidal signal of the form.

While direct and indirect cycles account is the formation of each half of quasisinusoidal when 7 outputs the significant digits of the counter pulses bitwise manage seven signal inputs combinational logic structure that generates a set of eight sequences of pulses, each of which during its positive phase sequentially connects to the ballast resistor corresponding functionally-weighted current source, and the result of the summation of the currents represents a sequence of voltage pulses of stepped form in the form of a positive half-wave rectified quasisinusoidal, with steps of discretization that are multiples of /32 , where the time interval corresponding to /32 is a unit of account.

Using synchronous counter pulses in the gray code for bitwise control signal inputs combinational patterns, which generates a set of eight axisymmetric sequences Chania corresponding current source of the analog part of the device, due to the following reasons:

1. Since the gray code has a single code length, each increment of the unit causes a change of state only one discharge pulse counter, then this essentially eliminates the interference switching - "needles" on the outputs of the elements matches due to the exclusion of matches of different variations on their inputs.

2. When calculating the 2nfirst unit received at the input n-bit counter, in its structure, the conditions for the formation of the signal transfer in the estimated (n+1)-th digit, and all the n least significant bits remain in a state of reflective account when it continued to state 100...0, the numerical value of which is(2n+1-1).

The above feature of the four-digit code is used synchronous pulse counter for continuously counting 32 pulses of the unit of account for direct and indirect cycles account.

When forming each half-wave quasisinusoidal with the base 32 of the unit interval four significant digits, the pulse counter is changed as follows: * 0000(0), * 0001(1), * 0011(2), ... direct bill to* 1000(15), * 1000(16), next, the reflected invoice * 1000(15) the ez accounting exclude fifth, indicated by the symbol *.

In Fig. 1 shows an electrical schematic diagram of the device of Fig. 2 - temporal correlation, explaining its operation; and used logical equations, the estimated quantitative ratios and logical displaced involved in the process discrete-analog conversion are summarized in table given in the description.

The table includes 9 lines, each of which argument is the current increment of the current Iiacting within the appropriate phase sector of the half-wave generated quasisinusoidal.

In column 3 of table 8 source logical equations describing each phase of the sectors of a certain durationiand variants of these equations is transformed to perform operations only two elements.

In column 4 of table 8 combinational circuits second order boundary changes capacity L/H and H/L, forming 8 positive pulses that make up the pyramid, as a practical example of the implementation of the functions described by the transformed equations of column 3 of the table.

These 8 combinational circuits, United eponymous signal potential seven signal inputs and eight parallel outputs.

Each of its outputs, representing the output of the open collector terminal of the transistor element, which in combination with the anode of a respective pair of diodes of the parallel set 4.1-4.8 forms one of the eight switches of the current, which is connected to the output of the respective current generator from a parallel set of 5.1-5.8.

Discrete-analog sine generator (Fig. 1) contains a generator G 1 pulse unit, the output of which is connected with e0input pulse counter 2, the combinational logical block elements 3, which is equipped with a family of 1, 3, 4-8 signal inputs and eight 1-8 outputs, 9 pairs of diodes 4.0-4.8, each of which the cathode of the first diode is connected to the anode of the second diode 9 generators 5.0-5.8, inputs are combined and connected to a source of voltage+U" 13, ballast resistor 6, the second output of which is connected to the shared bus, the switch 7, the output of which is connected to the input of the low pass filter 8, the inverter polarity and mark 10, the power supply input of which is connected to the voltage source minus U ' 14, managing JK flip-flop 11 and the element of coincidence 4I 12, the output of which is connected to the J and K inputs of the control of the JK flip-flop Q output of which is connected to the input of the inverter Polaroid ballast resistor and nine cathodes, combined, the second of nine diodes 4.0-4.8 pairs of diodes, the anode of the first diode of each pair of diodes, the first 4.0 ninth 4.8, is connected to the output of the respective current generator, with the first 5.0 on the ninth 5.8, and the output of the lowpass filter connected to the output bus 9 discrete-analog sine generator, and the pulse counter 2 is made in the form of a four-bit synchronous counter pulses in the gray code without preset initial condition and equipped with eight outputs of significant digits and e0QO-sync output, which is connected to the C input of the control of the JK-flip-flop 11, and the first 1 signal input combinational logical elements 3 connected to the Q1 output of the first discharge pulse counter, 7 second signal input combinational block of logic elements connected to the Q4 output of the fourth digit counter pulses, the third 3 signal input combinational block of logic elements connected to the Q2 output of the second discharge pulse meter, 5 fourth signal input combinational block of logic elements connected to the Q3 output of the third discharge pulse counter, fifth 4 signal input combinational block of logic elements connected to the second discharge counter is and pulse counter, seventh 8 signal input combinational block of logic elements connected to the fourth discharge pulse counter, and the first, second, third and fourth inputs of the element matches 4I connected respectively to the outputs of the respective digits of the count pulses, the current values of the nine generators, with the first 5.0 on the ninth 5.8 in the order listed, functionally weighted in proportion to the unit, which corresponds to the maximum value of the sinusoidal shape, as 0,049, 0,098, 0,143, 0,181, 0,162, 0,138, 0,109, 0,075, 0,038, and combinational block of the logical elements in the form of combinational logical block elements with eight outputs in accordance with the expression 1 corresponds to the first output, which is connected to the 5.1 output of the second generator current signal type 2 corresponds to the second output that is connected to the output of the third 5.2 power generator, signal type 3 corresponds to the third output, which is connected to the output of the fourth 5.3 power generator, signal type corresponds to the fourth 4 output, which is connected to the output of the fifth 5.4 current generator, the signal type corresponds to the fifth 5 output that is connected to the output of the sixth 5.5. generator current signal type corresponds to the sixth 6 wry connected to the output of the eighth 5.7 current generator, signal type corresponds to the eighth 8 output, which is connected to the output of the ninth 5.8 power generator.

The work of the sine generator (Fig. 1 and 2) is considered on the example of forming one period of oscillation quasisinusoidal (O.7 of Fig.2) from 0 to 2 for two counted by pulse counter 2 64 unit intervals (e0Fig. 2). Each of the half cycles of the 32 interval is formed with a direct account from 0 to 16 and reflected from 16 to 0 second (Q1, Q2, Q3, Q4 Fig. 2).

The pulses of the unit of account from the output of generator G1 is continuously output at e0-input four-bit synchronous pulse counter 2, a diagram of which elements miratransas communication and chain synchronization elements 2.2.0-2.2.4 account as an example running a similar scheme known pulse meter, used in synchronous frequency divider 3.

When forming each of the half-wave quasisinusoidal (Ref. 7 of Fig. 2) four significant digits Q1, Q2, Q3, Q4 of the counter pulses are sequentially transferred from the mode in direct mode the reflective account.

Let us assume the initial state of the device, which coincides with the first zero of the positive half wave of quasisinusoidal (O. 7 of Fig. 2).

When applying for e0input pulse zero is 2 enters the matching synchronizing pulse (eoQO Fig. 2) with a repetition period 2T0that switches managing JK flip-flop in the state of "unit" (O. 11 of Fig. 2) because its J and K inputs. since the end of the preceding echo cycle accounts were opened gate-pulse zero (O. 12 Fig. 2) generated by the element matches 4I 12, when significant bits Q4, Q3, Q2, Q1 of the counter pulses in the two periods account 2T0was in a state 0000.

The positive pulse Output. 11 of Fig. 2) with the Q-output of the control of the JK-flip-flop 11 to the input of the inverter polarity and mark 10, and the generated pulse output. 10 Fig. 2) negative level and polarity of its output goes to the second (control) input switch 7, is presented as an example of executing a known scheme with the change of the sign of the output voltage of 4 on field transistor with an operational amplifier (op-amp).

When elektrownie zero pulse sequence e0QO (Fig. 2) gate-pulse zero (O.12 Fig. 2) with a duration equal to two periods of the unit, when the JK-flip-2.2.1-2.2.4 significant digits of the counter pulses are able 0000, at each of the eight outputs 1-8 combinational logical elements 3, there is the potential saturation malayter 6 (Ref. 7 of Fig.2) there is only a voltage offset created by the current Iogenerator 5.0, connected in series with the anode of the compensation pair of diodes 4.0, and the current Iieach and eight generators 5.1-5.8 drains into a common bus through a saturated transition To a-e open transistor of one of the outputs 1-8 combinational logical block elements.

When applying for e0input (e0Fig. 2) pulse counter 2 of the first, second, fourth, sixth, eighth, tenth, twelfth and fourteenth pulse unit of account, common-mode, with the same natural delay closed the transistors of the first, second, third, fourth, fifth, sixth, seventh and eighth terminal elements combinational block of logic elements. When this occurs stepwise formation of the front for the first half of quasisinusoidal (Ref. Fig. 2) from the level-shifted zero 0,049 to the maximum value 0,993 through a serial connection to the ballast resistor 6 of each of the eight 5.1-5.8 functionally-weighted generator current I1-I8the sequential firing of each of the pairs of diodes set 4.1-4.8.

With the arrival of e0-input pulse counter 2 keswani quasisinusoidal.

During the echo cycle, when the fourteenth, twelfth, tenth, eighth, sixth, fourth, second and first pulses of the unit in reverse sequence opens the transistor terminal elements on 8-1 outputs of the combinational block of logic elements, sequentially locked pair of diodes from a set 4.8-4.1, disconnecting from the ballast resistor 6 current generator 5.8-5.1.

With the arrival of e0input count pulses of the clock of the second zero ends forming a first half-wave quasisinusoidal (Ref. Fig. 2), and then there is a formation of the second half, starting from level zero offset reference amplitude.

Both formed of the half-wave rectified quasisinusoidal with bases (Ref. 7 of Fig. 2) are present at the first input of the switch 7, when his output is formed by a stepped signal (the Output. 7 Fig 2) sinusoidal in managing its phase with the signal generated by the inverter polarity and mark 10.

In the first half of the period from 0 to the pulse Output. 10 Fig. 2) negative level coming from the output of the inverter polarity and mark 10 on the second (control) input switch 7 switches it off the field tra is connected to the first half-wave rectified quasisinusoidal (Ref. Fig. 2), and the output switch is Closed. 7 of Fig. 2) there is a positive veluvana quasisinusoidal.

When forming the negative half of quasisinusoidal from up to 2 managing JK flip-flop 11 is switched into the state of "zero" pulse sequences (e0QO Fig. 2) received on the C-input at the time of the second zero.

This zero potential with its Q output is inverted to a zero potential at the output of the inverter polarity and mark 10 (O.10 Fig. 2), which includes field-effect transistor switch 7, when connecting through a rich transition of the SOURCE-DRAIN to a common bus reinvestible entrance of the shelter.

Since the signal output of the ballast resistor 6 is continuously connected through the first resistor of the feedback circuit to the inverting input of the OS, then the output of the switch in this half-period of the negative half-wave of quasisinusoidal.

During the formation of the following periods of the sinusoidal signal of the form described process is repeated several times.

The low pass filter 8 to the output device smoothes the form of stupenchatogo good as utility power voltage obtained by sampling and quantization.

The proposed discrete-Anani with the repetition period T=64T0where T0- period of the pulse repetition unit of account, by eliminating switching noise generated by the elements counting schemes implemented in the prototype; ensure combinational logical block elements have the same natural delay of boundary changes L/H and H/L capacity, limiting the width of each of the phase sectors; use the analog part of the device known way discrete-analog conversion phase in amplitude using a parallel set of eight switchable functional-weighted generators stable current from the summing element at the output.

Literature:

1. Titze., Shek, K. Semiconductor circuitry: TRANS. with it. - M.: Mir, 1982, Fig.24.19, page 454.

2. SU, 1358062, AI, 4 H 03 B 19/12, H 03 K 4/92, C. F. Voropaev, generator subsonic, 621.374(88.8), 7.12.87. Bull. N 45.

3. RF patent N 2037957, 6 H 03 K 23/42, Synchronous frequency divider, C. A. Ostrovsky, 1995. Bull. N-17, Application N 5065077/10 from 20.07.92,

4. Titze, K. Schenk Semiconductor circuitry: TRANS. with it. - M.: Mir, 1982, Fig. 17.14, page 282.

Discrete-analog sine generator containing the pulse generator units of account, the output of which is connected to the l0-whodo eight outputs, nine pairs of diodes, each of which the cathode of the first diode connected to the anode of the second diode, nine current generators whose inputs are combined and connected to a source of voltage+U, ballast resistor, the second terminal of which is connected to the shared bus, the switch, the output of which is connected to the input of the lowpass filter, the inverter polarity and sign, the power supply input of which is connected to the voltage source "-U", managing JK flip-flop and the element of coincidence 4I, the output of which is connected to the J and K inputs of the control of the JK-flip-flop, The Q-output of which is connected to the input of the inverter polarity and sign, the output of which is connected to the second input of the switch, the first input of which is connected to the first output of the ballast resistor and nine cathodes, which are combined, the second diode nine pairs of diodes, the anode of the first diode of each pair of diodes, the first through the ninth, is connected to the output of the respective current generator, the first to ninth, and the output of the lowpass filter connected to the output bus discrete analog of the sine generator, characterized in that the pulse counter is made in the form of a four-bit synchronous counter pulses in the gray code without preset initial condition and equipped with eight Q1, Q2, Q3, Q4 Vera, and the first signal input combinational block of logic elements connected to the Q1 output of the first discharge pulse counter, a second signal input combinational block of logic elements connected to the Q4 output of the fourth digit counter pulses, the third signal input combinational block of logic elements connected to the Q2 output of the second discharge pulse counter, the fourth signal input combinational block of logic elements connected to the Q3 output of the third discharge pulse counter, the fifth signal input combinational block of logic elements connected to the output of the second discharge pulse counter, the sixth signal input combinational block of logic elements connected to the output of the third discharge pulse counter, the seventh signal input combinational block of logic elements connected to the output of the fourth discharge pulse counter, and the first, second, third and fourth inputs of the element matches 4I connected respectively to the outputs of the respective digits of the count pulses, the current values of the nine generators, from first to ninth in the order listed, functionally weighted in proportion to the unit, which corresponds to the Maxim the definition of elements in the form of combinational logical block elements with eight outputs in accordance with the expression where the signal type corresponds to the first output, which is connected to the output of the second current generator, the signal type corresponds to the second output that is connected to the output of the third current generator, the signal type corresponds to a third output that is connected to the output of the fourth current generator, the signal type corresponds to the fourth output that is connected to the fifth output of the current generator, the signal type corresponds to the fifth output that is connected to the sixth output of the current generator, the signal type corresponds to the sixth output that is connected to the output of the seventh current generator, a signal type corresponding to the seventh output, which is connected to the eighth output of the current generator, the signal type corresponds to the eighth output, which is connected to the output of the ninth power generator.

 

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