Digital multiband frequency synthesizer

 

(57) Abstract:

The invention relates to measuring and computing and can be used in systems of digital signal processing. To form the ensemble of periodic signals of the frequency divider with variable division factor (CPCD) 2 together with the read-only memory (ROM) 4 and the counter ROM 3 form a source of periodic signal, whose frequency is determined by the code generated by the counter 7. With the arrival of the next pulse of the sample on the bus 13 state of the counter 7 changes and initiates a synchronization unit (BS) 1. After running BS 1 pulses from the clock generator 10 receives the divider CPCD 2 and the frequency divider with a fixed division factor (CFCD) 5, forming at the output of the ROM 4 sine wave signal received via the digital commutator (CC) 12 on the data bus registers storing and recording information (HSI) 8 and 9. Output divider CFCD 5 pulses of records coming through the Central Committee on 12 outputs the write registers of HSI 8 and 9 and the address counter 6. The latter generates an address at which a write signal output from the ROM 4. The mode of operation of the Central Committee of 12 is determined by the state of the trigger 11. Aggregate, and also provides asynchronous exchange of digital data. 1 Il., table 1.

The invention relates to measuring and computing and can be used in systems of digital signal processing, as well as the basic device for the discrete Fourier transform (DFT) of the signal.

Known frequency synthesizers, which can be used to solve the problem of formation of an ensemble of harmonic signals with a uniform grid of frequencies (see ed. St. USSR, CL H 03 B 21/02 NN 657577, 845262, 964965, 1109861, 1365345, 1427553).

The main disadvantage of frequency synthesizers described in the ed. Holy NN 1427553, 964965, 1365345, CL H 03 B 21/02, is the limited number of output signals: they all have the same output. For the formation of an ensemble of N harmonic signals required N frequency synthesizers. This way you can solve the problem of formation of an ensemble of harmonic signals. In this case, we use a set of independent generators to obtain oscillations with the required frequency. Obviously, this method of formation of an ensemble of harmonic signals is simple, but requires a lot of hardware as a consequence, limits the amount of an ensemble of harmonic signalboost generator provides a reference oscillator 1, frequency multipliers 8 and 9, block the formation of high frequency 2, which in turn consists of a controlled oscillator 4, a mixer 5, the phase detector 6, the LPF 7. In addition, the multi-frequency generator contains blocks PLL, the output of which is formed of a frequency grid signals. Since each harmonic frequency of the grid corresponds to a separate block PLL, then the extension of the frequency grid, the number of required blocks of the PLL can achieve this limit, when the device will be physically impossible for technical or economic reasons. For a given multi-frequency generator should be noted complex algorithm of interaction between functional units, which determines the complex method of starting-up and adjustment and requires high qualification of the Adjuster.

The above analogues digital frequency synthesizer have one common drawback, namely the complexity and the limited size of the ensemble of harmonic signals.

Known digital multi-channel synthesizers grid frequency (CMSC) closest to the technical essence is a frequency synthesizer according to ed. St. USSR N 1608777, CL H 03 B 19/00 (analog).

Programmable multichannel Chiusi generator 4, shaper 5 pulses, the register 6 offset, and the counter 7, the first 8 and second 9 switches, the second 10 and 11 third memory blocks.

In order to analyze the shortcomings of the device selected as the analogue, the following should be noted.

Digital signal processing in real time based on the quantization of time and further quantization level continuous signal.

The basic quantization parameter time is the sampling period Tdor the sampling frequency Fd. Will continue to operate with the concept of the sampling period. Numerical values of the digital data is tied strictly and precisely on time points, resulting from the quantization of time.

Therefore, in digital devices, including digital frequency synthesizers operating in real time, must be an explicit or implicit way bus sample rate. After initiating pulses on the bus sample rate of the digital device begins the process for processing digital data according to defined algorithms with the aim of obtaining a certain result. In the case of multi-channel digital synthesizers, the result is a group of digital C is galow. Comparing the phase values to the values of the amplitudes occurs, usually in the ROM. Exactly implemented comparison of amplitudes and phases in the claimed device and the device are similar. All the results obtained in the development of digital amplitude signals belong to the previous or subsequent to the interim report. Now the question arises about the possibility and method of use of the digital results generated in digital frequency synthesizer. The device according to ed.mon. N 1608777 implements a synchronous way using numerical results. During the period of sampling uniformly in time unfolding sequence of addresses, which indicates the channel number, and synchronously with the addresses generated digital values of the amplitudes of the periodic signals. It is evident that the transmission of information to the user (processor or digital processing unit) must be synchronous and as a user can only be specialized processors (special processor). In other words, the device according to ed.mon. N 1608777 part of a particular setprocessor and is not the finished structure from the point of view of digital signal processing, that is, liaudin on the accuracy of the installation of frequencies, is a collection of elements: the master oscillator 4, the adder 1, a storage unit 2, the shift register 6 and the relationships between them. Presents a collection of elements at the output of the shift register 6 generates digital values of the phases. The rate of change of phase, determines the frequency of the generated signals, which will be equal to

Fo= NIfabout/2n+m,

where Fo- output frequency generated signals;

fabout- reference frequency oscillator;

NI- control code information input;

m+n-bit shift register.

Analysis of the expression (1) shows that the discrete frequency setting (frequency step or frequency grid) is equal to fabout/2m+n. In this expression, the denominator is the binary number that is almost insurmountable obstacle if you need to create a decimal grid frequency, not to mention the formation of arbitrary grid frequency, In this case, there is one way for the formation of the decimal grid frequency is used as a master oscillator device with a binary reference frequency. According to information available to the author, in the domestic e producers, Omsk) produce highly stable oscillators "sonnet" - 5000 kHz and "Hyacinth" - 10000 kHz.

The basic calculation, presentation and interpretation in most fields of science and technology using the international metric system (decimal). Therefore, the use of devices on the bus.mon. N 1608777 leads to selection of the parameters in the expression (1) for the approximation to the metric of the frequency step. The degree of approximation to the desired grid of frequencies determines the setting error frequencies. This approximation is associated with an increased capacity of digital elements and therefore increase the cost of manufacture of the device. Therefore, as a second drawback of the device is similar methodological setting error frequencies.

Thus, a programmable multi-channel digital frequency synthesizer for ed. mon. N 1608777 has a truncation error of installation of frequencies and has functional limitations.

The aim of the invention is to improve the accuracy and functionality.

This objective is achieved in that, in the digital multi-channel frequency synthesizer containing a clock generator, uhodi merged, digital switch, the address input of the read which is connected to the address bus, and the output of the address counter is connected to the input of the address recording digital switch, inputs the clock trigger, the frequency divider with variable division factor, the address counter a persistent storage device, a frequency divider with a fixed division ratio of the counter, the synchronization unit, the first input is combined with the inputs of the counter and a clock trigger and connected to the bus sampling rate, the second input of the synchronization unit is connected to the output of the clock generator, and a third input connected to the output of the overflow of the address counter and combined with the inputs of the initial installation of the divider CPCD, divider CFCD, the address counter a persistent storage device and the address counter, and the output of the synchronization unit is connected to a clock input of the divider CFCD and a clock input of the divider CPCD, the control input of which is connected to the output of the counter, and the output of the divider CPCD connected to the input of the address counter ROM, the output of which is connected to the input address bus of the ROM, the ROM is connected through the switch to digital data bus of the first and second storage register and write and the address, thus the inputs of the read first and second register, HSI through a digital switch connected to the bus read, and the output data bus connected to the output of the second register, HI.

The proposed synthesizer CMSC in their internal structure contains a clock generator, a synchronization unit, a counter, a clock trigger, the divider CPCD, the divider CFCD, the address counter and a persistent storage device, which together represent a device that generates a digital amplitude and phase (hereinafter shaper). A similar device, from the point of view synchronous digital data exchange, is a device on the bus.mon. N 1608777. The output of the address counter 6 of the proposed device complies with the address output by the analogue, and the output of the ROM 4, the proposed device meets the output of the constant storage unit 3 in the device-analog.

The trend of the development of computing shows the need to use asynchronous transmission of digital data. This gives the opportunity to use a wide set of General-purpose processors, which are more and more widely applied not only in computing but also in automation, telemetry, peredachi digital data, with regard to the claimed frequency synthesizer consists of the following. During the sampling period of the digital multiband frequency synthesizer (CMSC) generates digital values of the phases and their corresponding numerical values of the amplitudes of the periodic signals. These results are recorded in one of the registers storing and recording information (hereinafter register HSI) and relate to the next interim report. In this interval of time to access the data makes no sense, because the digital data belonging to a given sampling period, are in a different register, HSI and were formed in the previous sampling period.

The drawing shows a block diagram of a digital multi-channel frequency synthesizer.

Description and explanation of the work CMSC will draw on the example of the formation of an ensemble of periodic sinusoidal signals. The size of the ensemble determines the number of channels. As a basic element in the structure CMSC is the divisor CPCD 2 (thunk code - frequency).

The author did not detail this element, considering such converters are fairly well developed and well known devices, such as devices on the bus.mon. N 1206959,aigaleo signal, the divider CPCD 2 forms the source of the harmonic signal. The frequency of the harmonic signal code is N, which is formed in the counter 7, and is

< / BR>
where faboutthe frequency of the clock generator 10;

M is a parameter of the divider CPCD 2, M is a simple integer;

N - output code of the counter 7;

K1- factor account of the counter 3.

In the expression (2) there is no binary value and therefore, the developer is free to choose the frequency step in the formation of an ensemble of frequencies, and in the proposed device does not have the error of frequency setting. The formation of phases and amplitudes for all channels is the initiating bus sample rate. With the arrival of the pulse at the first input of the block synchronization clock pulses from generator 10 receives the inputs of the divider CPCD and divider CFCD. The divider CFCD, with a coefficient of account K1and K1must be greater than or equal to the parameter M of the divider CPCD 2, generates time intervals equal to K1/fabout. Coinciding with these intervals in the address counter ROM 3, having a coefficient of account K1formed numeric value of the phases of all channels. Simultaneously with the formation of phases in the ROM 4 is formed amplitudinous generator 10;

M is a parameter of the divider CPCD 2, M is a simple integer;

N - output code of the counter 7;

K1- factor account of the counter 3;

t - the current time.

Given that

t = n/fabout< / BR>
where n is the number of pulses from generator 10, one obtains the expression

< / BR>
where

< / BR>
Thus, at the output of the ROM 4 is unfolding in time sinusoidal signal, described by formula (3) and supplied through a digital switch on the data bus register HSI 8 or register HSI 9. At time intervals equal to K1/faboutat the output of the divider CFCD 5 pulses of records that come through the digital switch 12 to the inputs of register entries, HI 8 or register HSI 9. Simultaneously, the pulses entries come to the address counter 6, which generates an address at which a write signal output from the ROM 4 in the case of HSI 8 or register HSI 9, and generates a signal of the end of the entry in the registers of HSI 8 and 9. When the first pulse K1from the output of the divider CFCD is the amplitude of the periodic signal generated in the ROM 4, through the switch 12 in the case of HSI. This value of the digital signal corresponds to the signal of the first channel and time of the next interim report.

Following a triggering signal on the bus discretization leads to a similar process of formation of phases and amplitudes. The difference lies in the change of size N in the expression (5). This value determines the state of the counter 7. With the advent of the signals on the bus sampling the value of the counter is incremented. This will lead to a different value of the rate of change in phase in accordance with the expression (2) and accordingly change the values of the amplitudes by the formula (5), which will be recorded in all channels.

The table explains the process of formation of amplitude values for each of the channels in the two dimensions of time. The rows show the amplitude values of the respective phases that are deployed in time during the sampling period, i.e presents the values of mutie in time, which is determined by the quantization of time (sampling period).

In the result, we obtain the following value of the digital signal generated by the proposed synthesizer on each channel

S*m= sin(mw)t,

where t = Tdk;

m is the channel number;

Td- sampling period;

k is the number of times the report.

Initiating signals on the bus discretization lead to changes in the status of the counter 7 and a clock trigger 11. The functional purpose of the counter 7 has been described above. The functional purpose of the trigger 11 is to control the digital switch 12, which together with the registers HI 8 and 9, provides an asynchronous way of reading the digital values of the periodic signal on all channels. Asynchronous a method of transmitting digital data, in relation to the claimed frequency synthesizer consists of the following. During the sampling period of the digital multiband frequency synthesizer (hereinafter CMSC) generates digital values of the phases and their corresponding numerical values of the amplitudes of the periodic signals. These results are recorded in one of the registers storing and recording information and relate to the next time is of iesa to the previous interim report, are in a different register, HSI and were formed in the previous sampling period.

When the process of forming the digital amplitudes, the record of these values occurs in one of the registers of HSI and these data are prepared for the next interim report. Reading values of amplitudes across all channels, prepared in the previous sampling interval, occurs in another case, HSI.

Thus, the clock trigger 11 each sampling period reverses the order of the registers HSI to read and write. This replacement process registers for user not visible". Read the user produces the same addresses that define the channel number.

Digital switch 12 operates in two modes. The mode of operation of the digital switch is determined by the state of the trigger 11. The trigger condition 1 corresponds to the mode 1 for the digital switch, the state trigger 0 = mode 0. With the advent of the next sampling pulse on the bus 13 the state of the trigger 11 is changed to the opposite.

Mode 0 digital switch complies with the following switches:

- bus input register of HSE 8 is connected to the output PSU;
input register read HSI 8 is blocked;

- bus address register HSI 9 is connected to the input address bus 14;

- bus input register of HSE 9 is blocked;

input register read HSI 9 connected to the bus reading 15;

input register entries, HSI 9 is blocked.

Mode 1 is structurally corresponds to the above mode 0. The difference lies in the fact that the register of HSE 8 and the register of HSE 9 are swapped. If mode 0 write signal generated in the ROM 4, is made in the register of HSE 8, and the read information is from the register of HSE 9, the mode 1 signal from the ROM 4 is recorded in the register of HSE 9, and the read information is from the register of HSE 8. The table presents the result of the write signal output from the ROM 4 in the registers of HSI 8 and 9. The output device is output bus 16, which is connected to the combined outputs of the registers of HSI.

The presence CMSC synchronization unit, counter, counter addresses a persistent storage device, a frequency divider with variable division factor of the frequency divider with a fixed division ratio, clock trigger allows you to extend the functionality CMSC and to obtain a device in which there is no m what distinguishes the proposed device from analog and gives the opportunity to use the synthesizer frequency for the spectral analysis of the processes of long duration (tens of hours) in many fields of science, and in particular in Geophysics, seismology, acoustics.

Under the extension functionality CMSC refers to the fact that asynchronous method of digital data provides an extended field of application of this device.

The above-described structure CMSC is flexible with respect to changes of the ensemble of periodic signals and/as from the point of view of changing waveforms. The size of the ensemble is determined by the setting of the address counter, and the form of the signals recorded in ROM and can be different.

In known to the applicant of patent information technical solutions are not found with signs, similar to the distinctive features of the proposed solutions, contributing to obtaining new above properties.

From the above it follows that the claimed digital multiband frequency synthesizer can be considered new, with significant differences, as it is characterized by a new set of features that allow us to achieve a positive effect.

Digital multiband frequency synthesizer containing a clock generator, an address counter, a persistent storage ustroistvo, the address input of the read which is connected to the address bus, and the output of the address counter connected to the input of the address recording digital switch, characterized in that the synthesizer introduced a clock trigger, the frequency divider with variable division factor (CPCD), the address counter a persistent storage device, a frequency divider with a fixed division factor (CFCD), the counter, the synchronization unit, the first input of which is combined with inputs of the counter and a clock trigger and connected to the bus sampling rate, the second input of the synchronization unit is connected to the output of the clock generator, and a third input connected to the output of the overflow of the address counter and combined with the inputs of the initial installation of the divider CPCD, divider CFCD, the address counter a persistent storage device and the address counter, and the output of the synchronization unit is connected to a clock input of the divider CFCD and a clock input of the divider CPCD, the control input of which is connected to the output of the counter, and the output of the divider CPCD connected to the input of the address counter ROM, the output of which is connected to the input address bus of the ROM, the ROM is connected through the switch to digital data bus of the first and second register storing and recording information inputs C the reading passages of the first and second register, HSI through a digital switch connected to the bus read and the output data bus connected to the output of the second register, HSE.

 

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