The generator of uniformly distributed random pulses

 

(57) Abstract:

The invention relates to computer technology and can be used in computational and modeling devices using probabilistic principles for the presentation and processing of information. The aim of the invention is to develop a generator of uniformly distributed random pulses, which allows you to generate pulses with a uniform law of their distribution at a given time interval. This objective is achieved in that the signals of clock pulses in the shaper instantaneous values of voltage 2 is memorization sampling voltage noise over time So Simultaneously starts CLAYS 6. At the moment of equality of these voltages at the output of the comparator 3 is formed by a random pulse, the duration of which lies on the time interval ]0, T[. Typed element PROHIBITION 4 and the delay line 7 on the leading edge of this pulse to form a short pulse with a uniform distribution on the corresponding time interval. 5 Il.

The invention relates to computer technology and can be used in computational and modeling devices using probabilistic principle is[1, c. 148-149, Fig. 6-10], which contains the generators of the random sequence and a periodic pulse, triggers, keys, counters and intermediate memory.

However, this generator allows you to create only aperiodic sequence of random numbers in one-third of the cycles of their work. For successful operation of the generator it is necessary to provide a definite correlation between the repetition frequency of clock pulses and the average repetition frequency of random impulses.

The closest in technical essence is a generator of uniformly distributed random numbers [2].

The generator comprises a generator pulses, the AND gate, the output of which is connected with its first input and the input of the SHIFT of the shift register, the outputs of the i-th (i is a(1, k-1); k is the number of bits of the shift register) and the k-th bits of which is connected with the first and second inputs of the modulo two, the output of which is connected to the information input of the shift register. The output of the noise source is connected to the information input of the memory block, the output of which is connected to the first input of the comparison circuit. The output of the comparison circuit is connected to the second input element. The output of the pulse generator is connected to the input Sapolsky comparison.

This generator allows changing randomly and widely the number of clock pulses received at the input of the shift register with feedback, to generate pseudo-random numbers with uniform distribution in the ring of M-sequence.

However, the generator prototype has drawbacks. It is not possible formation of random pulses with uniform distribution on the interval [O, T].

The aim of the invention is to develop a generator of uniformly distributed random pulses, which allows you to generate pulses with a uniform law of their distribution at a given time interval.

This objective is achieved in that in the known generator of uniformly distributed random pulses containing the latch instantaneous values of voltage, information whose input is connected to the output of the noise source and the output to the first input of the comparator, the oscillator ramp voltage, the output of which is connected to the second input of the comparator, the pulse generator, the output of which is connected to the input of the ramp generator voltage and control input latch instant snakeline delay, as a direct input connected to the output of the comparator. The output element of the BAN is the output of the generator of uniformly distributed random impulses.

In Fig. 1 and 2 show respectively a diagram of the inventive generator and timing of its operation; Fig. 3 is a diagram of the latch instantaneous values of voltage, and Fig. 4 and 5 are respectively a diagram and timing diagrams of the operation element of the BAN.

The generator of uniformly distributed random pulses (GRI), the scheme of which is shown in Fig. 1, consists of a noise source (ISH) 1, release instantaneous values of voltage (FMOH) 2, a comparator 3, item BAN 4, pulse generator (GI) 5, oscillator ramp voltage (CLAY) 6 and a delay line (LPA) 7. Information input FMOH 2 is connected to output 1 ISH. Output FMOH 2 connected to the first input of the comparator 3. The output of CLAYS 6 is connected to the second input of the comparator 3. Exit GI 5 simultaneously connected to the input of CLAYS 6 and control input FMOH 2. An inverse input element PROHIBITION 4 through 7 LPA is connected to the output of the comparator 3. Direct entry element PROHIBITION is directly connected to the output of the comparator 3. The output element PROHIBITION 4 is the output GRCE.

The noise source 1 p [1, c. 26, Fig. 1.8].

Shaper instantaneous values of voltage designed for storing within a specified period of time instantaneous values of voltage coming from the output 1 ISH. The scheme of such FMOH 2 is known and described, for example, in [1, C. 46, Fig. 2.6]. In the claimed GRSI taking into account characteristics of the linkages with other elements of the scheme FMOH 2 takes the form shown in Fig. 3, and includes a first resistor 2.1, the first output of which is an information input FMOH 2, and the second is connected simultaneously to the first output of the second resistor 2.2 and direct input element 2.4 BAN on inverse input of which is connected the control input FMOH 2. The output element PROHIBITION 2.4 simultaneously connected to the first output capacitor 2.3 and to the input of the DC amplifier (UPT) 2.5. Output UPT 2.5 is connected to the second pins of the second resistor 2.2 and condenser 2.3, and with the release of the FMOH 2.

Item BAN 4 is designed to generate at its output a logical unit only with the simultaneous presence at its inverted input of a logical zero, and the direct input of logic unit. Functional diagram of this element is shown in Fig. 4, in Fig. 5 shows timing diagrams of the operation.

The pulse generator 5 is designed to generate a sequence of short clock pulses. A diagram of such a GUY known and described in [4; S. 213; Fig.7.6].

The oscillator ramp voltage 6 is designed to generate a voltage type saw. The scheme of such CLAYS are known and described in [5; c. 80-84; Fig. 1.64].

LPA 7 this generator is designed to delay a random pulse by an amount two to three times the duration of the average time delay of signal propagation tcf. ZV.pin the element PROHIBITION 4. When implementing element PROHIBITION on the model elements And NOT the first will be the average delay time tcf. ZV.withabout 40-50 NS [6, S. 431-435]. Schemes of providing a time delay is known. In particular, the delay line can be implemented on the four elements [3, S. 54, Fig. 2.4].

Scheme and principle of operation of the comparator 3 is known and is described in [4; c. 213; Fig. 7.6].

The claimed GRSI works as follows. When the control input FMOH 2 pulse output GI 5 (Fig. 2) in the first for the and output ISH 1 (Fig. 2, a). At the same time starts CLAYS 6. At the moment of equality of the voltages at the outputs of CLAY 6 FMOH and 2 (Fig. 2, b) triggers the comparator 3. As a result, the output of the comparator 3 is formed pulse (Fig. 2, e) with a voltage level equal to a logical unit. The duration of the resulting pulse is evenly distributed in the time interval ]O, T[. This is because the sampling instantaneous values of the voltages of the realization of a random process ISH 1 are uniformly distributed in some interval of voltage noise. The received pulse with a random duration is supplied to the direct input element PROHIBITION 4 and to the input of the 7. In LPA 7 pulse is delayed by the value of tcf. ZV.p. Then from out of the 7 pulse is supplied to an inverse input element PROHIBITION 4. It is known that the element PROHIBITION generates at its output a logical unit only with the simultaneous presence at its inverted input of a logical zero (Fig. 2, f), and the direct input of logic unit (Fig. 2, e). Thus, at the output of the element PROHIBITION 4 pulses of duration tcf. ZV.p(Fig. 2, n), the position of which in the interval ]O, T[ equiprobably.

In comparison with the known generator [2] claimed allows you to create Sluch the M Ii. Generating random signals. - M.: Energy, 1971, s.

2. Auth. St. N 1206779, CL G 06 F 7/58, 1986.

3. Potemkin, I. C. Functional units of digital automation. - M.: Energoatomizdat, 1988. - 300 S.: ill. [9].

4. Chips and their applications: a reference guide/ C. A. Batashev and others - M. : Radio and communication, 1983 - 272 C., Il. - (Mass reliability; vol. 1070).

5. Svechnikov, M. and other Pulse circuits on semiconductors and ferrites. - M.: Voenizdat, 1972.

6. Lavrinenko C. Y. Handbook of semiconductor devices. - K.: Engineering, 1980.

The generator of uniformly distributed random pulses containing the latch instantaneous values of voltage, information whose input is connected to the output of the noise source and the output to the first input of the comparator, the oscillator ramp voltage, the output of which is connected to the second input of the comparator, the pulse generator, the output of which is connected to the input of the ramp generator voltage and control input latch instantaneous values of voltage, characterized in that it additionally introduced an element of PROHIBITION, an inverse input through the delay line, and a direct input connected to the output of comparat.

 

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FIELD: cryptography.

SUBSTANCE: method includes generating random numbers with use of displacement register with check connection, elementary digit of which is a q-based symbol (q=2l, l - binary symbol length) at length of q-based digits register, in check connection networks nonlinear two-parameter operations on q-based symbols F (ub, ud) are used, on basis of random replacement tables, for generating next random number values z1=F(ui, uj), z2=F(ut, um), zg=F(z1, z2) are calculated, where ui, uj, ut, um - values of filling of respective register digits, value of result in check connection networks zg is recorded to g digit of displacement register and is a next result of random numbers generation, after which displacement of register contents for one q-based digit is performed.

EFFECT: higher speed and efficiency.

3 cl

FIELD: computer science.

SUBSTANCE: device has random numbers source, N-digit selector-multiplexer, RAM, ranges control block, generations number control block, J-input OR element, AND elements block. Because series of given values of data set is broken in ranges and frequency of their appearance is set within certain limits, random series is generated with distribution law, presented in form of ranges.

EFFECT: broader functional capabilities.

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