Drive storage device

 

(57) Abstract:

The drive is a storage device refers to the contactless storage non-volatile memory cells and can be used in microelectronics to create a ROM, CSU, program memory and increased information capacity. The technical result is achieved by using switching memory cells of the memory, which allows twice to reduce the number of tires metallization. This is possible because each tire metallization having a zigzag shape, bypasses the two diffusion with sequence numbers i and i-3 or i+3 depending on the evenness or oddness of the number i. This provides the individual selection of each memory cell during programming and reading. Diffusion bit bus is divided into isolated from other segments, and the gaps between segments of diffusion tires are between the contacts tires metallization to the segments of two adjacent diffusion tires. Technical solution allows to increase access to care sizes and resumeedge layers during formation of the contact Windows and a metallization layer and to increase the density of information in the drive. 2 C.p. f-crystals, 3 ill.

One of the most important parameters drives the semiconductor memory with non-volatile storage of information is information capacity. The most famous platekompaniet in the integrated design, the so-called contactless drives [1, 2] in which the contacts between the diffusion bit tires and shunt aluminum tires perform at a relatively great distance from each other, usually every 16 memory elements.

As a prototype of the selected drive mass storage device [3] is performed on the semiconductor substrate in a matrix memory field-effect transistors, the drain-ishikawae electrodes which are connected to the corresponding bit tyres, designed along the columns of the matrix, and the gates are connected to the address bus, designed along the lines of the matrix. As integrated circuits on a silicon substrate contacts between diffusion and shunt aluminum tires generated periodically between groups polysilicon address buses. In the prototype, the contacts are staggered, i.e., for each diffusion bus through two groups of address buses and two adjacent diffusion tire over two groups which are parallel to one another, and the amount of diffusion of the tire is equal to the number of metal tires. As storage elements in the memory is used, for example. MOS transistors with a floating gate, a record of information which channel is the injection of hot electrons, and the Erasure of ultraviolet (UV) radiation.

In memory of this design, in particular the prototype, critical size, further restricting the minimization of the square drive on an axis parallel to the columns of a matrix, is a step on tires metallization (mines width plus the gap). The difficulty of etching aluminum foil leads to the fact that the minimum step of the tire metallization higher than the same parameter for films of other materials used in MOS technology, about one and a half times, and this prevents further increases the density of the layout of the drive.

The present invention aims at eliminating this disadvantage and increase the density of memory in the integrated design.

Obtaining the desired result is achieved by the fact that in fragments of memory bit bus pairs connected together in such a way that arbitrary bit bus with a serial number i put the e j=3,

As integrated circuits on a silicon substrate column bit bus made diffusion, address lowercase bus from polysilicon, and pairing diffusion tyres produced aluminum tires zigzag form with contact Windows, made to diffuse tires between groups address buses.

The optimal value of the number j from the point of view of the composition is 3, which further will be used.

Bit bus memory as a whole can be formed in a sequence isolated from other segments of the diffusion of tyres placed on the drive shaft order, each of which is crossed by two groups address buses and have between them a contact to the aluminum bus, and the gaps between segments of diffusion tires are between the contacts aluminum tires to the two segments of the diffusion of tires belonging to two adjacent columns of the matrix, with aluminum bus connect segments of the diffusion of the tire along the columns of the matrix so that any line related to the i-th column of the matrix, connected to the two nearest lines, related to the column with sequence number i-3 or i+3 depending on orestia is due to the fact, in the proposed design step metallization almost twice freer similar parameter for the diffusion bit buses. This will increase the density of information in the drive. In the proposed design step metallization is not a parameter that limits the density of information. As will be shown below, the proposed design allows individual selection of each memory element when reading and writing information.

When bit bus drive generally formed as a sequence isolated from each other by gaps segments diffusion tires, the mutual position of the contact Windows and the gaps between the ends of the segments diffusion tire eliminates severe restrictions on the size and magnitude of resumeware, contact Windows. In this design, the size of the memory elements in the rows of the matrix is determined by the channel length of transistors and limitations on the width of the diffusion bit buses. Increase the information density of the drive due to the use of the proposed design is 30-40%

Unknown design matrix storage integrated circuits permanent memory with single metal is meets the opportunity to make an individual selection of each memory element when reading and writing information. Thus, the proposed design has a significant difference.

In Fig. 1 presents a fragment of the topological construction of the proposed drive in the integrated design, where 1 address polysilicon bus 2 bus metallization, 3 diffusion bit bus, 4 contact window; Fig. 2 the case when the fragments of the diffusion bit buses made in the form of segments, arranged in a checkerboard pattern of Fig.3 circuit diagram of a fragment of a memory storage device for a particular case, when the memory cell is made in the form of MOS transistors with a floating gate overlying a portion of the channel by stock area, where C1-C9 - cell memory, B1-B5 bus metallization, A1 and A2 address bus.

Let's consider a fragment of the drive RPSU on the basis of memory cells with a floating gate (Fig. 3), while keeping in mind that it is similar for both options, is shown in Fig. 1 and 2.

If bit bus B3 and the bolt bus A1 to apply the programming voltage, respectively, Upand Uppfor example, Up=8B, Upp=12B, and all other bus reset will occur simultaneous recording information in the memory cell C4 and C7. To prevent Zap osenia 0<U<U i<U<Uwhere Usothe minimum voltage at the source, for which there is no entry in the memory cell with the voltage on the drain is equal to UpUdo- maximum voltage at the drain, in which there is no entry in the memory cell with zero voltage at the source. As a rule, this requirement corresponds to the value Ui= Up/2. Similarly, to prevent the entry in cell C7 voltage Up/2 must submit to the bus B4.

When reading data from the bit buses, for example, B3 is zero, and all other bit bus serves the voltage Urr, for example, 2V. On the selected gate bus A1 serves voltage Uccfor example, 5V. The currents read through the memory cell C4, C5, C7 and C8 are measured respectively on the buses B1, B2, B4 and B5. To eliminate the influence of the resistance of the diffusion bit buses, which is in the reading mode can lead to the flow of parasitic current through bus metallization corresponding to the memory cells with a high value of the threshold voltage, the voltage Urshould be large enough, for example, 2V or more.

Bibliographic data

1. U.S. patent N 4597060, CL G 11 C 11/40, 365/185, 365/189, 1989.

2. Esg51, 365/189. 1988.

1. The drive is a storage device, executed on a semiconductor substrate in a matrix memory field-effect transistors, the drain-ishikawae electrodes which are connected to the corresponding bit tyres, designed along the columns of the matrix, and the gates are connected to the address bus, designed along the lines of the matrix, characterized in that bit bus pairs connected together in such a way that arbitrary bit with sequence number i is combined with the bit-line having a sequence number i j or i + j depending on the evenness or oddness of the number i, where j 3.

2. The device under item 1, characterized in that the integrated design on a silicon substrate column bit bus made diffusion, address lowercase bus from polysilicon, and pairing diffusion tyres produced aluminum tires zigzag form with contact Windows, made to diffuse tires between groups address buses.

4. The device according to PP.1 and 2, characterized in that bit bus drive generally formed as a sequence isolated from other segments of the diffusion tires, have the contact to the aluminum bus, the gaps between segments of diffusion tires are between the contacts aluminum tires to the two segments of the diffusion of tires belonging to two adjacent columns of the matrix, with aluminum bus connect segments of the diffusion of the tire along the columns of the matrix so that any line related to the i-th column of the matrix, connected to the two nearest lines related to the column with sequence number i 3 or i + 3 depending on the evenness or oddness of the number i.

 

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