The display device of the moving image and the external storage device used for it

 

(57) Abstract:

The invention relates to devices for display of the moving image and an external storage device for use therein, and more particularly to a video game devices. The aim of the invention is to provide a device of the display moving image is able to visualize the maximum number of objects without reducing the number of objects rendered in a horizontal direction. The display device of the moving image contains the main unit and the external memory, removable mounted on the main unit. The main unit of the display moving image is ZU video data to store the image data of the characters that make up the object. The memory program data of the external memory has a data object on the object subject visualization on the monitor raster type, i.e., data of the color palette data horizontal position, the data size of the object and the data indicate the size or the like, which are all pre-loaded into it. Object data about the object that you want to visualize it. Object data about the object to be rendered in the next vertical scan period, CityVision decides, is or is not an object in position falling within the range, based on data from the vertical position, data size and data indicate size, and also decides, or is no object in position falling within the range, based on data from the vertical position, data size and data indicate size. 2 S. and 9 C.p. f-crystals, 3 tab., 25 Il.

The invention concerns a device to display moving images and an external storage device (MD), suitable for use therein, and more specifically relates to devices of the display moving images such as video game device, a personal computer for animation (giving mobility) visualization of large object on the monitor raster type by combining one or more characters, each containing a set of points in the horizontal and vertical directions, respectively, and the external memory, suitable for use in a display device of the moving image.

A device lively display or moving image, such as "Family computer" (name used in trade), "entertainment System Nintendo" (name), etc. which occurs on 7 July 1984 Description contains a first memory for storing therein data about the object (symbol) corresponding to one screen, a second memory for storing therein data about the object rendered during the next period of the horizontal scanning, and a variety of shift registers, each of which is used to store the data (image data) of the object. The described device lively display outputs the horizontal and vertical positions, object codes and data characteristics for each object. Additionally, this device compares the vertical position of the display object and the line number of the horizontal scanning on the monitor with the purpose of adjudication of the so-called "definition of exposure range, determining whether or not the object can be visualized during the next period of the horizontal scan. The device will then display the moving image is excited to decide on a subject that hit the range for each object so that the image data of the object falling on the solution in the range, to transfer from the first memory to the second memory, thereby transmitting image data to the corresponding shear regrate graphic data object, at the decision about it in position falling within the range, during the period of the horizontal locking is transferred to the shift register. Therefore, the processing speed is considerably higher can be realized. However, when you want to visualize large-object by means of this device the display of the moving image, the load coming on the CPU (microprocessor), increases and OAM (ZU characteristics of the object), you need a high capacity. Specifically, it is the form of data of 4 bytes in the prior art. Therefore, it is necessary to rewrite and restart large-object containing the group II symbols, data of 4 bytes x II in each of the first and second memory to render this object. Thus, when a large object is rendered, the load imposed on the CPU (microprocessor) increases, thereby affecting the rest of the arithmetic processing, and so on, So the size of each object and the number of objects is limited, when you want to render the object in the range in which the load increases, mentioned above, has no effect on such arithmetic processing. Additional data about the object of all have to boot into OAM, thus causing the need to increase the storage capacity of TAM.

In contrast to the above mentioned prototype of the prior art proposed by the imaging device, is able to visualize large object, which device is described, for example, in Japanese patent application laid N 62-24296 submitted and published on 2 February 1987, According to the description of the data sizes of the horizontal and vertical display loaded into memory characteristics (corresponding OAM mentioned above). Additionally, data on the vertical size of the display are used to determine the exposure range, and the horizontal size of the display is used as the read address in relation to RAM characters. Thus, the description can create an advantage in that the size of the object can be changed for each object.

In the imaging device described in Japanese patent application laid N 62-24296, data on the size of the horizontal display is not used, however, for decisions about getting into range, and therefore the data about all the objects in the solution in contact with the range based on the size of the part of the application N 59-118184. Especially, even when the detected object lies beyond both edges of the display screen is determined that the object in position falling within the range, despite the fact that the object is normally not rendered on the screen, if the decision to hit the range made only on the basis of data on the vertical size of the display. In other words, even an object lying outside the range in which it can be visualized in a horizontal direction on the screen is processed in relation to the conversion data of the object in the image data. On the other hand, the time required to perform such a conversion process is kept constant, thereby causing a problem that the number of objects that each can be visualized by a single horizontal line, is significantly reduced. In order to solve such a problem. CPU (microprocessor) makes the necessary process in order to avoid a determination in relation to the subject, beyond the range of the display object that he is in the position of getting in range. Thus, the load or difficulty imposed on the CPU is not fully eliminated.

Referring to the above-mentioned problem, the main objective of the present invention consists of a poet is isawanya in this device.

Another objective of the present invention is to create a device display of the moving image, is able to visualize the maximum number of objects without reducing the number of objects rendered in a horizontal direction.

Another objective of the present invention is to create a device display of the moving image, is able to significantly reduce any load imposed on the CPU (microprocessor), when rendered large-sized object.

Another objective of the present invention is to create a device display of the moving image, is able to visualize large object, using the memory characteristics of the moving image having a small memory capacity.

Another objective of the present invention to provide the display device of the rolling of the invention, is able to visualize every one of objects of different sizes by using a memory having a small memory capacity.

Another objective of the present invention is to create a device display of the moving image, is able to increase the number of rendered objects using a memory having a small memory capacity.

Another objective of the present invention is to create a device of the display moving image type in which, when some or all of the objects lie in the range of the screen, the data processing section within the range blocks in order to reliably remove inefficient processing of data, thereby making possible a significant reduction in the number of objects.

Another objective of the present invention is to create an external memory used in each of the above devices of the display of the moving image.

According to one distinctive feature of the first invention provides a display device of the moving image type, in which the large object can be visualized on the monitor raster type by combining one or more characters, each containing a set of points in the horizontal and vertical directions, respectively, and the display device of the moving image includes:

first memory means for pre-loading image data of characters that make up the object in a corresponding address region DL is nachusa object, used to indicate at least one object is rendered on the monitor during the next vertical scanning period on the monitor;

the tool generate the positionally data to generate positional data used to represent the horizontal and vertical positions of the identified object on the monitor on which the specified object should be rendered;

a means of generating data size to generate a data size that is used to select one of the dimensions of the object;

second memory means for temporary storage of data refer to the object and positional data in it;

the means for determining the exposure range for a decision as to whether or not the object to be rendered on the monitor during the next period of the horizontal scan, based on the vertical position filed from the second memory means, and data size by means of generating data about sizing, and for a decision as to whether or not the object to be rendered on the monitor during the next period of the horizontal scan, based on the horizontal position, filed n is about choosing the size, and

the means of education read address for the formation of a read address for the first memory means in respect of an object falling under decision about the object that he is falling into the range, using the definition of exposure range, based on the data refer to the object, positional data and data about sizing, thereby sending an educated thus the read address to the first memory means.

On the occasion when the first invention is applied to an external memory, the external memory is formed with means for generating data about the designation of the object, means for generating positional data and a means of generating data about sizing.

For example, one symbol is represented in the form of 8 pixels (picture elements) in the horizontal direction x 0 pixels (picture elements) in the vertical direction. One object may be formed by any group or combination of one or more characters. Graphic data (point data) of one or more characters, each containing, for example, 128 objects are loaded into the first memory means such as memory video data, etc. for each object in advance. Thus, the desired object can be the ptx2">

The microprocessor (CPU) is excited to host data object in the second memory means, such as OAM (ZU characteristics of the object), and so on, while the initial condition is set at this time or during the period of the vertical lock on the monitor raster type. Such data about the object include, for example, the data object type (data name), information about the vertical position, the horizontal position and data about the choice of the size of the object, as well as data on the color palette, the data on the vertical and horizontal transfer and data display priority, etc.

These determine the size of the object include data indicate an object's size and data size, for example. The data indicate size are used to denote the two dimensions of the object, for example, "8x8", "16x16", "32x32 and 64x64". The data size will be, for example, either "0" or "I". When "0" is set as the data size, one marked as such in two sizes selected. When "I" is set as the data size, select a different size of its. Thus, the size of the object can be determined by using the data size determination.

Cf the data of the vertical position of the object, for example, and then make a decision in relation to the definition, or is no corresponding object in position falling within the range, i.e., it must be visualized by following the horizontal line based on the result of comparison and the size of the object mentioned above. At the same time, the means for determining the exposure range makes a decision of whether or not the corresponding object in position falling within the range of, based on, for example, the result obtained by performing an arithmetic operation on the absolute value of the horizontal position of the object and the size of the object.

Then, image data of an object falling under the definition that is set to hit the range on the horizontal and vertical directions by using the definition of exposure range read from the first memory means. More specifically, the means of education read address forms a read address based on the data refer to the object, the positional data and the size of the object so as to read image data of an object falling under the definition of exposure range from the first memory means.

According to the PE the terms falling within the range in vertical and horizontal directions. Therefore, the object being actually visualize, subject only to the determination of the exposure range, compared with the way a decision is or is not an object in position falling within the range only in the vertical direction as described in each of Japanese patent laid applications NN 59-118184 and 62-24296, thereby making it possible to prevent a significant reduction in the number of objects. An object falling under the definition that is set to hit the range, always visualized, and therefore a great time processing CPU or microprocessor can be eliminated, thereby enabling to improve the efficiency of the functioning of the microprocessor.

According to one distinctive feature of the second invention provides the display device of the moving image type in which the object of large size can be visualized on the monitor raster type by combining one or more characters, each containing a set of points in the horizontal and vertical directions, respectively, which device display moving image) includes:

first memory means for pre-loading graphics generirovannykh data refer to the object to generate the data refer to the object, used to indicate at least one rendered object on the monitor during the next vertical scanning period on the monitor;

a means of generating positional data to generate positional data used to represent the positions of the identified object on the monitor on which the specified object should be rendered;

a means of generating data size select the size of the object for each object;

a means of generating data mode legend for generating mode data destination used to determine the mode of designation of size for each screen;

second memory means for temporary storage of data refer to the object and positional data in it;

the means for determining the exposure range for a decision as to whether or not the object to be rendered on the monitor during the next period of the horizontal scan, based on a combination of positional data read from the second memory means, data size, subjects of the means of generating data about sizing, and data symbols sent on the output of the means generowania for the first memory means, in respect of the object, subject to a decision about the object as being in the position of getting in range, using the definition of exposure range, in order to apply the so formed the read address to the first memory means.

When the second invention is applied to an external memory, the external memory is formed with means for generating data refer to the object, means for generating positional data, means for generating data about sizing and means for generating mode data symbols.

According to the second invention, the means for determining the exposure range decides, or is no corresponding object in position falling within the range, i.e., must be visualized using the following horizontal line based on the size of the object defined by the data indicate the size and data size, and positional data of the object on the monitor. Additionally, means the formation of the read address forming the read address on the basis of, for example, data refer to the object, positional data, the data indicate the size and data size in such a way as to read image data of an object falling under the resh is size value is used to refer to many kinds of sizes, and the data size are used to select and determine the size of each object. Therefore, it is possible to significantly reduce the amount of data used to determine an object's size, compared with the conventional example. Accordingly, not only the memory capacity of TAM can be significantly reduced, but also the memory capacity of the memory programs can also be reduced. Suppose now that 128 objects can be visualized on the same screen as the maximum, and provides six types of rendered sizes, for example. In this case, the 3-bit data indicate size and 1-bit data size can be set for each screen and each object, respectively. Thus, the data on 131 bits (=1281+3) can be used to alternately or adjustable to determine the size of objects. The number of such data may be about 1/5 (=131/768) compared with the technical solution described in Japanese patent application laid N 62-24296.

According to one distinctive feature of the third invention provides the display device of the moving image type in which the object of large size can be visualized on the monitor raster type by obyedinenie respectively, which device display moving image) includes;

first memory means for pre-loading the graphics data about the characters that make up the object in the corresponding address area for each object;

a means of generating data refer to the object for generating the data object type that is used to denote at least one object that is being rendered on the monitor during the next vertical scanning period on the monitor;

a means of generating positional data to generate positional data used to represent the positions of the identified object on the monitor on which the specified object should be rendered;

a means of generating data sizing for generating data defining the size used for a decision about the size object

second memory means for temporary storage of data refer to the object and positional data in it;

the means for determining the exposure range for a decision as to whether or not the object to be visualized on the monitor during the next period of the horizontal scanning, on the basis of positionning sizing;

means for reading the image data from the first memory means in respect of an object falling under decision about the object as being in the position of getting in range, using the definition of exposure range;

the means for determining the hit for the band to judgment, is or is not part of the object falling under the definition of an object, as in the situation of falling into the range by using the definition of exposure range, with the range of the screen on the monitor, and

the means of preventing read to prevent reading from the first memory means image data of the part object that is subject to a decision about the object behind the screen, by using the definition of falling into the range.

According to the third invention, image data of an object falling under decision about him, as being in the position of falling into the range in the horizontal and vertical directions by using the definition of exposure range read from the first memory means. On the other hand, when the object is represented by the size of the object, based on the definition data object size, a measure of vihuelas edge and/or the right edge in the horizontal direction on the screen, on the basis of the positional data in the horizontal direction and given the size of the object. If it is determined that the part of the object lies beyond the left edge, then the means of preventing reading is excited to preset addresses for education began when reading image data of an object in the address of the image data to actually rendered characters, thereby preventing the reading of the ineffective image data. If it is determined that the part of the object lies beyond the right edge, then the output signal. In response to this signal, the means of preventing then prevent the reading of image data from the first memory means. Specifically, the data indicate the following object is blocked in the register used to store the data refer to the object, thereby starting the process towards the next object.

Also according to the third invention, when part of the object lies beyond the screen, the read image data with respect to such portion from the first memory means is prohibited. Therefore, the process is inefficient data with respect to part of the object, which is beyond both edges of the monitor screen, as mentioned above, is not executed. The PNA processor, used for processing moving images, thereby creating the possibility of more rapid processing speed as a whole.

The above and other objectives, features and advantages of the present invention will become apparent from the following detailed description and appended claims, taken in conjunction with the accompanying drawings in which is shown the preferred embodiment of the present invention as an illustrative example.

In Fig. 1 depicts a block diagram showing one embodiment of the present invention; Fig. 2 is a block diagram showing the video processor used in the implementation shown in Fig. 1; Fig. 3 is a block diagram showing the scheme of generating the synchronization signal, and Fig. 4 and 5 are graphs synchronization for descriptions of the corresponding clock signals in the horizontal direction of Fig. 6 schedule synchronization for descriptions of the corresponding signals in the vertical direction of Fig. 7, 8 and 9 are block diagrams, each showing a scheme of generating data recovery image shown in Fig. 2; Fig. 10 is a diagram for describing one example of a data object; Fig. 11 block diagram, shows the OAM detail; in Fig. 13 is a block diagram showing the scheme of the address vector RAM and vector RAM in detail; Fig. 14 is a block diagram showing in detail a control circuit register, the register of the H-position register V-position, register sign register name, the arithmetic circuit H-position and an arithmetic circuit V-position; Fig. 15 is a diagram for describing the horizontal (H) and vertical (V) position, pointing to the object on the monitor screen of Fig. 16 is a block diagram showing in detail the case size, case alternation, the decoder size and the detection circuit falling within the range of Fig. 17 and 18 are diagrams, each showing one example of the format ZU video data in the memory device of Fig. 19 is a block diagram showing the control circuit of the counter size in detail; Fig. 20 is a block diagram showing the control circuit of the adder addresses in detail; Fig. 21 (a-d) are diagrams, each showing the state of the H-jump and condition of V-jump, and Fig. 22 is a block diagram showing in detail the adder address, the addressing scheme/video ZU and ZU video data; Fig. 23 is a block diagram showing the circuit H inversion scheme and extracting color data in detail; Fig. 24 is a block diagram showing in detail the buffer RAM of Fig. 25 is a block diagram showing the addressing scheme bufernogo traccia.

Referring to Fig. 1, the microprocessor 10 controls the entire operation/functioning of the device display moving images such as video processor 12, and so on, in accordance with the data of the program sent from the memory 14 program data, which is included as an example in the loaded and unloaded cassette memory. As the microprocessor 10 uses a 16-bit microprocessor, such as IC "RF5A22", produced by RICOH TO.LTD. The video processor 12 reads the image data from the memory 16 and the video data in response to a command or instruction from the microprocessor 10, and then sends the read data to the television interface 18. ZU 16 video contains SRAM (Static memory random sampling), for example, 64 kilobytes, i.e., includes the storage area 16A of the background image and the storage area data symbols 16b. In other words, the storage area 16a of the background image and the storage area 16b data symbols formed from one SRAM. The reason for this construction is that the operating speed is fast, and the capacity of each storage area can be set arbitrarily by a symbol (object) and background image. Advanced audio circuit 20 generates data okazyvajus the om 10, for submission to the television interface 18. Television interface 18 converts the image data received from the video processor 12, the signal is RGB (red-green-blue red, green, blue approx. periods.) and then sends it to the video circuitry of the monitor RGB 22. Advanced television interface 18 converts the audio data generated by the audio circuit 20, the audio signal to feed the sound scheme in the RGB monitor 22. For example, integrated circuit "CXD 12220", manufactured by SONY CORP. possible as a sound scheme 20. Thus, an object such as a video game, and the background image, which changes in accordance with progress of the programs pre-installed in the memory 14 of the data about the programs, is visualized on the screen of the monitor RGB 22.

A variant of the implementation shown in Fig. 1, is the case where the television interface 18 converts the image data into an RGB signal. However, the present embodiment may alternatively use the TV interface, which converts the graphics data into TV video. In this case, as the monitor can be used home TV, which is widely available.

In Fig. 2 presents the block diagram, pokazyvaet 24 CPU with the latch (latch) data for capturing data from the microprocessor 10 in it, and the address decoder or the like. The interface 24, the CPU includes an interface 24A CPU for processing the background image and the interface 24b CPU for processing recovery (object). The interface 24A CPU is excited in such a way as to make possible the implementation of the data on the background image between the microprocessor 10 and the video processor 12. On the other hand, the interface 24b CPU is excited to generate data relative to the object between the microprocessor 10 and the video processor 12.

Then, the data generation scheme background image 26 reads the sample data (character code) representing the background image from the zone 16A storing a background image memory 16 video data in response to program data submitted to the exit of the microprocessor 10 through the interface 14a of the CPU. After that, the circuit 26 to generate the data about the background image reads image data indicating the background image from the zone 16b storage of the character memory 16 video data based on the sample data read thereby, and then sends read thus image data on the schema 28 sinasadya the present invention, will be described in more detail below. However, the circuit 30 generating data recovery image reads image data indicating the object from the zone 16b storing character data memory 16 and the video data on the basis of the program data generated by the microprocessor 10, and sends the read data to the synthesizer 28.

As will be described below, scheme 28 synthesizer determines or constrains the level of priority in relation to whether either the object or the background image to be specified when the object and the background image overlap each other. Therefore, if the object is treated as the highest priority, then it is rendered on the screen. However, the background image, which is superimposed on the object is not rendered on it. If a background image has received the highest priority, then it is rendered on the screen, but the object that is superimposed on the background image is not rendered on it. Thus, image data of the synthesized circuit 28 synthesizer, served on the circuit 32 to generate the image signal. Circuit 32 generating the image signal has a color encoder for education RGB signal in accordance with the color code point (picture element is written above.

Then, the circuit 34 generate a synchronization signal takes the primary synchronization signal 21,47727 MHz, shown in Fig. 4 and 5, the electrical processing by using, for example, counter, decoder, logic, etc. to thereby generate a number of clock signals shown in Fig. 3 and Fig. 4 and 5. After that, the circuit 34 generate clock signal is used to supply these signals to the interface 24 of the CPU circuit 26 generating data of the background image, the circuit 28 of the synthesizer circuit 30 generating data recovery image, the circuit 32 generating the image signal, etc.

Show more specifically: when the main clock pulse frequency divided by 1/2, the resulting clock signal either 10M or /10M ("/" is just the opposite 10M in the present description). When this signal is further frequency-divided by 1/2, we obtain the synchronization signal or 5M or /5M.

The period necessary to render 1 pixel (picture element) on the screen RGB monitor 22 (see Fig.1), corresponds to one complete cycle of the timing signal 5M. Thus, the time 0-341" as the reference value clock 5M, is a horizontal lane is there for one period of the display or render the horizontal line, then as time "269-341" as reading its value, equivalent to the period of the horizontal locking. The vertical signal V (see Fig. 3) is formed for each horizontal period, i.e., each time the reference value clock 5M is "0-341", and then kept in a vertical position during scanning, i.e. the line number. If one field at a time alternating scan is 262 horizontal lines, as shown in Fig. 6, then the resulting field of the synchronization signal during the interval in which the reference value of the vertical signal V is "0-262". The period in which field signal has a high level, corresponding to one vertical period, and 0-239" as the reference signal value V is equivalent to the period of the vertical imaging. Additionally, "240-262" as the reference signal value V corresponds to the period of the vertical locking.

As shown in Fig. 6, the synchronization signal VBH is applied to the output during the interval in which the reference value of the vertical signal is "240", and shows the beginning of the period of the vertical locking. The synchronization signal VB becomes high level during the period of the vertical locking, and synchronization signal /VB becomes high in level is the result of dividing the frequency of the above-mentioned signal 5M 1/2, while the synchronization signal /HCO is obtained by simply inverting the signal HCO. Signal /HCI obtained by dividing the frequency of the signal HCO 1/2. As shown in Fig. 4 and 5, the synchronization signal IN is a signal which becomes high level, i.e., indicates the status of the object processed by the detection circuit falling within the range during the period of the horizontal visualization, i.e., during the interval in which the reference signal value 5M is "0-255". Additionally, the synchronization signal /IN is a simple inverting clock IN. Sync /HI is output for each horizontal period during the interval in which the reference signal value 5M is "0". As shown in Fig. 5, the synchronization signal HBH applied to the output during the reference signal magnitude 5M "269-270", and shows the beginning of the period of the horizontal locking. Additionally, the synchronization signal /HBH is simply inverted signal HBH. Thus, the synchronization signal /HBH becomes high level during the interval in which the reference signal value 5M is "272-268" (either a typo, or counting down approx. periods.). On the occasion, the synchronization signal /HB becomes low level during the horizontal superannuation reading the signal 5M is "341-268", while the OAE signal is output as a high signal during the interval in which the reference signal value 5M is "0-271", as shown in Fig. 4 and 5. As shown in Fig. 4 and 5, the synchronization signal LBR is output as a high signal during the interval in which the reference signal value 5M is "17-272", while the synchronization signal LBW is output as a high signal during the interval in which the reference signal value 5M is "276-3". Further, the synchronization signal /CRES is formed as a low-level signal during the interval in which the reference signal value 5M is "3-17", as shown in Fig. 4 and 5.

As shown in Fig. 7, the interface 24b CPU includes an 8-bit register 36 address OAM is used to receive data from the data bus of the microprocessor 10. The register 36 address OAM takes the address from the microprocessor 10, when data is written to OAM (ZU characteristics of the object), is included in the circuit 30 generating data recovery image in order to set the starting address for the OAM 38. The OAM 38 has a memory capacity of 34 bits x 128, i.e., h bits, for example, and capable of storing the corresponding data objects in relation to 128 objects. As shown in Fig. 10, these results refer to the object, (data name), the 8-bit data vertical position, 9-bit data horizontal position and 1-bit data size of the object, as well as 3-bit data of a color palette, 1-bit data of the horizontal and vertical jump, and 2-bit data representation of the priority or the like.

As is well known, the object data shown in Fig. 10, is installed in advance in the memory 14 program data contained in the above-described cassette memory, i.e., the external memory in accordance with the content of games, for example. Additionally, the object data read from the memory 14 program data are transmitted to the OAM 38 of the microprocessor 10.

The decoder 40 address receives the signal read/write R/W from the microprocessor 10 and the address bus addresses in order to generate the appropriate signals OAW, /ODW, RAW, SZW and ITW of them. The signal OAW is served on the register 36 addresses of TAM, as the recording signal. The register 36 address OAM load the initial address, filed on output from the microprocessor 10 in response to the signal OAW.

Scheme 42 address OAM included in the circuit 30 generating data recovery image, mainly includes the address counter and is excited by the signal OAW. Scheme 42 address OAM accepts original is amym sending data addresses for the addresses of consecutive symbols in the OAM 38 on the circuit 44 address selection (see Fig. 8). Scheme 44 address selection also receives the address data from the vector RAM 46. The vector RAM 46 stores the address of the object in respect of which the decision circuit 56 for hit detection in the range that it is in position falling within the range, as will be described below. Scheme 44 address selection selects either the data address obtained from the circuit 42 address OAM, or the data address obtained from the vector RAM 46 in order to send the selection to the OAM 38.

Signal /ODW from decoder 40 address is sent to the circuit 48 management of TAM as a signal of her excitement. Scheme 48 management OAM outputs the recording signal WE and the data for submission to the OAM 38, when the circuit 48 management OAM writes the data from the microprocessor 10 in the OAM 38.

The register 50 size is a 3-bit register and load any one of the data values of size "000-101" table. 1, shown below, which are presented in the form of a 3-bit display data from D5 to D7, supplied from the microprocessor 10. Specifically, when the signals address, data, and records in respect of instructions (specifications) case 50 dimensions given from the microprocessor 10, the decoder 40 addresses outputs the signal SZW. The register 50 size loaded data size in the CTE is the R in the recovery image. The decoder 52 size is used to decode the sent thus the data size in order to generate each of the signals S8, S16, S32 and S64, indicating the size of the object, which (dimensions) are different from each other.

Additionally, a 2-bit register 54 alternation accepts 1-bit data interleaving, indicating either alternating or Nicaraguan, data OBJV SEL, which determine whether 1 point is represented (visualized) 1 row or 2 rows at the time of rotation, from the microprocessor 10. More specifically, when the signals address, data, and records in respect of issuing instructions (specifications) of the register 54 of the rotation transmitted from the microprocessor 10, the decoder 40 addresses outputs the signal ITW. Then register 54 alternation responds to the signal ITW in order to be loaded with the data of cardownie and data OBJV SEL.

In the shown embodiment, the implementation may be represented or visualized 32 object with one line maximum. It is therefore necessary to determine which object of 128 objects that can be visualized on a single screen, must be presented to the next line. For this purpose the circuit 56 for hit detection in range and vector RAM the operation (s) of interest.

Scheme 58 address vector RAM mainly includes a counter, and produces an increment addresses for the vector RAM 46 each time the signal /INRANGE (HIT RANGE) from the circuit 56 for hit detection in the range. On the occasion when objects find themselves in the position of falling in a range that does not appear in a horizontal line, the circuit 58 address vector RAM sends a signal to NONOBJ (NO OBJECT) indicating its absence, the circuit 92 controls the buffer RAM (see Fig. 9), as will be discussed below. As described above, 1 line can visualize only 32 objects max. Therefore, when the number of objects that find themselves in the position of falling into the range, reaches 32, the circuit 58 address vector RAM sends the output signal INRANGE FULL CONTACT with the FILLED RANGE), for submission to the circuit 56 for hit detection in the range. Accordingly, the circuit 56 for hit detection in the range stops the feeding of the subsequent output signal for hit detection in the range at the circuit 58 address vector RAM.

The counter 60 size shown in Fig. 8, outputs data SC used to determine which character from a variety of characters that make up the object that should be rendered when the view is from the circuit 62 controls the counter size, in order to produce the increment of the initial value in response to the signal /HCO generated by the circuit 34 generate signals. The result of this increment is applied to the output of the counter 60 dimensions as the above-mentioned data SC, which are used to calculate the address arithmetic circuit 64 horizontal position (hereinafter, abbreviated "H"), as will be discussed below.

Scheme 62 control counter sizes sends to the output signal L indicating the synchronization regarding data loading horizontal position of the new object in the schema 64 position H. More specifically, the signal L is a synchronizing signal for the electrical process in relation to the next object, and is fed to the circuit 58 address vector RAM. Scheme 58 address vector RAM responds to the signal L in order to produce a negative increment (decrement) address vector RAM. Thus, each address of the vector RAM 46 is changed each time the signal L. When the signal L is not filed at the output of circuit 62 controls the counter sizes, functioning to translate each address in scheme 58 address vector RAM data is terminated. Specifically, when using a large object address in Oblivayutsya. Therefore, the address in the OAM 38 will remain constant until all characters of the same object will not be electrically processed in accordance with the signal L. On the occasion, the signal L can be obtained by delaying the signal C from the D-FF corresponding to the first stage.

As described above, the horizontal (H) position, data on the vertical (V) position, the characteristic data and the data names temporarily loaded into the OAM 38. However, these data read OAM 38, respectively, are loaded into a 9-bit register 66 H-position, 8-bit register 68 V-position, 8-bit register 70 signs, and a 9-bit register 72 names respectively under control circuit 74 of the control register. Scheme 74 control register controls the synchronization load each of the registers 66, 68, 70 and 72, in response to the signals L and C from the circuit 62 controls the counter size.

The register 66 H-position sends data H-position HP to the arithmetic circuit 64 H-position. Additionally, HP data is also sent to the circuit 62 controls the counter size. The arithmetic circuit 64 H-position performs an arithmetic operation according to the absolute value FOR indicating the horizontal (H) position of the object, and sends the resulting data to the CE are used as the address of the buffer RAM 84. The arithmetic circuit 64 H-position adds data indicating the H-position, and data SC from the counter 60 size and sends the result of its addition to the circuit 62 controls the counter size.

The arithmetic circuit 76 V-position receives data about the vertical (V) position VP and the signal V of the vertical interval and subtracts the V-position of the object from the position of a horizontal line which is being scanned at the moment. The result of the subtraction is used as data for determining whether or not the object to be presented to the next horizontal line. The result of the subtraction is supplied to a circuit 56 for hit detection in the range of and circuit 78 controls the adder addresses.

Scheme 56 for hit detection in the range, which is described in detail below, determines whether or not the object to be represented or visualized the next horizontal line, i.e. the object is in a position falling within the range based on the H and V positions thus obtained, and data on the size of the SR, data interleaving IR and data of signs AR. Scheme 56 for hit detection in the range makes the determination as to whether the object in position falling in the range 128 times during the azone, reaches 32, as described above, the circuit 58 address vector RAM sends a signal INRANGE FULL on circuit 56 for hit detection in the range. Thus, the circuit 56 for hit detection in the range of not sending the signal INRANGE scheme 58 address vector RAM after the filing of the signal INRANGE FULL.

Scheme 78 control adder addresses processes the incoming data before the adder 80 addresses will perform the operation of addition. Specifically, the circuit 78 controls the address adder receives the data about the H-position and V-position received from the arithmetic circuit 64 H-position and an arithmetic circuit 76 V-position, respectively, and also receives data from SR register 50 sizes, IR data from register 54 rotation and AR data from register 70 signs. When data H-position represented by H-flip (reverse (H) or V-position represented by V-flip (reverse V), the circuit 78 controls the adder addresses changes the value, add up to another value. Then, the adder 80 addresses adds together the data submitted on the output from the circuit 78 controls the adder addresses, and the data object code (which correspond to the name of the symbol, i.e., the reference address is placed in the upper position to give the address for the zone 16A storage of data symbol. Thus, this address is supplied to the output circuit 82 address/ZU video.

The buffer RAM 84, shown in Fig. 9, has a memory capacity h bit, and temporarily stores data about the color palette, the data priority level, and so on Scheme 86 invert H, which is electrically connected with the data bus is used for memory 16 video takes the color information of respective pixels (picture elements) that are read from the zone 16b storing data symbol, in order to invert the horizontal (H) directions for each point on the basis of the team inverting presented AR data received from register 70 signs. After this scheme 86 invert H sends data color scheme 88 data highlighting color. Scheme 88 highlight color data collects color information entered in each of the four color cells to obtain 4-bit color data per pixel, which is transmitted to the data input D1 of the buffer RAM 84. On the other hand, since the data of the color palette (3 bits) and the data level of priority (2 bits) from register 70 signs also served on the buffer RAM 84, the buffer RAM 84 holds 9-bit data per pixel, as described above.

Scheme 90 address buffer RAM takes absolute data in the buffer RAM produces an increment address applied to the output from the buffer RAM 84 to "0-255" during the display period (i.e. period visualization) and sends thus increase the address in the buffer RAM 84. Thus, the buffer RAM 84 reads the color data or the like in sequence. When the write data in the buffer RAM 84, the circuit 90 address buffer RAM creates a record address for the buffer RAM 84 on the basis of data of the absolute value of HA. However, the reading or writing of data from and to the buffer RAM 84 is controlled by the circuit 92 controls the buffer RAM. More specifically, the circuit 92 controls the buffer RAM receives the signal /NONOBJ generated by the circuit 59 address vector RAM (see Fig. 8), in order to prevent the writing of data in the buffer RAM 84. When these colors indicate the "transparency", the circuit 92 controls the buffer RAM also prohibits the writing of data in the buffer RAM 84.

Now will be described in detail above their respective schemes with reference to Fig. from 11 to 24.

Scheme 42 address OAM shown in Fig. 11, includes a counter 8-bit addresses (Hi) 94 and the counter 2-bit address (Lo) 96. The address counter 94 receives the address input signals A2 through A8 of the address latch (Lo) register 36A 36 address OAM and address input si is ora 36A. Address A1 is used to determine any one of the 2 words of the object, whereas the addresses A2 through A8 are used to determine any one of 128 objects. The logical element 98 AND receives the output of the D7data received from the address latch 36b, together with signals /HI, /VB (i.e., invert VB) coming from the circuit 34 to generate synchronization signals. Thus, the output of the D7data is fed through gate 96 AND to the input R of establishing the initial position of the address counter 94. When D7data becomes low level, the address counter 94 is set to the initial position and starts counting from zero each time, to be able increments. As a result, when you need to decide is whether or not the object in position falling within the range object, which primarily has been read and then determined within the range is treated as if the presence of higher prioritaire. When D7data is "1", the address counter 94 is not in the initial position, the data, which ultimately were introduced from the microprocessor 10 (see Fig. 1), are set as the data of the original value as it is. Thus, the object indicated such on the cash /HCO, coming from the circuit 34 to generate the synchronization signal, selectively sends the address counter 94 pulses whose frequencies are different from each other during vertical locking and the other period is not a period of the vertical locking. More specifically, since the output D=FF 102 receiving a signal IN sent from circuit 34 generate the clock as the input data and the signal HCO sent from the circuit 34 to generate a clock as a clock pulse, is sent to the input of logic element 104, And the signal VB supplied from the circuit 34 to generate the synchronization signal, is entered in the logical element 104 And and gate 104 And generates a signal which becomes low level during the period of the vertical locking. The selector 100 data responds to a signal of low level in order to make a decision, whether filed clock pulse, synchronized with the signal /HCO received from the circuit 34 to generate a clock for clock the address counter 94 or clock synchronized with the sampling clock of the microprocessor 10, i.e., signal OAW from the address decoder 40 (see Fig. 7). Thus, the address counter 94 receives the clock pulse, which sinkronizirano vertical locking, while the address counter 94 receives the clock pulse, synchronized with the internal clock during a different period than the period of the vertical locking.

The output of logic element 104 And is fed through a logic element 108 OR the address counter 94 as the excitatory input T together with the signal transfer C being output from the address counter 96.

The signal VBH coming from the circuit 34 generating the synchronization signal, is fed to the D-FF 110, as its input, while the signal HCO from the circuit 34 to generate a sync signal is fed to the D-FF 110 as the input clock pulse. The signal VBH also served on the output of D-FF 110 and the logical element 112 I. Thus, the output of the logic element 112 And becomes high level when the synchronization signal HCO. Additionally, the output of the logic element 112 And is fed through a logic element 114 is NOT-OR at the data input of each D-FF 116 and 118 together with signals OAW1 and OAW2, educated the address decoder 40. Signal /10M coming from the circuit 34 to generate the synchronization signal, is fed to the D-FF 116 as his clock pulse, while the 10M signal coming from the circuit 34 to generate a sync pulse is applied to the D-FF 118 as the sync pulse. the TA 114 NOT-OR. Thus, the logical element 120 is NOT-OR outputs numeric data is equivalent to the address on the data bus when the microprocessor 10 sets each address OAM 38. However, the synchronization signal LD to load numeric data in the address counter 94 is fed to the address counter 94.

Scheme 44 sample addresses, shown in Fig. 12 is used for sampling or addresses A2 through A8 being output from the address counter (Hi) 94 scheme 42 OAM address or addresses A2 to A8 of the vector RAM 46, in order to apply for the main OAM 124 OAM 38. More specifically, the signals /VB and /IN coming from the circuit 34 to generate the synchronization signal, are fed through the logical element 126 is NOT-OR selector 122 of the data. Thus, the selector 122 sends data addresses A2 through A8 coming from circuit 42 address OAM, on the main OAM 124 during the period of the vertical locking. Similarly, the selector 128 data is used to sample either of the addresses A0 through A4 received from the address counter (H) 94 and address counter (Lo) 96 in scheme 42 address OAM or addresses A0 through A4 of the vector RAM 46 in response to the signal /VB received from the circuit 34 to generate the synchronization signal in order to send him to the auxiliary TAM 130 OAM 38. Additionally, the selector 122 data in the signal VB, received from the circuit 34 to generate the synchronization signal. Two input logic element 134 And receive the signal HCO and the signal IN received from circuit 34 generate the clock. Thus, the data submitted on the output from the microprocessor 10 are recorded in the OAM 38 during the period of the vertical locking, whereas higher or the left-most data object DOH and lower or the right-most data object DOL is read from the primary OAM 124, i.e., the OAM 38 in response to the internal clock pulse in the other period than the period of the vertical locking to apply for the exit.

The OAM 38 is divided into two sections, i.e., the main OAM 124 and auxiliary TAM 130. The reason for this is that the data bus for the microprocessor 10 of 8 bits, and the data object is loaded into the OAM 38 of 34 bits, as described above. Specifically, as shown in Fig. 10, 8-bit data is loaded into the main OAM 124 four times, and the remaining 2 bits (= from 34 to 32) are grouped together or multiplied by four in order to be 8-bit data, which are then loaded into the auxiliary TAM 130. Thus, the high-order 9-bit N-way data and 1-bit data size loaded in the auxiliary TAM 130.

Schemes is bhakta, educated by the microprocessor 10, the OAM 38. Specifically, the data D0 through D7 are fed to the data latch 136, as its output signal, while the output of the data latch 136 is supplied to the data latch 138 is provided as an input signal. The data latches 136 and 138 are taking as his signal latch signal /PAW applied to the output of the address decoder 40 (see Fig. 7), and the output of logic element 140 NOT-AND, respectively. The logical element 140 NOT-AND takes the address of JSC submitted to the output circuit 42 address OAM, and the signal /ODW, served on the output of the address decoder 40. Address AO is inverted by inverter 144 in order to apply for the logical element 142 is NOT-AND the only way out of it. Additionally, the logical element 142 is NOT-AND receives signal /ODW mentioned above. Thus, when the address AO low (voltage level), the latch data 138 captures data in response to the signal /ODW. When the address AO is high (voltage level), the logical element 142 is NOT, AND sends the recording signal on the main OAM 124, and higher and lower data object DIH and DIL, which is fixed in the data latches 136 and 138, respectively, are recorded in the main OAM 124.

As a subsidiary of TAM 130 is not 16-bit type, a data entry in the OAM 130 manufactured by the which is fixed in the data latch 138, recorded in the auxiliary TAM 130.

On the occasion, scheme 48 management OAM includes two logical element 146 and 148 are NOT-OR. The logical element 146 is NOT-OR takes the address A9 circuit 42 addresses of TAM, which is inverted by inverter 150, and the signal VB supplied from the circuit 34 to generate the synchronization signal. Additionally, the logical element 148 OR directly address A9 and the signal VB. Thus, when the address A9 is a high level voltage during the vertical locking, logical element 148 OR sends a driving signal to the auxiliary TAM 130. When it is low voltage level, the logical element 146 is NOT-OR sends a driving signal to the main OAM 124. Higher data object DOH, read from the main OAM 124 are loaded into the register 68 V-position, the register 70 signs and the register 72 names, while the lower data object DOL read from there, loaded into the register 66 H-position and the register 72 names.

As described above, the specific data object data are loaded into the auxiliary TAM 130 so that four objects are grouped or collected. Therefore, the selectors 150 and 152 data load 2 bits, which prinadlejali, when loading data into the main OAM 124.

Scheme 58 address vector RAM shown in Fig. 13, includes a 5-bit reversible counter, i.e. With/In counter 154 (/=sum/subtractive approx. the translator). Data counted With/In counter 154 are served at the addresses A0 through A4 vector RAM 46. The signal IN supplied from the circuit 34 to generate the synchronization signal, is sent to the data input of D-FF 156, the output of which is fed to the data input of D-FF 158. Signals HCO and 5M from the circuit 34 to generate the synchronization signal serves on the D-FF 156 and 158 as input sync them accordingly. The output of D-FF 158 is fed to the logical element 160 is NOT-AND, as the input signal together with the signal HCO, and the output of logic element 160 is NOT-AND output logic element 162 is NOT-AND served on the logical element 164 NOT-OR as two input signal. On the occasion, the signal /LB and /HCO received from the circuit 34 to generate the synchronization signal serves two input logic gate 162 NO-GI Advanced output logic element 164 is NOT-OR is served on/In the counter 154, as its input the reference signal, i.e., its clock pulse. Thus, the clock pulse With the/In the counter 154 is determined by the signal HCO coming from the circuit 34 to generate the clock.

Further, the signals 5M and HCO coming from the circuit 34 to generate the synchronization signal, are fed to the input of logic element 168 is NOT, the output of which is fed to the logical element 170 is NOT AND together with the signal /INRANGE coming from circuit 56 for hit detection in the range. Then, the signal INRANGE is supplied to the data input of D-FF 172, and the output of logic element 168 is NOT-AND served on the D-FF as its clock pulse. The output of D-FF 172 is supplied to the selector 174 data as its one input, and the signal /LB is supplied to the data selector 174 as its input the switching signal. Additionally, the output of logic element 170 is NOT-AND is served on RS-176, as its set input /S, and the signal /HI coming from the circuit 34 to generate a sync pulse is applied to RS-FF 176 as its input the signal /R baseline position. The output of RS-FF 176 is sent to the logical element 178 And as its input signal. Or the signal /HBH or L from the circuit 34 generating synchro the signals.

Therefore, when the signal /LB becomes a high level voltage during the period when the determination is made contact with range, C/B, the counter 154 is excited to select the operation of summation of reference. Then D-FF 172 generates a driving signal each time the signal INRANGE indicating status falling in the range becomes the low voltage level, and therefore C/B counter 154 believes in the forward direction, the pulses supplied at the output of the logical element 164, NOT-OR. Counted value C/B of the counter 154 is fed to the vector RAM 46 as the address of record. When C/B counter 154 believes in the forward direction clock, and counting the value of C/B of the counter 154, i.e., the number of objects within the range, reaches 32, is able to render a single line, the logical element 186 and the D-FF 188 generate a signal INRANGE FULL. As a consequence, the circuit 56 for hit detection in range, de-energized in response to the signal INRANGE FULL. On the other hand, when the signal /LB is a low voltage, C/B, the counter 154 is excited to select the operation countdown, after which he counts backwards the clock every time the signal L from the circuit 62 controls the counter size. For the read address. When all objects are read counted value C/B of the counter 154 reaches "0" and the signal transfer is sent to the D-FF 182, thereby obestochena C/B counter 154.

When the circuit 56 for hit detection in the range produces a start operation determination falling within the range, the signal /HI generated by the circuit 34 generating a sync signal is input to establish in the initial state/In counter 154, and also served on the RS-FF 176, as its input signal setting in the original position. If the object is within the range in the following is not detected, then the output of RS-FF 176 remains low level voltage. Then the output of RS-FF 176 passes through the D-FF 190 and D-FF 192, which in turn is output as a signal /NONOBJ in response to the signal HCO received from circuit 34 generate the clock. Signal /NONOBJ is fed to the circuit 92 controls the buffer RAM (see Fig. 9).

Scheme 74 control registers shown in Fig. 14, has a logical element 194 is NOT-OR and logical elements 196, 198 NON-And. the Signal being output from the circuit 62 of the control counter dimensions (see Fig. 8), and the signals VB and IN coming from the circuit 34 to generate the synchronization signal, are sent to the inputs of the logic element 194 is NOT-OR. The inputs of the logical is aerovane clock, accordingly, while the inputs of the logic element 198 is NOT-AND serves signal L generated by the circuit 62 of the control counter dimensions (see Fig. 8), and the signals 5M and HCO coming from the circuit 34 to generate the synchronization signal, respectively.

The arithmetic circuit 64 H-positions includes an 8-bit full adder 200 in relation to one, i.e., from A0 to A7, from input to which is supplied the output of the logic element 202 EXCLUDING OR, in respect of the other, i.e. from B3 to B5, the input to which is supplied the output of the logic element 204 I. On the occasion, to the remaining input of the above inputs of the full adder 200, is ground potential, i.e., the "0" potential. Data H-positions from D0 to D7 from the first register 66A H-position register 66 H-positions, served on one of the inputs of the logic element 202 XOR with the input signal transfer CIN supplied from the logic element 206 I. Thus, when the input signal transfer CIN is high voltage level, the data D0 and D7 are inverted by logic element 202 EXCLUDING OR, in respect of the other, i.e. from B3 to B5, the input to which is supplied the output of the logic element 204 I. On the occasion, the remaining input of the above inputs para 66A H-position register 66 H-position, served on one of the inputs of the logic element 202 XOR with the input signal transfer CIN supplied from the logic element 206 I. Thus, when the input signal transfer CIN is high voltage level, the data D0 to D7 are inverted by logic element 202 XOR, and inverted so data are fed to the full adder 200, the input signal A0 to A7 mentioned above.

On the occasion, the logical element 206 N receives the data D8 sent from the second register 66b H-position register 66 H-positions, and the output of logic element 208 OR. When the data D8 is "1", horizontal (H) position of the object falls in the negative (minus) district, as shown in Fig. 15, while the H-position of the object falls in a positive /polosovoi/ area, as shown in Fig. 15. Specifically, the actual screen of the monitor 22 (see Fig. 1) to render it of the object corresponds to the right half of the screen when viewed from the point of intersection of the coordinates (o, O), as shown in Fig. 15. The horizontal position is represented in the range of "0 to 255", i.e, "000H-OFFH" in the context of such a display screen. However, in the present implementation to smoothly render the part of the object in the region of the imaginary screen, defined by the left half of the screen of the monitor 2, it is assumed, even if the object is rendered outside the range of the display screen, and the horizontal position can be established even at this range. The horizontal position is represented in the range 256-511", i.e. "100H-1FFH" when the object is exposed outside the range of the display screen. When data H-position D8 are "0" during the determination period falling in the range, the data D0 through D7 are directly served by the full adder 200, the input signal A0 through A7. At this time, the inputs from B3 through B5 becomes low voltage level in the signal IN is supplied by a circuit 34 for generating the synchronization signal, which indicates the state of an object placed on the stage of determining the exposure range. Thus, the output of the full adder 200 is the sum of the "D0-D7+0", and therefore the data D0 through D7 are output from the full adder 200 as they are. When data H-position D8 represent "1", the data D0 through D7 are inverted logical element 202 XOR, and inverted so data are fed to the full adder 200, as an input signal with A0 through A7. At that time, the inputs from B3 through B5 are fixed to be low voltage medium When the signal HCO, submitted through the logic element 208 OR from the circuit 34 to generate the synchronization signal, a high level voltage, and if you use another process instead of the above, or "D0 D7 + 0" or "D0 D7 + 1" full adder 200 is loaded into the counter 60 dimensions (see Fig. 8) as the initial value, depending on either "0" or "1" data H-position D8. When the signal HCO low voltage level, the data H-positions D0 through D7 are served at full adder 200, as input signals with A0 through A7, as they are, and the data on SC2 SC0, served on the output of the counter 60 dimensions, served on the full adder 200 as input signals from B3 through B5. Therefore, the result of the addition of both data applied to the output of the full adder 200.

Thus, the reason for converting H-position in absolute value in the arithmetic circuit 64 H-positions is that the object is intended for visualization of the left end of the display screen except for the parts of an object that is outside the display screen of the monitor.

On the occasion, the arithmetic circuit 76 V-position includes an 8-bit full adder 210 in relation to one, i.e., from A0 to A7, from inputs that provides data V-positions D8 through D15 register 68 V-position, inverted inverter the project for a clock. Then the result of adding both of the inputs of the full adder 210 is fed to the circuit 78 controls the adder addresses and circuit 56 for hit detection in the range (see Fig. 8), as data on the vertical (V) position of the object.

The register 50 dimensions shown in Fig. 16, includes first, second and third registers size 50a, 50b and 50c, each of which receives the signal load signal SZW sent by the decoder 40 addresses (see Fig. 7). Each of the first, second and third registers 50a, 50b and 50c, receives data D0 through D7 received from the microprocessor 10 (see Fig. 1) via the data bus. The register 54 of alternations of a first and a second interleaving registers 54a, 54b, each of which receives the signal load signal ITW sent by the decoder 40 addresses (see Fig. 7). Each of the first and second interleaving registers 54a and 54b receives data D0 through D7 sent over the data bus from the microprocessor 10 (see Fig. 1). The first register sizes 50A load data BASE address in the memory zone of the object, and the second register sizes 50b loaded data SEL. Additionally, the third register 50 is loaded with data of size. The first register rotation 54A loaded data interleaving for decision-making, Budelli implemented another display is zagruzaetca data OBJ VSEL.

Data BASE and SEL loaded in the first and second registers sizes 50a and 50b are used to determine the address in memory 16 video for arbitrarily setting the storage area 16A of the background image and the storage area 16b data symbol ZU 16 video data (see Fig. 1) formed in a single unit's RAM, as described above. Specifically, the memory 16 of video data shown in Fig. 17 and 18, has a memory capacity of 64 kilobytes (words), which allocated 4 KB area 16A is designed for data BASE defined data D0 by d

Additionally, other areas 16B1, 16B2, 16B3, each of which is represented in the form of 4 kilobytes, and the other zone 16B4, which is also presented in the form of 4 kilobytes, designed for data SEL-defined data D3 and D4. The object type can be changed only by correctly combining the data BASE and SEL and change 2 bits defining data SEL. More specifically, data of the character object required at some stage in the game, loaded into any one of the designated zones 16A and other areas with 16B1 on 16B4, and character data of the object needed in another scene, loaded into one of the remaining zones number of zones with 16B1 on 16B4. Thus, the object type can be easily changed for each game scene by simple generous garden light with the desired object is required.

3-bit data size D5 through D7 sent the third register sizes 50C, are input to the decoder 52 sizes. The decoder 52 size decodes the 1-bit data select size SEL supplied from the first register signs 70A (see Fig. 14) included in the register of the signs of 70, and the data size D5 through D7 in order to emit signals indicate sizes S8, S16, S32, S64, respectively, from the corresponding logical elements are NOT-OR 52a, 52b, 52c, 52d. Specifically, when the signal S8 denote the size of the submitted output from the logic element is NOT-OR 52a, object (formed single character) in the form of a horizontal x vertical 8x8 pixels will be selected. When the signal S16 denote the size of the submitted output from the logic element is NOT-OR 52b, the object (formed four-block symbol) in the form of a horizontal x vertical 16 x 16 pixels, is selected. When signal S32 denote the size of the logic element is NOT-OR s, object (formed shestnadcatiletnie symbols) in the form of a horizontal x vertical 64 x 64 pixels, is selected.

These signals S8, S16, S32 and S64 denote the size of the control adder addresses as signals /OBJ8, OBJ16, /OBJ32 and OBJ64 respectively. Consequently, the falling in the range while the signals S32 and S64 denote the size are fed to the selector 216 data. Further, the signal S64 denote the size is supplied to the selector 218 data as one of its two inputs, and the other one of its inputs is fixed at "1". Each of the data selectors 214, 216 and 218 receives the data interleaving as the signal sample, which is output from the second register alternations 54b, included in the register of alternations 54. The size of the object is changed at the time of rotation and Nicaraguan. When the dot density is increased at the time of rotation, for example, the size of the object decreases. Accordingly, resize, used as the criterion to determine the exposure range on the basis of the signal indicate the amount submitted by the decoder 52 size that you need. To perform the operation of determining the exposure range in accordance with the difference in size between objects are data selectors from 214 to 218.

The output of the data selector 214 is inverted by the inverter 220, and inverted so the output is on one of the two inputs of the logic element And 224 through the logical element OR 222. The output of the logic element And 226 is fed through an inverter 222 to the other one of the inputs of the logic element And 224. Two input and the signal S8 denote the size, supplied through the inverter 228 from the logic element is NOT-OR 52a. Data V-position D3, served on the output from the arithmetic circuit 76 V-position, is fed to the other one of the outputs of the logical element And 224.

The outputs of the data selectors 216 and 218 are served on the logical element 230 And, as two of its three input signals. Information about V-position D4, served on the output of the arithmetic circuit 76 V-position, served on the logical element And 230 on the other remaining input. Additionally, the output data selector 218 is fed to the logical element And 232 together with the data V-position D5 supplied from the arithmetic circuit V-position. The output of the logic element And 226 is fed to the logical element And 234 together with the data V-position D2 is sent to the output of the arithmetic circuit 76 V-position. The respective outputs of these logic elements And 224, 230, 232 and 234, are inverted together with the data V-position D7, served on the output of the arithmetic circuit 76 V-position, and thus the inverted data, all served on a logical element And 236 as its input signals.

Further, the output of the logic element is NOT-OR 238 is fed to the logic element is NOT-as its input signal. Two inputs of the logic element is NOT-OR 238 accept these H-position the second element is NOT-AND 240 receives as input signals the outputs of logic elements NOT-241, 242 and 244 and inverts each of the data about H-position D6 and D7, send the register 66 H-positions. Two input logic gate 241 is NOT-AND take the output of the inverter 228 is used to receive signal S8 denote the size and the data H-position D3 supplied by the register 66 H-positions. Additionally, three input logic element is NOT-AND 242 serves data on H-position D4, sent by register 66 H-positions, and the signals S16 and S32 denote the size. Next to two inputs of the logic element is NOT-AND 244 serves data on H-position D5, send the register 66 H-positions, and the signal S64 denote size.

The output of the logic element is NOT-OR 238 is used as a signal that indicates, or is not in a position falling within the range in the horizontal (H) direction. Each of the outputs of logic elements And 224, 230, 232 and 234, is used as a signal indicating whether or not each of the data D5 and D7, send an arithmetic circuit 76 V-position in the position-hit range in the vertical (V) direction.

Then the inputs of the logic element is NOT-AND 236 receive the output of the logic element is NOT-OR 238, the outputs of logic elements And 224, 230, 232, 234, the output of D-FF 246, at its data input signal IN, send circuit 34 generate with the CSOs RAM. Thus, when the signal IN the input, and the signal INRANGE FULL is not input, the logical element is NOT-AND 236 sends a signal INRANGE, indicating that the detected or determined, the object is set to hit the range in the horizontal and vertical directions.

Scheme 62 control counter dimensions shown in Fig. 19 includes a data latch 248 to which the signals of the object's size /OBJ8, /OBJ16, /OBJ32 and /OBJ64 respectively, sent by the circuit 56 for hit detection in the range, i.e., from logical elements are NOT-OR 52a, 52b, 52c and 52d decoder size 52.

Then, the data H-position D8, sent by the register 66 H-position, serves two inputs of each of the logical elements 250, 252 and 254. The data D3, D4 and D5 data ON absolute values, respectively, served on the other of the two inputs of each logic element And 250, 252 and 254. The output of each logic element And 250, 252 and 254 is supplied to the counter size 60 as the initial value. When data on the H-position register 66 H-positions are positive (plus), the position to start operations on the display of the object appears in a certain location on the display screen of the monitor 22 (see Fig. 1). So "0" is always entered as dagania, and data about the starting or initial value set in the counter of size 60, are set to "0". On the other hand, when data H-position register 66 H-positions are negative (minus), "1" is always entered as data H-position D8. When data H-position are, for example, "-8", the absolute value of their HA is set to "8" and will be presented in the form of data bit "1000". Thus, D3 absolute value becomes high level voltage, and the output of the logic element And 250 also becomes a high level voltage. So "1" is set in the counter size 60 as the initial value. If the shift in the negative direction increases, the absolute value, i.e. the initial value is set in the counter size 60 increases.

Signal /HCO sent by the circuit 34 generate a clock is supplied to the counter size 60 as the sync pulse. Thus, the counter size 60 produces an increment of the initial value set as described above, for each signal /HCO. On the occasion, the signal IN fed to the output circuit 34 generate a clock is supplied to the counter of size 60, as its input signal ustanovlennoy 56 for hit detection in the range of operation of such a definition.

Then the output SC meter size 60 fed into the control circuit of the address adder 78, as described above, and to one of two inputs of each of the logical elements And 256, 258 and 260. Signals /OBJ16, /OBJ32 and /OBJ64, fixed in the data latch 248, served on the other of the two inputs of each logic element And 256, 258 and 260. Additionally, the output of each of the logical elements And 256, 258 and 260 is fed to the logic element is NOT-OR 262 together with the signal /OBJ8, which is fixed in the data latch 248. The output of D-FF 264 and 266 are served respectively to corresponding inputs of a logic element is NOT-OR 262. The output of the logic element And 268 is applied to one of two inputs of the D-FF 264, while the signal from HBH circuit 34 for generating the synchronization signal is fed to one of two inputs of the D-FF 266. The logical element And 268 receives the data D3 to D7 from the arithmetic circuit 64 H-positions, and the data D8 about the H-position register 66 H-positions, which are inverted by the inverter 270. Signal /HCO filed by circuit 34 generate the clock, served as the synchronization signal to each of the D-FF 264 and 266 in a manner analogous to each signal of the recording data selector 248. The output of the logic element is NOT-OR 262 is fed to the D-FF 272 as its input and circuit 74 controls registry.nl her.

Scheme 78 management address adder shown in Fig. 20, includes a D-FF 274 for receiving signals about the size of the object /OBJ8, /OBJ16 and /OBJ32 respectively, sent by the circuit 56 for hit detection in the range, i.e., from logical elements are NOT-OR 52a, 52b and 52c of the decoder size 52. The signal HCO filed by circuit 34 for generating the synchronization signal, is fed to the D-FF 274 as their signal. Signal /OBJ8, sent from the D-FF 274, is fed to one input of each logic element And 276, 278, 280, 282, 284 and 286. Signal /OBJ16 from the D-FF 274 is supplied to another one of the inputs of each logic element And 278, 280, 284 and 286. Signal /OBJ32 from the D-FF 274 is supplied to another one of the inputs of each logic element And 280 and 286. Data H-FLIP, filed on case characteristics 70, serves on the remaining inputs of the logic elements And 276, 278 and 280, while the data V-FLIP case-sensitive characteristics 70 serves on the remaining inputs of the logic elements And 282, 284 and 286. Data V-FLIP case-sensitive characteristics 70 then served on one of the two inputs of each logic gate EXCLUSIVE-OR 288, 290 and 292. The output of each logic element And 276, 278 and 280 is fed to one of two inputs of each logic gate EXCLUSIVE-OR 294, 296 and 298, together with the data from the on SC2 SC0, send sketchcom size 60. Vihodyashie OR 300, 302 and 304. The output of the selector 306 6-bit data is fed to the other of the two inputs of each logic gate EXCLUSIVE-OR 288, 290, 292, 300, 302 and 304.

The data selector 306 receives the signal FIELD generated by the circuit 34 for generating the synchronization signal, and the output of the D-FF 308 for receiving data D0 to D5 from the arithmetic circuit 76 V-positions, each of which indicates the difference or distinction between V-position and line number of the scan. Signal /HCO submitted to the output circuit 34 for generating the synchronization signal, is fed to the D-FF 308 as its signal. D-FF 308 sends the data D0 through D4 to one of the inputs of the data selector 306 and sends the data D0 through D5 to another of its inputs. Then the data selector 306 selectively outputs the input signals received from the D-FF 308 in response to data OBJ V SEL sent by register 54 alternations, and sends the selected output signal to each logical EXCLUSIVE OR element 288, 290, 292, 300, 302 and 304.

Scheme 78 control adder addresses mainly changes the address at run time H invert and/or invert, as shown in Fig. 21 (a-d). Referring to Fig. 21, and the data H-FLIP and V-FLIP to "0" and H invert, and V invert not produced. Referring to Fig. 21b, the data H-FLIP to "1",Finance is not made. Referring to Fig. S, data H-FLIP to "0" and data V-FLIP to "1", and therefore H inversion is not performed, and V inversion is performed on the horizontal axis 312. Referring to Fig. 21,d data H-FLIP and V-FLIP to "1", and the inversion of H and V is the vertical and horizontal axes 310 and 312, respectively.

Referring now to Fig. 20 as H - or V-inverted distances change according to the size of the object, the signals /OBJ8, /OBJ16 and /OBJ32 sent by the decoder size 52, serves on the corresponding logical elements, And 276, 278, 280, 282, 284, 286 accordingly, as the input signals. When an object is represented in the size 8x8, signal /OBJ8 will be low voltage. Therefore, the output of each logic element And 276, 278, 280, 284 and 286 becomes low voltage. Thus, the logical XOR 294, 296 and 298, respectively, serves to output data size with SC0 and SC2 coming from counter sizes 60, as additive addresses AA, AA and AA as they are, so that each address is not inverted. When the object is represented by 16x16, signal /OBJ16 becomes a low level voltage. As a consequence, the only logical elements And 276 and 282 is excited, and the output of each of the remaining LGD data size SC0, submitted on meter size 60, inverted logical EXCLUSIVE OR element 294 to feed the output as an additive address AA. When the object is of size 32x32, signal /OBJ32 becomes a low voltage level, thereby arousing the logical elements And 276, 278, 282 and 284, in order to make the output of the remaining logic elements And 280 and 286 low voltage level. If the data H-FLIP to "1" at this time, the data size SC0 and SC1 sent from counter sizes 60, inverted logical EXCLUSIVE OR element 294 and 296, respectively, in order to emit as additive addresses AA and AA. When the object is of size 64x64, signals /OBJ8, /OBJ16 and /OBJ32 become a high voltage level, thereby stirring all the logical elements, And 276, 278, 280, 282, 284, 286. If the data H-FLIP to "1" at this time, the data size with SC0 and SC2, served on the output meter sizes 60, inverted logical XOR 294, 296, 298, respectively, for supply to the output as an additive addresses A on AA.

In the case of V-invert invert the bottom three, i.e., the most right-wing bits of the address supplied to the circuit 82 ZU video/address shows the inversion of the horizontal line, and invertirovat right bits not related to the size of the object, each logical EXCLUSIVE OR element 288, 290 and 292 inverts or does not invert the data transmitted from the data selector 306 in response to a "1" or "0" data V-FLIP in order to emit as three of the most right-wing bits A0, A1 and A2 of the address sent on the circuit 82 ZU video/addresses. Additionally, three of the most left bit is processed in the same manner as in the process of the preceding H invert. Specifically, each of the logical elements And 282, 284 and 286 sets the conditions of the object in relation to size, and each logical EXCLUSIVE OR element 300, 302 and 304 inverts or leaves the non-inverted data received from the data selector 306 under such conditions in accordance with either "1" or "0" data V-FLIP for submission to the exit as the three left most bit AA8, AA9 and AA10 sent to the address adder 80.

On the occasion, the logical elements And 314 and 316 included in the circuit 78 controls the address adder is fed to the output additive addresses AA12 and AA13 respectively. However, such addresses AA12 and AA13 is used to denote any one of the zones with 16B1 on 16B4, shown in Fig. 17 and 18.

The address adder 80, shown in Fig. 22, includes three 4-bit full address 80a, 80b and 80c. The outputs of these three full address 80a is Oh 78 control adder addresses served on the scheme 82 ZU video/address as his address with A0 through A2, whereas the signal HCO coming from the circuit 34 to generate the synchronization signal, is fed to the circuit 82 ZU video/address as its address A3. On occasion, data BA E of the first register sizes 50A (see Fig. 16) case size 50, makes a decision regarding which input bits in the full adders with 80A through 80C discharged to ground potential. Additionally addresses A0 through A15 video data in the memory device 16 is determined by the circuit 82 ZU video/addresses, and the data D0 through D15, filed on output from the video ZU 16, is sent to the circuit 86 inverting H.

Scheme 86 invert H, shown in Fig. 23, includes a data selector 318 that provides data D0 through D15 sent ZU video 16. The data selector 318 has 16 data selectors each of which selects one of the 2-bit inputs in order to submit it to the output in the form of one bit. The output of D-FF 320 is supplied to the data selector 318 as its signal sample. Data H-FLIP serves on water data D-FF 320, and the signal /HCO submitted to the output circuit 34 for generating the synchronization signal, is fed to the D-FF 320 as its signal. The data selector 318 outputs the data in accordance with the following table. 2 in response to signals is installed, coming from ZU video data 16 in the form of 8 bits in accordance with whether or not to enter the command invert H-FLIP horizontal (H) direction. Image data supplied to the output circuit 86 inversion H, served on the scheme 88 data extraction color.

Scheme 88 extracting color data contains four data selector, i.e., the first data selector 322, the second data selector 324, the third data selector 326 and the fourth data selector 328. Each of the data selectors 322, 324, 326 and 328 selects any one of the 8-bit inputs and outputs only one bit is selected in this way. The signals of the NRA, 5M and HCO supplied to the output circuit generating signals 34, served on each of the selectors, it is the first data selector 322, the second data selector 324, the third data selector 326 and the fourth data selector 328, as their select signals. Image data that is submitted to the output circuit 86 invert H, served on each 16-bit D-FF 330 and 332, and the output of D-FF 332 is fed to the D-FF 334. Signal /HCO sent by the circuit 34 for generating the synchronization signal, is fed to each D-FF 330 and 334 as their signals, while the signal HCO filed with the circuit 34 generate signals, is fed to the D-FF 332 as its clock pulse. Additional the M from the circuit 34 to generate a sync pulse is fed to the D-FF 336 as his signal. The output of D-FF 336 served on each D-FF 330 and 334 as the input signal setting in the original position.

D-FF 332 hold the first 16-bit graphics data sent by the circuit 86 invert H in response to the signal HCO. Additionally the D-FF 330 holds the following 16 bits in response to the signal /HCO. At this time, the first 16 bits, which were held by the logical elements of the D-FF 332, shift to the D-FF 334 in response to the signal /HCO. Thus, image data of 32 bits in General serves as an 8-bit to 8-bit first data selector 322, the second data selector 324, the third data selector 326 and the fourth data selector 328, as their input data. Each of the data selectors 322, 324, 326 and 328 selects one bit in accordance with the following table. 3 in order to apply for the output color data cell (picture element) of 4 bits as a whole. Thus, the circuit 88 extracting color data defines or identifies four color cells.

The buffer RAM 84, shown in Fig. 9, includes a first buffer RAM a and the second buffer RAM 84b, each of which has a memory capacity of 128 9 bits (i.e., 9 bits x 128). One buffer RAM can normally be used as the buffer RAM 84. However, the present embodiment shows the case when Buda as point even numbering is loaded into the second buffer RAM 84b. More specifically, the data selectors 322, 324, 326 and 328 schema 88 retrieving the color data selectively fed to the output data from 0D0 on 0D3 indicating points odd numbering, and data from 1D0 on 1D3 indicating points even numbering accordingly, in response to the signal HCO filed by circuit 34 generate the clock. Submitted thus on the output data from 0D0 on 0D3 and 1D0 on 1D3 respectively sent to the first and second buffer RAM 84a and 84b as its input data.

When you need to read the requested data from the buffer RAM 84, the data is first read from the first output latch a and the second output latch 338b at this time, and the read data is then fed into the circuit synthesizer 28 (see Fig. 2).

Scheme 90 address buffer RAM shown in Fig. 25, includes an 8-bit counter 340. The output of the counter 340 is fed to the circuit 92 controls the buffer RAM as data addresses for the buffer RAM 84. The counter 340 receives as its input signal setting in the initial position signal CRES sent by the circuit 34 generate sync pulse immediately before the period of data visualization. The counter 340 receives the output signal of the data selector 342 as its signal. The signal /10M and HCO, pay circuit 34 for generating the synchronization signal, sent to the data selector 342 as the signal sample. Thus, the counter 340 produces a change in the timing when data is written in the buffer RAM 84, and a change in the timing when data is read from the buffer RAM 84. Specifically, when data is written in the buffer RAM 84, the counter 340 produces increments in response to the signal /10M. When data is read from the buffer RAM 84, the counter 340 produces increments in response to the signal HCO. Thus, when reading data from the buffer RAM 84, the counter 340 produces increments by 1 for each 2 points.

Additionally, the signal L, sent by meter size 60, is supplied to the data input of D-FF 346. The signal HCO filed with the circuit 34 generate a sync pulse is applied to the D-FF 346 as his signal. The output of D-FF 346 is fed to the D-FF 348 as the synchronization signal, which takes HCO sent by the circuit 34 generate the clock. Further, the signal HCO from the circuit 34 to generate the synchronization signal is entered into the data input of D-FF 350. The signal 5M filed from the circuit 34 to generate the synchronization signal, is input to clock the D-FF 350 and is supplied to the data input of D-FF 352. The signal 10M submitted to the output circuit 34 for generating the synchronization signal, is fed to the D-FF 352 as his signal. Then o is ω LBR, sent from circuit 34 for generating the synchronization signal, which is inverted by inverter 354. The output of the logic element is NOT-AND 344 is supplied to the counter 340 as its input loading /LD. Thus, the load time counter 340 depends on the signal L, i.e., the size of the object.

When the counter 340 serves as its inputs the outputs 9-bit logical elements of the D-FF 356, it takes absolute values D0 through D7, send an arithmetic circuit 64 H-position, and receives the output of logic gate EXCLUSIVE-OR 360 as D8, i.e., the outputs of the D-FF 358. Data of absolute values D8 sent by register H-position 66, and the signal transfer H-CARRY, sent to the arithmetic circuit 64 H-positions, served on a logical EXCLUSIVE OR element 360 as its input signals. Accordingly, the inversion of the data D8, sent by register H-positions 66, served on the D-FF 356 as its input data D8, when the input signal transfer. The output of the logic element is NOT-AND 362 is used to receive signals /5M and HCO sent by the circuit 34 generate a clock is supplied to each of the D-FF 356 and 358 as their signal.

Then, the outputs D0 and D8 from the D-FF 358, respectively, served on D-FF 364 and 366 as their input data. The output logic is udaetsya on each of the D-FF 364 and 366 as his signal. The output of D-FF 364 served on the previously described circuit 88 extracting color data as a signal HPO and served on a logical element And 370 included in the circuit 92 controls the buffer RAM. Additionally, the output of D-FF 366 is fed to the logical element And 374 through an inverter 372 included in the circuit 92 controls the buffer RAM.

Circuit 92 controls the buffer RAM includes a 7-bit full adder 376. Full adder 376 receives as its input data signals D1 through D7 sent counter 340 in the circuit 90 of the address of the buffer RAM. Full adder 376 takes for the remainder of its input B ground potential, i.e. "0". Additionally, the full adder 376 receives the output of the logic element And 370 as the input to the transfer. Full adder 376 outputs the data as addresses OA on OA each of the first and second buffer RAM a and 84b in the buffer RAM 84 for each of the first and second buffer RAM a and 84b. When the first row as the source H is a string that specifies the object that is represented by points any numbering, for example, the output of the counter 340 on the above-mentioned respective buffer RAM as addresses AA and AA as they are. When it presents points of all numberings, summary data, the resulting increment matched as addresses OA on OA.

The signal recording /WE0 and /WE1 sent to the first and second buffer RAM a and 84b (see Fig. 24) the buffer RAM 84, receive from logical elements are NOT-OR 378 and 380, respectively.

The outputs of logic elements NOT AND 382 and 384 are fed to the inputs, respectively, of the logical element is NOT-OR 378. The logical element is NOT-AND 382 receives the output of each logic element And 386, inverter 388 and logic element is NOT-AND 390, and 10M signal sent by the circuit 34 generate sync pulse. The signal 5M filed from the circuit 34 to generate the synchronization signal, and the output signal of the logic element And 392, respectively, served on two inputs of the logic element is NOT-AND 384. The signal LBW sent by the circuit 34 generating the synchronization signal, the signal /NONOBJ sent by the circuit 58 address vector RAM, and the output of the logic element is NOT-OR 394, respectively, served on three input logic element And 386. On the logical element NOT-390 is input to the inversion of each of the output signals with 1D0 on 1D3 sent by the circuit 88 extracting color data. On the logical element is NOT-OR 394 is supplied the output signal of the logic element And 374 and the output signal of the logic element And 396. Additionally, the logical element And 396 receives the output D8 counter 340, binversie each output D1 and D2 of the counter 340.

The output of each of the logic elements are NOT-AND 400 and 402 is fed to each of the two inputs of the logic element is NOT-OR 380. On the logical element is NOT-AND 400 serves the output of each logic element And 386, logic gate xnor 404, the logic element is NOT-AND 406, as well as the 10M signal sent by the circuit 34 generate the clock. Enter two input logic gate EXCLUSIVE-OR-NO signal 404 transfer, send full adder 376, and the output D8 counter 340. On the logical element is NOT-AND 406 served as its each input signal, the inversion of each of the outputs from OD0 to OD3 sent by the circuit 88 extracting color data. The signal 5M submitted to the output circuit 34 for generating the synchronization signal, and the output of the logic element And 392 are served at the two inputs of the logic element is NOT-AND 402. Signal /HCO submitted to the output circuit 34 for generating the synchronization signal, and the output signal of D-FF 408 served on two input logic element And 392. Signals LBR and 5M submitted to the output circuit 34 for generating the synchronization signal, respectively fed to the input data and the input clock of the D-FF 408.

As a result of this data is respectively written into the first buffer RAM 84b and a in response to signals /WE1 and /WE0 sent between two logical is reprocessor 10 sets of 9-bit address of the OAM for the register 36 address OAM (see Fig. 7). At this time, the address data and the recording signal to determine the register 36 address OAM fed to the input from the microprocessor 10. As a result, the address decoder 40 outputs the signal OAW mentioned above. At the same time, the microprocessor 10 outputs data indicating the source address. Therefore, the microprocessor 10 sets the source address for the register 36 of the OAM address in response to the signal OAW. The value of the source address register 36 address OAM and signal OAW from the address decoder 40 are fed to the input circuit 42 address OAM. Then, the signal OAW is delayed in the circuit 42 of the OAM address and then used as a signal load for internal counter (described below). Therefore, the value of the source address for the OAM 38, which is supplied from the microprocessor 10, is also installed in the circuit 42 of the OAM address with its value delayed by a small amount compared with the source address register 36 address OAM.

Then, the microprocessor 10 writes the data object in the OAM 38. At this time, the first microprocessor 10 outputs the address data and the recording signal. As the scheme is 44 sampling sites (see Fig. 8) receives the signal VB from the circuit 34 to generate a clock output output address of the address scheme OAM 42 and the output of the input address OAM 38 electricity is l /ODW in response to the data signal address and the recording signal, filed with the microprocessor 10. Then the scheme 48 management OAM captures data sent from the microprocessor 10 in response to the signal /ODW. After this fixed so the data is fed to the input data D1 OAM 38, and the signal recording/excitation WE/CE is input to OAM. Thus, the data object is sent through the circuit 48 management OAM from the microprocessor 10 is written into the address of the OAM 38 specified by the circuit 42 address OAM. After this scheme 42 address OAM consistently produces an increment of the address as described above. Thus, the object data from the microprocessor 10 is sequentially recorded respectively in the corresponding addresses.

Then, the microprocessor 10 loads the data size in the case of size 50 (see Fig. 7). At this time, the microprocessor outputs an address data and the recording signal to condition register sizes 50, and therefore, the address decoder 40 outputs the signal SZW mentioned above. At the same time, the microprocessor 10 has already filed on the data size, previously shown in the table. 1, thereby placing the data size register 50 in response to the signal SZW.

Then, the microprocessor 10 loads the 2-bit data interleaving in the case of alternations 54 (see Fig. 7). In this case, microprocesso the s 54. In the above-mentioned signal ITW is output from the address decoder 40. At the same time, the microprocessor 10 has applied to the output data sequence and OBJ V SELECT, thereby placing the data in the register alternations 54 in response to the signal ITW.

The period of the first horizontal scan.

Scheme 56 for hit detection in the range produces the detection or determination of exposure range during 1 horizontal scanning in order to record the address of the OAM object in contact with the range in the vector RAM 46.

Specifically, the circuit 58 address vector RAM (see Fig. 8) is installed in its original position in response to the signal H1, sent by the circuit 34 generate the clock, immediately before the beginning of the horizontal scan. Thus, the address vector RAM is set to "0". The data priority of the object, which is loaded into the register 36 address OAM, are fed to the address counter 96 (see Fig. 11) circuit 42 address OAM. When the data object's priority is set to "0", the address counter 94 (see Fig. 11) circuit 42 address OAM is installed in the original position, so that the OAM address is set to "0". When the data object's priority to "1", the counter adressability as the initial value of the address counter 94. When you need to make a decision or determination, is or is not an object in position falling within the range object, which has previously been subjected to such a definition, and indeed falls within the range, will be visualized on the screen of the monitor 22 (see Fig. 1) as having a preference over another object, sequentially subjected definition, which is set to hit the range. Therefore, it is possible to change the initial value of the OAM address during the operation of determining the exposure range using this method, and thereby to change the priority level of the object.

More specifically, the circuit 44 sampling sites (see Fig. 8) connects the output of the output address circuit 42 OAM address with the output of the input address OAM 38 in response to the signal IN, sent by the circuit 34 generate a synchronization signal during the interval when the circuit 56 for hit detection in the range performs the operation of determining the exposure range. Additionally, the circuit 48 management OAM sends an excitation signal on the OAM 38 at all times during a different period than the period of the vertical locking. Therefore, the OAM 38 reads data OAM in accordance with the data address submitted at the output of circuit 42 address OAM, and excited si is imenovani 72 downloaded data H-position, data V-position, data characteristics and data items (code designation of the object) from the data sent to the OAM 38, respectively, in response to the signal load sent by the circuit 74 control registers.

The position data H filed to the output register of the H-positions 66, served on arithmetic circuit 64 H-positions. As mentioned previously with reference to Fig. 15. If the high order bit data H-position is set to "0", i.e., H-position is present in the range of "0 to 255", then data H-position served on the circuit 56 for hit detection in range as they are. If the high order bit data H-position is set to "1", i.e., H-position is present in the range -256=-1" in contrast, then, the arithmetic circuit 64 H-position calculates the "2's complement" (absolute value) H-positions, and then sends the result of his calculations on the circuit 56 for hit detection in the range.

The arithmetic circuit 76 V-position receives the signal V from the circuit 34 to generate the synchronization signal. Then, the arithmetic circuit 76 V-position subtracts data V-position, served on the output of the register V-position 68, from the data of the vertical position of the string specified by the signal V, and then sends the result of your subtraction on Shemet solution gets or not the object according to its definition in the range based on the data H position arithmetic circuit 64 H-position, adjusted if necessary, data arithmetic circuit V-position indicating the result of the subtraction, the data sample size, served on the output of the register 70 signs, data size, served on the output register sizes 50 and data OBJ V SEL filed case alternations 54. If it is determined that it is positive, the circuit 56 for hit detection in the range sends a signal INRANGE scheme 58 address vector RAM.

Scheme 58 address vector RAM sends the signal recording on the vector RAM 56 in response to the signal /INRANGE from the circuit 56 for hit detection in the range. The vector RAM 46 receives the signal recording and data addresses from the circuit 58 address vector RAM and data (address OAM) from circuit 44 sample addresses in order to load the data D1 in its memory. After the schema 58 address vector RAM gave to the output signal of the entries in the vector RAM 46, each address in the vector RAM 46, respectively incremented.

In response to the signal HCO sent by the circuit 34 generate a clock circuit 42 address OAM produces an increment of the magnitude of its address OAM on the "+1". Scheme 56 definition of pop is the azone, in the same way as described above. After that, the address of the OAM 38 for the data object in the object within the range, is loaded into the vector RAM 46.

As stated previously, the circuit 42 of the OAM address is set to the initial position in accordance with the data object's priority register 36 address OAM. However, when the circuit 42 address OAM is in the initial state, the address of the OAM is changed from "0" to "127". When the circuit 42 address OAM is not installed in the original position, address OAM incremented by "+1" for "+1", since the "final set". Then the address of the OAM changes from "127" to "0", thereby leading to "end the set address -1".

The above method of determining the hit range is 128 times during the interval when it is line-scanned in the monitor 22 (see Fig. 1). However, the number of objects that can be rendered in one line, 32. Thus, when the number of objects that are in a position falling within the range reaches "32", scheme 58 address vector RAM sends a signal INRANGE FULL on circuit 56 for hit detection in range, thereby preventing the circuit 56 for hit detection in range to emit signal /INRANGE scheme 58 address vector RAM the static data object, in the same position as falling within the range are loaded into the buffer RAM 84.

Scheme 34 generating clock sends a signal HB scheme 58 address vector RAM during the period of the horizontal locking. Counting mode C/B of the counter 154 (see Fig. 13) in scheme 58 address vector RAM is changed from a mode of direct calculation on the reverse of the invoice in accordance with the signal HB. Additionally, the circuit 58 address vector RAM produces a negative increments (decrements) of each address in response to the signal HBH sent by the circuit 34 for generating the synchronization signal, and therefore the vector address of RAM in which the OAM address permanently installed data object is loaded, served on the vector RAM 46.

The vector RAM 46 receives the address from the circuit 58 address vector RAM in order to generate the desired address OAM. Scheme 44 sample address sends the address of the vector RAM 46 on the output/input terminal of the address of the OAM 38 in response to signals IN VB, sent by the circuit 34 generate the clock.

The register 66 H-position, the register 68 V-position, the register 70 signs and the register 72 names of downloaded data H-position, data, V-position, data characteristics and data name of the data object sent from the OA is e, H-position, fixed in register 66 H-positions, served on arithmetic circuit 64 H-positions. If the high order bit data H-position "0", then the circuit 64 arithmetic operations with H-position sends a "0" on the meter size 60. If the high order bit data H-position "1", the arithmetic circuit 64 H-position sends data D3 to D5 data Supplement "2" S (absolute value) H-position counter of size 60. Data sent to the meter size 60 in this way, are used to define them as blocks of character (one character block corresponds to 8 bits) of an object when viewed from the left side in the horizontal direction should be visualized on the screen of the monitor 22. When the position H of the object is represented, for example, as "504" (1F8H=-8), the complement of "2" S "8". Thus, every data D3 to D5 data Supplement 2 S is "1". This means that the object is visualized on the screen of the monitor 22 of the first character block constituting the object. However, the display of the object begins with the 0-th symbol, and therefore the first character corresponds to the second symbol, if you look on the left side.

Immediately after the start during the period of the horizontal locking circuit 62 controls the counter sizes receives the signal from HBH schemes is etcic size 60 responds to the signal load /LD circuit 62 controls the counter size, so for this advance is set to "0" when the H-position of the object is represented in the range of "0 to 255", and the data sent from the arithmetic circuit 64 H-positions, pre-installed when the H position is in the range 256-511".

Counter data size 60 serves on the arithmetic circuit 64 H-positions. The arithmetic circuit 64 H-position converts the regime arithmetic operation on the complement of "2" S in the mode of the adder in response to the signal HCO and IN sent from circuit 34 generate the clock. In this mode adder data H-position and data sent from the counter of size 60, are added together. Then the result of this addition corresponds to H-position, which take the size of the object in the horizontal direction into account and represent data H-position adjusted at the time when the symbol data of 8 pixels was recorded in the buffer RAM 84 in the number of times corresponding to the number of characters in the horizontal direction. Additionally the result of the addition is fed to the circuit 90 address buffer RAM as data addresses. At the same time, the data sent by the meter size 60, served on the circuit 78 controls the adder addresses and are used to identify the Nations subtracts the data of the V-position of each object, which is fixed in the register 68 V-position, from the data on each line number represented by the signal V sent from circuit 34 generate sync pulse and then supplies the result of the subtraction to the circuit 78 controls the adder addresses.

Scheme 78 management address adder selects either the data from D0 to D5 indicating the results of the subtraction arithmetic circuit 76 V-position, or from D0 to D4 + signal FIELD sent by the circuit 34 for generating the synchronization signal, in accordance with either "1" or "0" indicating data OBJ V SEL register alternations 54.

If the last selected circuit 78 controls the adder addresses then one line produces a graphical representation of a single point in the vertical direction. If the first select circuit 78 controls the adder addresses two lines produce a graphical representation of a single point in the vertical direction.

The data size that is loaded in the register sizes 50, decoded by the decoder size 52 in the signals /OBJ8, /OBJ16, /OBJ32 or /OBJ64.

Only the necessary bits that take into account the size of the object, from the data selected by the circuit 78 controls the adder addresses, as described above, inverted or made penverne in scheme 78 control Alannah with circuit 56 for hit detection in the range. As a result, with A0 through A2, AA4 in AA6, with AA8 on AA10 and AA12 to AA13 (see Fig. 20) sent to the address adder 80. At the same time, the circuit 78 controls the address adder receives data from the meter size 60 in order to invert or to make penverne only the necessary bits of the above data that take into account the size of the object in accordance with the data of H-FLIP filed from register 70 signs, and signals /OBJ8, /OBJ16, /OBJ32 or /OBJ64 sent by circuit 56 for hit detection in the range. After that, the circuit 78 controls the adder address sends its result to the adder address 80. Further, the circuit 78 controls the address adder receives the high-order register of the names of 72 and a data block indicating the name of the object in the register of sizes 50, so as to produce a conversion address, and then sends the result of the conversion of addresses by using the circuit 78 controls the adder addresses on the address adder 80.

The address adder 80 adds the right-most bits of the arithmetic data H and arithmetic data V filed from the circuit 78 controls the adder addresses after the implementation of the inversion of H and/or inversion of V, and the data name, issued with register names 72, and at the same time adds after this sends the result of its addition to the scheme 82 ZU video/address as the address.

Scheme 82 ZU video/address signal is received from the OAU used for each address in the memory 16 video their circuit 34 for generating the synchronization signal, so as to emit each address adder 80 addresses in the memory 16 of the video.

ZU 16 video takes away from the circuit 82 ZU video/addresses in order to send image data to the circuit 86 inversion H.

Scheme 86 inversion H inverts or does penverne graphic data of 8 pixels in accordance with either "0" or "1" data H-FLIP, sent by the register of the signs of 70 in order to apply for the scheme 88 extracting color data.

On the other hand, each address is sent to the arithmetic circuit 64 H-positions, pre-set counter 340 (see Fig. 25) in the circuit 90 of the address of the buffer RAM, and the data sent from the counter 340, served on the buffer RAM 84. Additionally, the high-order data of the position H in case H-positions 66 and the signal transfer (transfer in time, when evaluated each address buffer RAM), sent by the circuit 64 H-position, electrically processed by logical EXCLUSIVE OR element 404 (see Fig. 25) in the circuit 92 controls the buffer RAM, and thus obtained the result in advance Ushinskogo of the EXCLUSIVE OR element 404 becomes "0". Data as the output of the logical EXCLUSIVE OR element 404 in the circuit 92 controls the buffer RAM is used to generate a recording signal sent to the buffer RAM 84.

Circuit 92 controls the buffer RAM takes the output of the logical EXCLUSIVE OR element 404 in order to send any signal recording /WE0 or /WE1 to the buffer RAM 84, when the color of the point indicated by the circuit 88 extract the color information is not code that indicates transparency.

When the display object on the screen starts with points odd numbering, full adder 396 (see Fig. 25) in the circuit 92 controls the buffer RAM produces an increment of the address of the buffer RAM "+1" and the result of the increment is sent to the buffer RAM 84.

The buffer RAM 84 receives each address submitted at the output of circuit 90 address buffer RAM, the color data sent from the circuit 88 extracting color data, color data and the priority data sent by the register of 70 signs and signals record and each address issued from the circuit 92 controls the buffer RAM in order to download color data and the priority data of 9 bits as a whole.

In the shown implementation as the buffer RAM 84 is used two RAM on K bits (i.e., h bits is carried out to store the data points even numbering. Therefore, it is necessary to create two types of addresses in this implementation. However, you may use only one type of address, if the speed of response of each of the first and second buffer RAM a and 84b (see Fig. 24) is increased. In this case, the address sent from the circuit 92 controls the buffer RAM is not required.

When the object size 8x8 or more, i.e. when the object is formed of two or more characters, the counter size 60 counts in the forward direction, and then the above operation is repeated a number of times corresponding to the number of characters mentioned above.

Scheme 62 control meter sizes shall make a decision regarding the timing for holding data of each volume in the buffer RAM 84, using signals /OBJ8, /OBJ16, /OBJ32 or /OBJ64 sent by circuit 56 for hit detection in the range, and each value counted by the counter size 60. Each address in scheme 58 address vector RAM is prevented from countdown (decrementvalue) until the set of data symbols comprising one object, not everything will be written in the buffer RAM 84. The address circuit 58 address vector RAM is decremented by "-1" in the above-mentioned time to record all data of the character in buf the data to the OAM address of the next object, on the vector RAM 46. Data sent from the vector RAM 46, is sent to the OAM 38, and the data H-position, issued by the OAM 38, are sent through the register 66 H-posici the arithmetic circuit 64 H-positions. Then, the data start position horizontal display the next object is sent again to the meter size 60 circuit 64 H-positions. Additionally, the signal load is sent to the counter of size 60 from the circuit 62 controls the counter size, thereby pre-setting the position counter of size 60.

Similarly, the data object further relevant objects are then loaded into the buffer RAM 84.

During the second horizontal scanning.

During the period of the horizontal scanning data in the buffer RAM 84 is converted into the image signal in order to send RGB monitor 22 (see Fig. 1).

After the period of the horizontal locking circuit 90 address buffer RAM receives the signal /CRES from the circuit 34 to generate the clock in order to set the initial position of the counter 340 is provided in the circuit 90 of the address of the buffer RAM.

During the period of the horizontal scan buffer RAM 84 receives each address from the circuit 90 addresses buffer the data object, combined with the background image in the schema synthesizer 28 is converted into the image signal by circuit 30 to generate the image signal. Thus, the image obtained as a result of the merger of the object and the background image is visualized on the screen of the monitor 22.

In the circuit 90 address buffer RAM counter 340 counts in the forward direction in response to the signal HCO sent by the circuit 34 for generating the synchronization signal, thereby sequentially generating each increment of the address. Additionally, the buffer RAM 84 is excited to receive addresses from the circuit 90 of the address of the buffer RAM in order to generate image data that are sequentially fed to the circuit 28 of the synthesizer.

On the occasion, the data line being scanned at the moment, are output from the buffer RAM 84, and at the same time executes the previously described operation in the period of 1 horizontal scan) again to education data of the next line.

Although the details shown and described the preferred implementations of the present invention, they nevertheless illustrate only an example, and therefore it should be clear that the invention is not limited to these slozenijem the accompanying claims.

1. The display device of the moving image type in which the object can be visualized on the monitor raster type, comprising first memory means for pre-storing image data of the symbols that make up the object in the corresponding address area for each object, a means of generating data refer to the object for generating the data object type that is used to denote at least one object that is being rendered on the monitor during the next vertical scanning period on the monitor, a means of generating position data to generate position data used to represent the horizontal and vertical positions of the identified object on the monitor, this marked the object should be rendered, second memory means for temporary storage of data object type and data about the position therein, means for determining the exposure range for making the first decision of whether or not the object is an object having a portion which should be visualized on the monitor during the next period of the horizontal scanning, based on data from the vertical position, read Jory should be visualized on the monitor during the next period of the horizontal scanning, based on data from the horizontal position read from the second means, and the means of education addresses for reading education read address for the first memory means in relation to the subject, which according to the decision on this subject adopted by the means for determining the exposure range, is set to hit the range, based on the data object type, data about the position, resulting sends educated thus the read address to the first memory means, wherein the device is configured to render on the monitor large object by combining two or more characters, each containing a predetermined number of pixels in horizontal and vertical directions, respectively, provides a means of generating data defining the size to generate data related to the number of characters that is used to determine with replacement of size of the object, means for determining the exposure range is made with the possibility of making the first decision, based on data from the vertical position data and size determination issued by the tool to generate the data size determination and the second determination, based on and is continued with the ability to form a read address, based on the data object type, data about the position and definition data size.

2. The device under item 1, characterized in that the means of generating data defining the size includes a means of generating data size to generate data that is used to select the size of the object for each object, and a means of generating data symbols to generate the data indicate size, used to denote the size of the object for each screen, and the means of education read address is excited to produce the read address in the object, which according to the decision of this object is set to hit the range on the conclusion of funds for hit detection in the range, based on the data obtained by combining the data size and data indicate size, data refer to the object and data about the position.

3. The device under item 1 or 2, characterized in that the means of generating data indicate size includes means for temporary storage of data in itself denote the size generated for each screen.

4. The device under item 1, the La pre-store the data size used to select the size of the object for each object, and the data indicate size, used to denote the size of the object in respect of each screen, means for reading the data indicate size that is loaded into the third memory means, in respect of each screen, and a data size that is loaded in it for each object, and means to temporarily store therein data indicate size, read the read means, and means for determining the exposure range is excited for a decision, or is no object in position falling within the range based on the combination of data size and data indicate size.

5. Device according to any one of paragraphs.1 to 4, characterized in that the means of generating data defining the size includes a means of generating data size to select the size for each object and a means of generating mode data symbols to generate data symbols used to denote the size of each screen, and the device includes a second memory means for temporary storage of data indicate the object of the CSOs decisions based on a combination of data items, read from the second means of the data size that is issued from funds generating data size, and data mode designation issued from the data generation mode designation.

6. The device under item 5, characterized in that it contains means for temporarily storing therein data selection mode.

7. The device according to PP. 1 to 5, characterized in that it contains means for reading image data from the first means according to the read address generated by means of education address reading means for determining out of range to decide whether or not part of the object within the range according to the decision means for determining the hit range, to lie outside the range of the monitor screen, and the means of preventing read to prevent reading from the first memory means image data of the part object that falls outside the range of the screen according to the decision about this object, made by the means for determining the exposure range.

8. The device according to p. 7, characterized in that the means for determining out of range includes means for determining the left end for a decision, if the object lies behind Horiz who has a prior job to pre-define the start address, used to read image data of an object when it is established that the object lies outside the range from the left end thereof, the image data of the actual rendered characters, thereby preventing the read image data of characters that lie behind the left end of the screen.

9. The device under item 7 or 8, characterized in that the means for determining out of range includes a means for identifying the right end for a decision, lies or not the object for horizontally placed right end of the screen.

10. Removable mounted external memory on the device display moving image that is used to render the object on the monitor raster type, comprising first memory means for pre-storing image data of characters that make up the object in the corresponding address area for each object, a means of generating data refer to the object for generating the data object type that is used to denote at least one object that is being rendered on the monitor during the next vertical scanning period on the monitor, a means of generating data on the Nations of the identified object on the monitor, on which the specified object should be rendered, second memory means for temporary storage of data object type and data about the position, the means for determining the exposure range for making the first decision of whether or not the object is an object having a portion which should be visualized on the monitor during the next period of the horizontal scan, based on the vertical position read from the second memory means, and the second adjudicator's decision of whether or not the object is an object having a portion which should be visualized on the monitor during the next period of the horizontal scan, based on the horizontal position, read from the second means, a tool for generating read address to generate the read address for the first memory means in relation to the subject, which according to the decision of this object is set to hit the range, based on the data object type, data about the position at the conclusion of funds for hit detection in the range, in order to send educated thus the read address to the first memory means, wherein the device is made with the ability to visualize kruper is anee specified number of pixels in horizontal and vertical directions, respectively, the external memory includes a means of generating data sizing for generating data defining the size associated with the number of characters that is used to determine with replacement of size of the object, and means for determining the exposure range is made with the possibility of making the first decision on the basis of the data of the vertical position and the data size determination issued by the tool to generate the data size determination and the second determination, based on data from the horizontal position data and determine the size, and the means of education addresses the reading is made with the ability to form a read address based on the data object type, data about the position and definition data size.

11. External memory on p. 10, characterized in that the means of generating data defining the size includes a means of generating data size to select the size for each object and a means of generating data symbols to generate the data indicate size, used to denote the size of the object for each screen, and the means of education read address is excited to obrazovaniya in the range on the conclusion of the means of determining the exposure range on the basis of data obtained by combining the data size, the data indicate the size and data refer to the object, and data about the position.

 

Same patents:

The invention relates to computing technology, and is intended for digital image processing

The invention relates to computing and is designed for optimal digital synthesis and playback pictures, audio and other perceptions writable media or display

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Vector generator // 2100842
The invention relates to computing, and in particular to processing or image formation, in particular the proposed vector generator can be used to generate test images

The invention relates to television

The invention relates to a television and can be used in studies images

The invention relates to a television and can be used in comparative studies of images

The invention relates to computing technology, and is intended for digital image processing

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The invention relates to computing

FIELD: computer network communication means.

SUBSTANCE: method includes conversion of speech to electric digital signal, transfer of said signal to sound-playing device, conversion of person face to electric digital signal, recognition of face, its characteristic areas and their movement parameters, transfer of information along communication channels to graphic information output device, control of shape changes and space direction of artificial three-dimensional object and its characteristic areas. Method additionally includes detecting errors in face recognition and accompanying parameters by detecting mismatches between configurations of face areas and characteristics of movement thereof for speaking person in electric digital signals, and correction of mistakes before visualization of artificial three-dimensional object by forming control commands on basis of previously recorded shape signs and orientation of three-dimensional object and its characteristic areas for speech characteristics.

EFFECT: higher reliability and precision.

3 cl, 1 dwg

FIELD: aircraft instrumentation engineering; manned flying vehicle information representation systems.

SUBSTANCE: proposed device is provided with computer module, memory module and graphical module and is designed for dynamic forming of sequence of cartographic mimic frames and their animation demonstration on displays of onboard multi-functional indicators. Device employs cartographic data kept in memory and present flight data. Actual navigational information pertaining to present moment may be obtained by personnel in graphical form at high level of clearness and readability, which is achieved due to realization of definite modes and conditions of flight and conditions of several modes of flight of synthesis of cartographic mimic frames which differ in criterion of selected representations, methods of representation, cartographic projections and rules of positioning, orientation and scaling-up of cartographic representations. Mode of synthesis of cartographic mimic frames is selected automatically according to results of identification of present stage, mode and conditions of flight or at the discretion of personnel.

EFFECT: possibility of keeping the personnel informed on flight conditions at all phases of flight.

5 cl, 2 dwg

FIELD: computer science.

SUBSTANCE: method includes performing a block of operations along N1 channels, where N1 is selected from 1 to 2256, wherein received information is separated on logically finished fragments, encoded on basis of preset algorithm, to produce a block of N-dimensional sets adequate for converted source information Aj with elements like {Bm, X1, X2,...,Xn}, where j - order number of set in range from 1 to 2256, Bm - identifier, X1-Xn - coordinate of element from its coordinates center, m and n are selected from 1 to 2256; received block of sets is compared to already accumulated and/or newly produced sets from multiple channels, intersecting portions of sets are found and cut out; after that cut intersections and sets remaining after cutting are distributed among databases, placing each same set into database appropriate for it and each of sets different with some parameter to databases appropriate for them and identifiers of databases storing these sets are substituted in place of cut sets.

EFFECT: higher speed of operation, higher precision, lower costs, broader functional capabilities, higher efficiency.

9 dwg

FIELD: computer-laser breadboarding.

SUBSTANCE: using a system for three-dimensional geometric modeling, volumetric model of product is made, separated on thin transverse layers and hard model is synthesized layer-wise, thickness A of transverse layers is picked from condition, where A≤F, where F is an allowed value for nominal profile of model surface and generatrix of model surface profile passes through middle line of transverse layers.

EFFECT: shorter time needed for manufacture of solid model.

1 dwg

FIELD: computer-laser breadboarding.

SUBSTANCE: using a system for three-dimensional geometric modeling, volumetric model of product is made, separated on thin transverse layers and hard model is synthesized layer-wise, thickness A of transverse layers is picked from condition, where A≤F, where F is an allowed value for nominal profile of model surface and generatrix of model surface profile passes through middle line of transverse layers.

EFFECT: shorter time needed for manufacture of solid model.

1 dwg

FIELD: computer science.

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EFFECT: higher efficiency, broader functional capabilities, lower laboriousness.

3 cl, 5 dwg

Vector synthesizer // 2266566

FIELD: technology for processing and producing images, in particular, device can be used for forming random vector field with given statistical characteristics of synthesized realization.

SUBSTANCE: known vector generator, having noise generator, digital filters, connected to first input of adder, multiplexers, random numbers generator, n blocks of serial adders, control block, device for visual output, additionally has analysis block. Outputs of analysis block are connected to inputs of control block. Outputs of noise generator are connected to n blocks of digital filters, outputs of the latter are connected to inputs of n blocks of serial adders. Outputs of n blocks of serial adders are connected to n multiplexers, outputs of the latter are connected to device for visual output.

EFFECT: possible registration of nonlinear statistical dependencies of random-generated realization.

9 dwg

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