The extender rectangular pulses

 

(57) Abstract:

Usage: can be used in devices of automatics and computer engineering. The inventive device includes an input terminal 1, the terminal for the signal of the first discharge control code control expansion terminal for the signal of the second discharge control code control extension 3, the terminal for the signal of the third discharge control code control extension, the output terminal 6, subtractive pulse counter 7, the element OR NOT 16, the clock 20. 3 Il.

The invention relates to a pulse technique. The device, made in accordance with the proposed technical solution can be used to increase the duration of output pulses compared to the input by a certain specified amount, and the amount of expansion can be adjusted using an external installation code.

Extending the duration of the rectangular pulses is one of the important and common operations performed on the signals in the pulse technique. Extenders rectangular pulses is known. One of the famous options for building rasshirili duration rectangular pulses. - Exchange of experience in the radio industry, N 12, 1975, S. 27, Fig.2). This device will be considered as device - the first analogue in relation to the proposed. The device is the first analogue consists of the input of the switching transistors T1integrating RC circuit formed of the collector resistor R2cascade on key input transistor T1and the capacitor C1and the output stage transistor T2, the base of which is connected the output from the collector of the input of the switching transistors T1and with one lead of the capacitor C1. The emitter of the output transistor T2connected to the cathode of Zener diode D2and with one output of the ballast resistor R5the other output of which is connected to the bus power supply.

The device is the first similar works in the following way. In the absence of an input pulse, i.e., when the logic level zero at the input of the expander, the input key transistor T1locked. The transistor T2included due to the action of direct base current flowing through resistor R2from the power source. The capacitor C1charged to a voltage equal to the amount included in the Zener diode D2(the value of this on the th eABonly fractions of a volt. The voltage at the collector of transistor included T2is equal to the sum of the voltage UARTICLEand the voltage between the collector and the emitter of the transistor included T2equal to UCAN. This amount UARTICLE+UCANcorresponds to the bottom level of the output signal. The input pulse durationIunlocks key input transistor T1. On timeIthe transistor T1is turned on (saturated). When the enable input of the switching transistors T1the voltage on the base of T2decreases, and the transistor T2will be locked voltage UARTICLEstill current at its emitter. DuringIthe capacitor C1quickly discharged through the collector circuit is turned on transistor T1. The voltage at the collector of T2after locking the door will be close to +E, where E is the voltage of the power source. Voltage +E corresponds to the top level of the output voltage.

After the end of the pulse input transistor T1again locked, however, the output transistor T2some time will be locked and its collector is maintained upper level of the output voltage. Obyasnaet on which a jump may not change. The capacitor C1after locking the input of the switching transistors T1begins to charge through resistor R2from the power source +E. When the voltage on the capacitor C1and hence on the base of transistor T2will increase to values UARTICLE+eABoutput transistor T2is turned on and the voltage at its collector drops. The high voltage level on the output device (i.e., the collector of the output transistor T2) will exist during the timeI+ where the value is determined by the charging time of the capacitor C1to a voltage UARTICLE+eAB. The lifetime of the upper logic level of the output voltage corresponds to the duration of the output pulseo. The duration of the output pulse is extended in comparison with the duration of the input value . The device first performs similar thus the function of the extender.

The drawbacks - the first are similar:

High bottom level of the output signal. It is determined by the voltage UARTICLEthe Zener diode D2. High bottom level of the output signal makes a pair of such expander with other pulse to the s value of the extension length (device - first clone of any electronic circuits control the timing of generated signal does not have).

Another known device used to extend the rectangular pulse extender is described in the book (Erofeev Y. N., Impulse devices, M. : Vysshaya SHKOLA, 1989, S. 260, Fig. 5.18). This device will be considered as device - a second similar in relation to the proposed. The device is the second analogue consists of a bit cascade RK, an input connected to the input terminal of the extender, one output contact - bus negative supply voltage-E1, breathalyser capacitor, one lead of which is connected to the negative bus supply voltage-E1, limiting resistor r, one output of which is connected to another output breathalyser capacitor C1, the output transistor of type n-p-n, the base of which is connected to the other output pin bit cascade RK and the other output limiting resistor r, breathalyser resistor, one lead of which is connected to the base of the output transistor of type n-p-n, and the other bus positive supply voltage +E, collector resistor, one you is orytelling supply voltage +E. The emitter of the output transistor of type n-p-n connected to the housing (shared bus) devices.

The device is the second similar works as follows.

In the absence of input pulses output pins bit cascade RK open. Through timing resistor R1from the source of positive supply voltage +E in the chain-emitter junction of the output transistor T1type n-p-n flows direct base current, which when selected resistance value of the collector resistor R2sufficient for saturation of the output transistor T1. The output transistor T1type n-p-n is enabled and is in a saturated mode. The voltage on the collector, and hence at the output terminal, has a value of UCANnumerically constituting a fraction of a volt. The voltage +UCANcorresponds to the lower logical level of the output signal. The input pulse durationIarrives at the input terminal extender and includes bit cascade RK. On timeIoutput pins bit cascade RK closed. If: a) the voltage of the negative supply voltage-E1through isolated output contacts bit Cascada RK Pera T1takes the logical value of the upper level, close to a +E. the formation of the output pulse; b) the timing capacitor C begins to discharge through tomographically resistor r and isolated output contacts bit cascade RK. DuringIthe capacitor C has time to drain to zero.

After the end of the input pulse (completion interval I) output pins bit cascade RK open again. However, the output transistor T1remains off because the circuit base has discharged timing capacitor C and the voltage on the base (on the bus "case") is negative. Starts the charge breathalyser capacitor C through the circuit: bus source of positive supply voltage +E; timing resistor R1; tomographically resistor r; the timing capacitor C; bus source of negative supply voltage-E1. The time constant of the charge circuit of the capacitor is determined mainly by the elements C and R1. As charge breathalyser capacitor C the voltage at the base of the locked output transistor T1increases. When the voltage on the base Dostoyanie transistor turns on, the voltage at its collector drops and the formation of the output pulse ends. The duration of the output pulse, as in the device - the first analogue, is determined by the equality o=I+ = + . The value obtained expansion is defined aso=R1Cln(1+E1/E).

Your second counterpart of the lower level output voltage low (on the order of +UCAN) that when integrating with other pulse and logic devices makes it more comfortable than the device - the first analogue. However, the device is the second analogue also has significant drawbacks:

a) the necessity of using two different supply voltages. The introduction of a second (negative) supply voltage, in some cases, can significantly complicate the construction of the system power extender;

b) the impossibility of an electronic control or electronic set extensionsI.

It is also known device (ed. St. USSR N 1243110: Valuable K. M., Naydenov centuries, the Shaper pulse duration, class H 03 K, 5/04, BI N 25, 1986, S. 250). This device will be seen as a device of the prototype in relation to the proposed.

The device is about the input element OR bitwise NOT connected to the outputs of discharges subtractive pulse counter. The last input of logic element OR IS NOT connected to the enable input setup subtractive pulse counter and to the input terminal of the device. Information subtractive inputs pulse counter connected bitwise with terminals for supplying a control code to adjust the duration. The generator output clock pulses is connected to the counting input of subtractive pulse counter, the input set to zero which is connected to the output of the logical element OR NOT and with the output terminal of the device.

The device prototype works as follows.

For its purpose it is the shaper of pulses which are accurate to the repetition period of the clock pulses produced by the generator of clock pulses is constant. The duration of the generated pulse can be installed (or regulated) by using an external parallel code adjustment duration. After turning on the power supply and feed a control code to terminals for supplying a control code elements of the device will be in the following state. In the absence of input pulses at input terminal has a logical zero voltage. The same, Ural branch of the feed control code to adjust the duration for informational inputs subtractive pulse counter, to enroll in the discharge subtractive pulse counter may not. The output of the logical element OR NOT and to output terminal device level is set to logical one output voltage. This level is fed to the input set to zero subtractive pulse counter and keeps a count of the status of the logic zero at the output of its digits. The clock produces clock pulses with a period T0that arrive at the counting input of subtractive counter pulses; however, the switching subtractive pulse counter they do not lead, because subtractive counter is maintained in the reset condition constant voltage logical units on the asynchronous input set to zero for the specified counter. In this state, the device can be as long as you want - until the arrival of trigger pulse at the input terminal of the device.

The starting pulse with an amplitude corresponding to the level of the logical unit, is fed to the input terminal of the device. The duration of its small (it should be sufficient to provide switches in the subtractive pulse counter and a logical element OR NOT, but should not exceed the period following the Oia duration provides the following switch: he comes to the last input of logic element OR NOT and causes a logical zero at the output of the logical element OR NOT. The result of this is formed by the front output pulse on the output terminal of the device and removes the signal of the logical unit with the input set to zero subtractive pulse counter; he indulges on the entrance permit installation of subtractive counter pulses, resulting in information on the information inputs of the specified counter, will be recorded in its digits.

After a short input pulse clock pulses from the generator output clock pulses to the counting input of subtractive counter pulse, begin to cause switching of the bits of the counter. With the arrival of the next clock pulse, the information recorded in the discharge subtractive counter is decremented by one. When the switching discharges subtractive counter pulse voltage at the output of each of the discharge of this counter will be exactly logical zero, the output of the element OR NOT and to output terminal device, a signal will appear as a logical unit. The formation of the output pulse on the output terminal is determined by the equalityIkT0where k is the number of clock pulses counted subtractive counter pulses until it is reset. After the end of sformirovann the th subtractive counter in the state, the corresponding logical zero at the output of all its digits. In this state, the device will be kept until the arrival of the next trigger pulse. Since his arrival processes switching device prototype again. To change the duration of the generated pulse code should be changed to the terminals for supplying a control code to adjust the duration. In this case, the input pulse in the discharge pulse counter will register a different number k of clock pulses counted subtractive counter pulses until it is reset.

The device prototype has a number of disadvantages. The first is the difficulty of performing logical element OR NOT, provides the devices of the prototype for a given logic. Due to the lack of following. The duration of the generated pulse is maintained at a specified level of accuracy repetition period of the clock pulses T0. If the accuracy of maintaining the specified duration value should be high, you will need a multi-bit counter, and hence the logical element OR NOT with a large number of inputs (number of inputs must be always equal to the number of digits wuchenich series integrated trace elements does not exist. To implement logical element OR NOT with a large number of inputs have to use extenders or collect logical elements OR set of elements OR with a small number of inputs, which increases its size and the number of intermediate connections.

The second disadvantage is the possibility to use when building for the device to prototype a limited number of varieties subtractive counter - essentially, you can only use subtractive counter with parallel transfer. In other types of counters due to the phenomena of "cars" switching places there may be situations where the output of one bit was set to a logical zero, and the output of the next discharge, which was to establish a logical unit, this is the voltage due to the effects of lag, not yet established. In this case, the possible short-term (the so-called "needle") sets logical zeros, which can lead to malfunction of the device.

The third drawback of the prototype is the variability of the value of the expansion pulse. As noted, the input pulse device is a short pulse with durationoless PE is determined by the ratioIkT0. Then the magnitude of expansion =o-Ifor different values ofoit turns out differently:o. . This disadvantage stems from the fact that their purpose device prototype is not an extender pulses of constant expansion, and the shaper pulse of a given durationI=const. Electronic adjustment by means of a control code in the device prototype is subjected too, not the size of the expansion, but in General the duration of the output pulseI.

The problem, which was solved with the creation of the proposed extender rectangular pulses, consists of obtaining a given value of the extension based on the use of integrated digital elements and providing electronic adjustment of the value of the expansion by the impact on the extender control digital code.

The purpose of the invention is the provision of specified values of expansion of the different values of the length of the input pulse and adjusting the value of the expansion using a digital control code.

Additional technical effect of using the proposed scheme extender rectangular pulses with the cops OR NOT the proposed technical solution is possible to apply two-input logic element OR NOT; such items are issued by the industry and for their implementation does not require additional extenders or other additional logic elements, increasing the number of soldered joints in the device).

The essence of the proposed technical solution is the following. It is proposed to use the clock pulses with a period T0the smaller the length of the input pulseI(i.e. to work while ensuring ratio >T0). Then the initial part of the duration of the generated output pulse will be intervalo=I+ =Ioccupying one, two or more periods of the clock pulses T0. Cheating information in subtractive counter that begins after the input pulse is in this case to determine the duration of the output pulse, and the amount of expansion after the end of the pulse input: IkT0andI+kT0. For different values of the length of the input pulse , matching >T0the magnitude of the expansion kT0constant and does not depend on the length of the input pulse. The control code will adjust the amount of expansion . On the last (second) input of logic element OR the transfer. This allows you to perform a logical-OR-NOT as two.

Characteristics of the proposed device are:

the presence in its composition of clock pulses, a logic element OR NOT, subtractive pulse counter;

bitwise communication of information subtractive inputs pulse counter with terminals for supplying a control code to adjust the value of the expansion;

the connection of one input of the logical element OR NOT the input terminal and entrance permit installation of subtractive pulse counter;

the connection of the output of the logical element OR NOT with the output terminal of the device and with the input set to zero subtractive pulse counter;

the connection of the generator output clock pulses with a counter input of subtractive pulse counter;

link the other input of the logical element OR NOT with inverse output transfer subtractive pulse counter.

Characteristics of the proposed device, in common with the device of the prototype are:

the presence in its composition of clock pulses, a logic element OR NOT, subtractive pulse counter;

bitwise communication of information outputs subtractive pulse counter with kimama OR NOT the input terminal and entrance permit installation of subtractive pulse counter;

the connection of the output of the logical element OR NOT with the output terminal of the device and with the input set to zero subtractive pulse counter;

the connection of the generator output clock pulses with a counter input of subtractive pulse counter.

The hallmark of the proposed device is the communication of another logic element OR NOT with inverse output transfer subtractive pulse counter.

You can set the following prichina-effect relationship, while achieving the above technical effect:

the extension value is set as a parallel digital code information levels ("0" and "1" in each category) in the operating temperature range does not depend on the parameters of the elements of the expander and fluctuations of supply voltage, as a consequence, information about the desired value of the extension and expansion in the work process will not be changed;

if you use to control the logical state of the element OR NOT the output signal of the counter, namely, the logical signal transfer, the logical element OR NOT you can perform two-input that will facilitate practical implementation, will reduce the number of soldered joints while maintaining the accuracy of sow; in Fig.2 - graphics stresses in characteristic points of the device of Fig.3 is a circuit diagram of the proposed device.

The proposed device has an input terminal 1, terminal 2 for the signal of the first discharge control code control expansion terminal 3 for the signal of the second discharge control code control extension terminal 4 a signal from the third discharge control code control expansion terminal 5 to signal the last digit control code control extension, the output terminal 6, subtractive pulse counter 7 with the information input of the first digit 8, the information input of the second digit 9, the information input of the third discharge 10, the information input of the last digit 11, entry permit installation 12, the counting input 13, input asynchronously set to zero 14 and inverted output transfer 15, the logical element OR NOT 16, having one input 17, the other input 18 and the outlet 19, the clock 20 with the outlet 21.

Input terminal 1 is connected to the enable input setup 12 subtractive pulse counter 7 and to one input 17 of the logical element OR NOT 16, the other input 18 which is connected with an inverted vyhoda is regulirovki extension connected with the information input 8 of the first discharge subtractive pulse counter 7. Terminal 3 for the signal of the second discharge control code control extension connected with the information input 9 of the second discharge subtractive pulse counter 7. Terminal 4 for the signal of the third discharge control code control extension connected with the information input 10 of the third discharge subtractive pulse counter 7. Terminal 5 to signal the last digit control code control extension connected with the information input 11 of the last category subtractive pulse counter 7. The output terminal 6 is connected to the input asynchronously set to zero 14 subtractive pulse counter 7 and the output 19 of the logical element OR NOT 16. The counting input 13 subtractive pulse counter 7 is connected to the output 21 of the clock 20.

The proposed device operates as follows.

To terminals 1 to 5 for signalling bits of the control code control extension filed managing parallel binary code, the number of bits which is equal to the number of terminals for supplying a control code control extension. This code defines the desired value extensionso. The code from the terminal 2 to 5 for supplying the control is.(Of Fig.1 for definiteness subtractive pulse counter 7 and the control adjustment of the extension is shown a four-digit, the number of digits may be different and the number of digits of fundamental importance when considering the principle of operation of the device does not have). A positive input pulse duration othat exceeds the repetition period of the clock pulses T0, arrives at the input terminal 1, and the specified terminals on the entrance permit installation of 12 subtractive pulse counter 7. Under the action of the input pulse, the information included in the parallel control code control extension, the current at terminals 2 and 5 are written into the ranks of subtractive pulse counter 7. In addition, the input pulse from the input terminal 1 is supplied to one input 17 of the logical element OR NOT 16. The output of this element produces a signal of logical zero, which is passed to the output terminal 6. Begins the formation of the output pulse. The appearance of a logic zero at the output terminal 6 corresponds to the disappearance of the logical unit input asynchronously set to zero 14 subtractive pulse counter 7. With the end of the input pulse at the entrance permit installation of 12 subtractive pulse counter 7 disappears the last signal prohibiting the expense of clock pulses, and work begins subtractive counter empul is one clock pulse recorded in the discharge subtractive pulse counter 7, the count is decremented by one. The signal on the inverted output transfer 15 subtractive pulse counter 7 is equal to a logical unit, and the output terminal 6 is equal to a logical zero. The formation of the output pulse continues.

When with the arrival of the next clock pulse to the counting input 13 subtractive pulse counter 7, the information previously recorded in the counter will be written down to zero, inverted output transfer 15 subtractive pulse counter 7 will be generated signal is a logical zero. At the output 19 of the logical element OR NOT 16 and the output terminal 6 of the device, the signal changes to a logical unit. The formation of the output pulse ends. When this signal is the logical unit from the output 19 of the logical element OR NOT 16 will be asynchronous input set to zero 14 subtractive pulse counter 7 and the voltage at the output discharges subtractive pulse counter 7 is maintained at logic level zero.

During the formation of the duration of the output pulse othe voltage at output terminal 6 corresponds to a logical zero, and outside the intervalIcorresponds to the value of logical units, so we can assume that this device has is italinate input pulse / time and subtracting information from the bits of the counter. Extension Iis determined by the time of writing information in the subtractive counter pulses. It does not depend on the length of the input pulse and at constant engine code on terminals 2 and 5 will also be constant. The extender allows extension of the pulse at constant (at constant engine code) value .

The change of a given extension under the action of a control code, as in other digital devices, is discrete. The magnitude of the value corresponds to one period of clock pulses T0produced at the output 21 of the clock 20. Due to lack of synchronism (in General) after the end of the duration of the input pulse oand receipt of the next clock pulse potential changes in value of the expansionIwithin a discrete time T0. Due to the connection of the input terminal 1 with a single input 17 of the logical element OR NOT 16, the front output pulse at terminal 6 coincides (up to a latency signal in the logical element OR NOT 16) to the front of the input pulse, and checked (within the same value of T0) change the extension of the total duration owill prowl is prohibited experimentally. When experiments were used: counter type IE; logical-OR-NOT type LE; a generator of clock pulses for logic elements series 564 type LE. The clock generator circuit of which is shown in Fig.2, producing pulses with a period T0=5 μs. Control code, coming to the information inputs of the D1- D4counter IE, was taken four-digit. The duration of the input pulses was changed from 6 μs to 50 μs. Control code on the information inputs of the D1- D4counter took a different value (for example, corresponded to the number 7 and number 14). The duration of the input pulseI= 50 μs and a control input corresponding to the number 7, the calculated value ofoshould be in the range from 85 to 90 μs. The measured value was 85 ISS. The duration of the input pulse o=50 μs and the control code corresponding to the number 14, the duration of the output pulse should be within the range of from 120 μs 125 μs. The measured value lengthI120 µs Similar compliance values were observed for other values in the above range. Thus, the experiment fully confirmed functionality of Stroitelei, characterizing the operation of the proposed device.

The extender rectangular pulses, comprising a generator of clock pulses, a logic element OR NOT and subtractive pulse counter, the information input of which is connected with bitwise terminals for supplying a control code to adjust the value of the expansion, the counting input with the output clock, the enable input setup input terminal and one input of logic element OR NOT, the input asynchronously set to zero with the output of logic element OR NOT and with the output terminal, wherein the other input of logic element OR NOT connected with interstim output transfer subtractive pulse counter.

 

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