The sensor of random numbers with a uniform distribution of the increased accuracy

 

(57) Abstract:

The invention relates to computing and can be used in statistical analyses. The aim of the invention is to increase speed and simplification of the sensor, as well as improving the quality of modeling for generating uniformly distributed binary random numbers by equalizing their probabilities. The sensor comprises a generator 1 of rectangular pulses, the first 2 and second 3 counters, register 4, the first 5 and 12 second memory blocks, the first 6 and second 7 groups of XOR elements OR 8 and I, the resistor 9, the button 10. The advantage of the proposed solution in comparison with the known is to increase speed and simplification of the device and improving the quality of modeling uniformly distributed binary random numbers. 1 Il.

The invention relates to computing and can be used in statistical analyses.

Known sensor random equiprobable binary digits [1], containing the random event generator, a trigger, a source of synchronizing pulses, two valves, two delay lines.

The disadvantages of analog I who also is a random equiprobable binary digits [2], containing the random event generator, trigger generator of clock pulses, the EXCLUSIVE OR element, a generator of rectangular pulses.

The disadvantages of this are the counterpart of his narrow features, due to the small width formed on the sensor output code, and low accuracy.

The prototype of the proposed device is a random number generator [3] , comprising a generator of clock pulses, switch, counter, two blocks of memory, accumulating adder-myCitadel, the pseudo-random number generator, the unit of comparison, two elements OR element And the unit element And.

The disadvantages of the prototype are:

the complexity and awkwardness of the scheme due to the large number of items;

poor performance, because of the formation of each binary number is required To iterative cycles of clock pulses;

the lack of quality in modeling when generating uniformly distributed binary random numbers.

The purpose of the invention is to increase speed and simplification of the device and improving the quality of modeling for generating uniformly distributed in a random number generator, contains the generator of rectangular pulses, two blocks of memory, a register, a switch element, And the element OR the first counter, the outputs of which are connected to the input of the first memory block, the output element And is connected to the first input element OR additionally introduced resistor, two groups of XOR and the second counter, the counting input of which is connected to the output of the pulser connected with a counter input of the first counter and to the input of the write register whose output is the output of the sensor, the zero potential bus connected to the first output switch, and the bus unit capacity connected to the first resistor, the second terminals of the resistor and switch are United and connected with the input set to the first counter and the second input member OR the output of which is connected to the input of the second counter, the outputs of which are connected with the input element And the second memory block, the outputs of memory blocks connected to the inputs of the XOR of the first group, the outputs of which output LSB first counter connected to the inputs of the XOR of the second group, the outputs of which are connected to information inputs of the register.

The drawing shows a diagram of the sensor. The sensor comprises a generator 1 of rectangular pulses (GPI), the output of which is connected to the clock inputs of the first 2 and second 3 counters, and also with the input of the write register 4, the information output which is the output of the sensor, the output of the first counter 2 is connected to the input of the first memory block 5 (BP), the output of which is connected with the first inputs of the first group of 6 XOR, the outputs of which are connected with the first inputs of the second group 7 XOR, the second inputs are combined and connected to the low order output of the first counter 2, and outputs connected to the information input of the register 4, the input to the zero of the first counter 2 is combined with the second input of the OR element 8 and is connected through a resistor 9 to the bus unit capacity, as well as through the switch 10 is connected with the bus zero potential, the output element OR 8 soy is the second BP 12, the output of which is connected with the second inputs of the first group of 6 XOR, the output element And 11 connected to the first input element, OR 8.

The sensor uses a binary counters 2 and 3, for example, 8-bit. In blocks 5 and 12 of the memory pre-recorded multibit binary number, for example, 8-bit, distributed according to the uniform law. In this implementation element And 11 has 8 inputs.

The sensor operates as follows.

When the switch contacts open 10 to the inputs of the zero of the counters 2 and 3 receive a single voltage, which leads to their installation in the zero state. Output code counters 2 and 3 are applied, respectively, to the inputs BP 5 and 12 as a result, their outputs appear binary 8-bit number stored in the cell with address 00000000. These numbers are applied, respectively, to first and second inputs of the first group of 6 XOR. The output is a binary 8-bit number, resulting as a result of the addition modulo two two filed with the outputs of blocks 5 and 12 numbers. This result is passed to the second group 7 elements EXCLUSIVE OR on the input of the register 4 unchanged, Oskolkova pulse output GPI 1 the result of the sum output group 7 XOR is recorded in the register 4. As a result, in the first step of the sensor output appears in a number equal to the sum modulo two of two multi-digit numbers stored in cells PSU 5 and 12 with address 00000000.

On the trailing edge of the first pulse from the output GPI 1 the contents of the counters 2 and 3 becomes equal to 00000001. However, the first and second inputs of the group 6 elements EXCLUSIVE OR put, respectively, the number stored in the cells PSU 5 and 12 with the address 00000001. However, now the sum of these numbers modulo two, appearing on the outputs of the first group of 6 XOR, invert the second group 7 XOR, because their second inputs are applied to a single voltage LSB output of counter 2. This inverted code amount is recorded in the register 4 on the leading edge of the next pulse from the output GPI 1.

In the following cycles of operation of the transducer at its output alternately appear: 1) the value of the sum modulo two numbers of cells PSU 5 and 12 with the address 00000010; 2) the inverted value of the sum modulo two numbers of cells PSU 5 and 12 with the address 00000011 etc.

After the end of the 255-th quantum GPI 1 the contents of the counters 2 and 3 becomes equal to 11111111, output BP 5 appears the number stored in the last cell is output also appears isolated voltage, which, passing through the element OR 8, clears the contents of the counter 3. In the 256-th stage output PSU 12 is the number stored in the first cell with address 00000000. The sensor output appears inverted result of the sum modulo two numbers that are stored, respectively, in the first cell PSU 12 and in the last cell PSU 5.

257-m quantum code counter 2 becomes equal to 00000000, and the code counter 3 - 00000001. The sensor output appears non-inverted result of the sum modulo two numbers stored in the first cell BP 5 address 00000000 and in the second cell BP 12 address 00000001, etc.

Thus, through careful mixing numbers from BP 5 and 12 (by sequential addition modulo two with a pinch of cell addresses, BP 12 per unit time through the loop counter 3, and inverting the amount in each even cycle of operation of the counter 2) at the output of the sensor is formed by a sequence of uniformly distributed random binary numbers. This sequence is equal to the product of the sequences stored in the PSU 5 (256), BP 12 (255) numbers, given that they are mutually Prime numbers.

The advantages of the proposed solution compared to known the simulation when generating uniformly distributed binary random numbers by equalizing their probabilities. Diagram of the sensor can easily be implemented on a common integrated circuits domestic production. In particular, the blocks 5 and 12 of the memory can be performed as a permanent storage device or memory storage device; in another embodiment, the sensor elements 2 and 5 can be implemented on the first chip microcomputer (for example, a series of 1816), and the group of items 3, 8, 11, 12 on the second on-chip microcomputers.

The sensor of random numbers with a uniform distribution, comprising a generator of rectangular pulses, two blocks of memory, a register, a switch element, And the element OR the first counter whose outputs are connected to the input of the first memory block, the output element And is connected to the first input of the OR element, characterized in that it introduced the resistor, two groups of XOR and the second counter, the counting input of which is connected to the output of the pulser connected to the counting input of the first counter and the input of the write register whose output is the output of the sensor, bus reference potential connected to the first output of the switch and the bus unit capacity connected to the first resistor, the second conclusions reticle, the output of which is connected to the input of the second counter whose outputs are connected to inputs of the element And the second memory block, the outputs of the memory blocks are connected to the inputs of the XOR of the first group, the outputs of which output LSB first counter connected to the inputs of the XOR of the second group, the outputs of which are connected to information inputs of the register.

 

Same patents:

The invention relates to computing and can be used in statistical analyses

The invention relates to computer technology and can be used in testing and monitoring equipment

The invention relates to computer technology and can be used for building sets blocks stochastic computing machines

The invention relates to computing, and in particular to devices simulating random processes, and can be used in systems with complex signals

The invention relates to computing and can be used to generate a selective sampling of random variables

The invention relates to computing and can be used in mathematical modeling

The invention relates to the field of computer engineering and can be used for solving problems of statistical modeling

The random process // 2050585
The invention relates to computer technology and can be used to generate random processes with specified values cumulants first, second and third order and adjustable value cumulant fourth order

The invention relates to computer technology and can be used for statistical modeling

FIELD: cryptography.

SUBSTANCE: method includes generating random numbers with use of displacement register with check connection, elementary digit of which is a q-based symbol (q=2l, l - binary symbol length) at length of q-based digits register, in check connection networks nonlinear two-parameter operations on q-based symbols F (ub, ud) are used, on basis of random replacement tables, for generating next random number values z1=F(ui, uj), z2=F(ut, um), zg=F(z1, z2) are calculated, where ui, uj, ut, um - values of filling of respective register digits, value of result in check connection networks zg is recorded to g digit of displacement register and is a next result of random numbers generation, after which displacement of register contents for one q-based digit is performed.

EFFECT: higher speed and efficiency.

3 cl

FIELD: computer science.

SUBSTANCE: device has random numbers source, N-digit selector-multiplexer, RAM, ranges control block, generations number control block, J-input OR element, AND elements block. Because series of given values of data set is broken in ranges and frequency of their appearance is set within certain limits, random series is generated with distribution law, presented in form of ranges.

EFFECT: broader functional capabilities.

3 cl, 7 dwg

FIELD: engineering of pseudo-noise series generators with arbitrary number of bits, while said number of bits is transferred in parallel manner during each clock pulse.

SUBSTANCE: beginning values of states are loaded in registers of parallel pseudo-noise generator, which immediately generates following n bits of pseudo-noise series, where n - arbitrary number, depending on required productiveness level. Then, first sub-portion of pseudo-noise generator in accordance to invention receives current state of pseudo-noise generator and outputs state of n bits pseudo-noise generator in the future.

EFFECT: increased speed of operation, realization of parallel processing for capturing and demodulating processes.

3 cl, 9 dwg

FIELD: computer science.

SUBSTANCE: generator has set-point generator 1, generator 2 of exponential voltage, generator 3 of evenly distributed random numbers, digital-analog converter 4, elements OR 5,6, block 7 for comparison, device for pulse generation 8, forbidding element 9, trigger 10, multiplication block 11, input 12 and output 13 of device. Requests stream is formed of elementary stream by excluding one request with preservation of second request, i.e. at output 13 of generator through temporal ranges, distributed in accordance to Erlang law of second order, pulses are generated, modeling receipt of requests.

EFFECT: decreased hardware costs.

1 dwg

FIELD: computer science, possible use in imitators of random processes, and also in specialized and universal computing machines.

SUBSTANCE: device has random number sensor, clock impulse generator, stepped voltage generator, comparison block, counter, decoder, trigger, impulse generator, memory blocks, delay elements, AND elements, multiplexer, adder, block for setting source data, block of adders, block of subtracters, block of amplitude discriminators, code-amplitude transformer, blocks of elements AND, elements OR.

EFFECT: expanded functional capabilities of device.

1 dwg

FIELD: computer engineering; cryptographic systems.

SUBSTANCE: method is based on entropy valuation calculation and writing of mixed packed data into corresponding cells in different memory block areas. On the basis of written data new initial value is formed. Device for initial value of pseudorandom value generator forming contains data source analysis and current entropy valuation calculation means, data package means, data mix means, data accumulation and entropy valuation forming means, new initial value forming means.

EFFECT: method and device provide the capability of initial values forming, which provide dynamic source speed valuation, classification of sources by fast and slow, reliable and unreliable, and also forming of initial values taking into account speed characteristics of sources and reliability of these sources.

10 cl, 2 dwg

FIELD: engineering of methods for cryptographic transformation of data, possible use in communication, computer and informational systems for cryptographic encryption of information and computation of numbers close to random.

SUBSTANCE: device contains two memory blocks, current time moment timer, two concatenation blocks, two hash-function computation blocks, operation block, computing block.

EFFECT: increased complexity of encryption analysis and decreased probability of reliable prediction of next values of pseudo-random series bits while increasing operation speed of generator.

1 dwg

FIELD: computer engineering, possible use for producing a random series of a given set of data with required characteristics.

SUBSTANCE: device contains selector-multiplexer (1), random-access memory device (2), supply of random numbers (3), K P-bit registers (4), where K≥2 and P≥2, K comparison blocks (5), priority encoder (6) and N, where N≥1, inverters (7).

EFFECT: increased trustworthiness of generated series of values due to ensured dependence of value selection only on probability of occurrence of that value set by distribution law.

2 dwg, 2 cl

FIELD: information technology.

SUBSTANCE: invention refers to the computer science, cryptographic encoding and discrete information transfer and can be used for creation of pseudorandom sequences generators. The device consists of the timing pulse generator, control and adjustment unit and series of uniform cells with corresponding relations.

EFFECT: enhancement of functional possibilities of the device and realisation of program change of generator's structure during the working process.

2 dwg

FIELD: information technology.

SUBSTANCE: invention refers to methods and systems of data protection from unauthorised actions, changing of the content during data transfer and storage and can be used for quick generating of random numbers required for ciphering, creation of digital signature, authentication protocols etc. It is assumed to use the random number generator containing source of low intensity elementary particles, receiver containing particle detector and an events storage unit that allows obtaining instant analogue value of quantum events intensity proportional to the number of registered particles; analog-to-digital coder and a scheme equalising statistical properties of the obtained data stream and also generator setting measuring frequency and connected with the analog-to-digital coder. Thereby the simultaneous quantum process is used as a source of low-intensity elementary particles.

EFFECT: increase of random numbers generation speed while saving their properties comparing with other known methods and devices.

1 dwg

Up!