Storage device

 

(57) Abstract:

The invention relates to electronics and is intended for use in a synchronous random access memory devices. Its aim is to increase the noise immunity of the storage device in the write mode in violation of the simultaneity shift signals on the address and information inputs 5, 6 and 7. The problem is solved by addition of each of the decoders 3 and 4 sample columns one input of the ban and their connection to the input 8 of the synchronization device, which ensures the locking of the outputs of the decoders 3 and 4 during the installation of the input signals address, data, and this eliminates the possibility of false entries. The diagram of the storage device also marked the memory elements 1, 2 inputs of the sampling device and the input D-flip-9. 1 Il.

The invention relates to electronics and is intended for use in a synchronous random access memory devices.

Known synchronous random access memory, see, for example, Ignatiev, S. M. Nikolaenko, A. C. Savenkov Century. N. Dual-port RAM memory type CCV with greater functionality. Electronic industry. 1993, vol. 3, S. 48 52, Fig. 1, in part to the effects on choose to write the memory elements. The starting signal for shapers is the decline in the clock, the locking state of the input triggers writing addresses and data.

The disadvantage of such devices is that the temporary positions of recording pulses that are optimal from the point of view of speed and reliability of operation in the recording mode, should provide the pulse shaper. This greatly complicates the electrical circuit and complicates the design.

To address this lack allows use in a synchronous memory device schema entries are made in accordance with [2] In this storage device, the information signal recording selectively received in the memory elements via the decoders sample columns similarly, the address signals, which ensures the necessary coincidence of the beginning of the recording with the completion of the sampling and recording was completed with the beginning of the sample to another address. This device is the technical nature of most closely to this invention.

The closest analogue contains a matrix of memory elements 1, the first 3 and second 4 decoders sample columns. The inputs of the memory elements 1 constituting a row of the matrix are the inputs 7 of the sampling device. Inputs p of the e inputs respectively 9 direct and inverse 10 information input device. The outputs of the first 3 and second 4 decoders sample columns respectively connected to the first and second information inputs of columns of the matrix elements 1 memory.

Device-similar works as follows.

In the recording mode information to the input 7 of the sample corresponding to the row containing the desired memory element 1, a signal sample at the same time, through the appropriate address 8 and information 9 and 10 of the input device in the decoders 3 and 4 sample columns receive information and address signals, determining the occurrence of signal recording on an information input column of the matrix containing selected for recording, the memory element 1. As a result, the memory element 1, at the same time belonging to the selected row and column of the matrix is exposed to the joint effect of the signal sample and the information signal and receives the desired state.

The advantage of the described device is the high synchronicity of the early influences on the memory element 1 according to the 8 inputs of the sample and information inputs 9 and 10 while switching the corresponding signals. Synchronicity is achieved through the dissemination of the information signal through the CTA appears at the inputs 9 and 10 and the signal delay of the sample relative to the address inputs 7.

The disadvantage of this device is its low immunity in violation of the simultaneity shift signals, address and data inputs 8, 9 and 10. Advance information signals at the inputs 9 and 10 of the address signals or the penetration of the inputs 7 of false alarms addresses during recording can disrupt stored in the matrix information.

The objective of the invention is to eliminate this disadvantage.

The problem is solved due to the fact that the storage device that contains a matrix of memory elements, the first and second decoders sample columns whose outputs are respectively connected to the direct and inverse information input columns of a matrix of memory elements, one input of the first and second decoders, the selection of columns is connected to inverse and direct information input device, respectively, and the other inputs connected to respective address inputs of the device, decoders sample columns have one entry ban, which is connected to the synchronization input of the device.

The specified implementation of the storage device through the introduction of new features to provide a lock of the outputs of the decoders is th entry.

Distinctive features of the invention, allowing to obtain a new technical result is the addition of each of the decoders sample columns one input of the ban and connect them to the synchronization input of the device.

Conducted patent research confirmed the novelty of the invention, and also showed that in the literature there are no data showing the impact of differences patentable inventions to the achievement of the technical result. Therefore, we must assume that the patented invention meets the criteria of novelty and inventive step.

The drawing shows a structural diagram of a storage device.

The memory device includes a matrix of memory elements 1, the input sample in each row of the matrix are combined and the 2 inputs of the sampling device, the first 3 and second 4 decoders sample columns. As the decoders 3 and 4 samples of columns in the device, you can use a partial decoders with a bit depth n+2, where n is the number of digits code address column of the matrix. Each decoder 3 and 4 employs a quarter of the younger output codes with zero to 2n-1. Thus, the presence of logical units on at least Oleniy operation PROHIBITION. Inputs 20, 21, 22, 2n-1the decoders 3 and 4 sample columns are address inputs 5 devices, and additional inputs 2naccordingly inverse 6 and 7 direct information input device. Inputs 2n+1the decoders 3 and 4 are connected to the input 8 of the synchronization device. The outputs of the decoders 3 and 4 sample columns respectively connected to the direct and inverse information input column of the matrix elements 1 memory. At the outputs 5, 6 and 7, a synchronous memory device set D-flip-9, state clock inputs of which are connected to the input 8 of the synchronization device and the information input D receives the appropriate bits A0An-1the address code and the input data, and D.

The device operates as follows.

Perform each act of writing the data into the specific memory element 1 begins with the switching of the logic signal at the input 8 from level zero to level one. When the trigger 9 is able to accept the condition, the appropriate logic signals to the inputs D and determining the recorded data and the address column of the matrix containing the memory element 1. All outputs desireto the first memory element 1 and it goes into storage mode. Then the level at the input 8 goes to zero, the locking state of the trigger 9 and lifts the ban from the outputs of the decoders 3 and 4. At the same time to the input 2 of the sample corresponding to the row that contains a writable memory element 1, a signal sample. Element 1 memory belonging to the selected row and column of the matrix and at the same time receiving the impact of signal sampling and informational influence, acquires the desired state.

To read the information at the beginning of the acts of appeals for informational inputs 6 and 7 do logical zeros, which leads to the formation of signals of individual level information inputs selectable column belonging to him the memory element 1, the receive signal sample input 2, is in the reading mode.

High interference immunity of the storage device is achieved by providing a lock information impact on the memory elements 1 from the outputs of the decoders 3 and 4 sample columns during installation of input signals address and data. Necessary to avoid false write-ahead signal sampling signal recording is provided by predustanovit signals address and data at the outputs 5, 6 and memory.

A storage device containing a matrix of memory elements, the first and second decoders sample columns whose outputs are respectively connected to the direct and inverse information input columns of a matrix of memory elements, one input of the first and second decoders, the selection of columns is connected to inverse and direct information input device, respectively, and the other inputs connected to respective address inputs of the device, characterized in that the decoders sample columns have one entry ban, which is connected to the synchronization input of the device.

 

Same patents:

The invention relates to a semiconductor device crash survivable memory and method of programming, more precisely to erasable and electrically programmable read-only memory having a cell in the form of structures AND IS NOT, and how, enabling optimized programming data using the above ROM

The invention relates to the field of computer engineering and can be used as a buffer storage device in the system of collecting and processing information

Programmer // 2078381
The invention relates to computing and can be used to control and record the information in field-programmable gate arrays, including permanent and reprogrammable storage device

The invention relates to a storage device of a dynamic type, made in the form of large-scale integrated circuits, and can be used in modern computers and memory devices

The invention relates to automatic control and computer engineering, in particular to a device write binary information into permanent memory chip with ultraviolet erasing and fused jumper

The invention relates to computer technology and can be used in computer systems special purpose exposed during operation to physical fields of high and variable intensity

The invention relates to computer technology and can be used for data recovery in the semiconductor dynamic memory devices included in a specialized computers which are exposed during operation to physical fields of high intensity

FIELD: digital memory technologies.

SUBSTANCE: board has rewritable power-independent memory and control circuit, means for storing address, pointing at limit between authentication area and non-authentication area, circuit for changing size of said areas. Reading device contains estimation means, reading information, pointing at number of times, for which digital data can be read, and playback means. Second device variant additionally has means for digital output of contents.

EFFECT: higher efficiency.

3 cl, 23 dwg

FIELD: computer science.

SUBSTANCE: editing is performed for data files, which are segmented on blocks, each of which has known data length, and to which attribute file is added, having known length, while segmented blocks are recorded on energy independent memory device., method includes selecting two files of data, recorded in data area for their combination, attribute file is separated from the last data file from selected two; control data are edited recorded in control area by setting a logical link between two data files, and attribute file added to first placed file is edited; and edited control data are recorded to control area, and attribute file - to data area.

EFFECT: broader functional capabilities.

4 cl, 5 dwg

FIELD: data carriers.

SUBSTANCE: device for reproduction of data from data carrier, program zone of which is used for recording a set of files, and control zone - for controlling copy protection data concerning the file, recorded in program zone, has computer for calculating copy protection information for each time file is reproduced, comparison means for comparing value, calculated on reproduction command, being prior to current one, to value, calculated on current reproduction command, and if these values coincide, the last value is stored as copy protection value, calculated on reproduction command , prior to current one and control means for allowing reproduction of file, appropriate for current command, if value, calculated as response to command, previous relatively to current command, coincides as a result of comparison to value, calculated as a response to current command.

EFFECT: higher reliability, higher efficiency.

4 cl, 46 dwg

FIELD: data carriers.

SUBSTANCE: device for reproduction of data from data carrier, program zone of which is used for recording a set of files, and control zone - for controlling copy protection data concerning the file, recorded in program zone, has computer for calculating copy protection information for each time file is reproduced, comparison means for comparing value, calculated on reproduction command, being prior to current one, to value, calculated on current reproduction command, and if these values coincide, the last value is stored as copy protection value, calculated on reproduction command , prior to current one and control means for allowing reproduction of file, appropriate for current command, if value, calculated as response to command, previous relatively to current command, coincides as a result of comparison to value, calculated as a response to current command.

EFFECT: higher reliability, higher efficiency.

4 cl, 46 dwg

FIELD: data carriers.

SUBSTANCE: board has protected area, wherein a series of encoding keys is stored, unprotected area, wherein at least one sound record is stored and control information. Reproduction device has reading means, decoding means and reproduction means. Recording device has encoding means and recording means. Methods describe operation of said devices. Data carriers contain software, which reflects operations of said methods.

EFFECT: broader functional capabilities.

10 cl, 109 dwg

FIELD: electric engineering.

SUBSTANCE: semiconductor memory board has protected area, unprotected area, while board stores sound sequence, multiple objects in form of fixed images, at least one fragment of information about reproduction route, and at least one fragment of information about first and second pointers. Reproduction device has reproduction means, visual display means, control means. Recording device has assignment means and recording means. Methods describe operation of said devices. Data carrier has recorded software, providing reproduction procedure for said board.

EFFECT: broader functional capabilities.

7 cl, 148 dwg

FIELD: electric engineering.

SUBSTANCE: device has frequency filter, voltage amplitude limiter and two comparators, each of which includes differential cascade, two power sources, emitter repeater and voltage divider.

EFFECT: simplified construction, higher precision, higher reliability.

2 dwg

FIELD: data carriers.

SUBSTANCE: device for determining logical state of selected memory cells in memory device with passive matrix addressing is made with possible connection to ferroelectric memory device or forming its portion and contains reading amplifying contours, synchronous amplifier, combined source of shift voltage and signal, active control line driver, multiplexer, a set of routers. Other variant of aforementioned device is additionally equipped with second set of routers. Method describes operation of aforementioned devices.

EFFECT: higher efficiency, broader functional capabilities.

3 cl, 12 dwg

FIELD: editing of records.

SUBSTANCE: device is used for separation of data file with main and control data on first file and second file. Device has operation means for determining a point of division on first and second files; editing means for editing first control data, to render ineffective first portion of block of recorded data of fixed length with main data; and means for generating second control data, to render ineffective second portion of block of recorded data of fixed length with main data, and for adding second control data to second data file.

EFFECT: higher efficiency.

3 cl, 46 dwg

FIELD: technology for manufacturing plastic cards with chip (cards with inbuilt micro-circuit).

SUBSTANCE: method includes performing cycles of operations, consisting of loading command by external device into buffer of chip-card, execution of command by chip-card and return of message about result of command execution by chip card to external device. Prior to operation of loading by external device, block of commands is formed, containing administrative command, in which as data several commands fed onto card are used, aforementioned commands block is executed and message about result of execution of command block is returned to external device. Number of commands in block is supposed to be maximal possible to decreased exchange cycles and it determined by length of commands, size of command buffer, maximally allowed length of data in used transfer protocol.

EFFECT: when used in plastic cards with chip on basis of microprocessor, for example, in SIM-cards, leads to increased speed (decreased consumed time) of card initialization.

6 cl, 2 dwg

Up!