The pulse shaper write random access memory

 

(57) Abstract:

The invention relates to electronics, and is intended for use in integrated circuit memory devices, the object of the invention is the achievement of structural conditionality for the duration of the generated pulse recording the actual processes of switching memory elements and the propagation of signals in the record path information storage device. This is achieved by the execution of line 3 delay, which determines the duration of the generated pulses, in the form of a Daisy chain of equivalent 7 record path information storage device and item 8 of the memory is identical to the element information storage. In addition to these elements on the diagram of the device indicated by the first and second D-flip 1 and 2, the XOR element 4, the output 5 of the generated pulses and the input 6 of the clock signals. 2 Il.

The invention relates to electronics, and is intended for use in integrated circuit memory devices.

Known memory devices [1] to work in the recording mode information to the corresponding inputs must be applied pulses tasapainoa devices. This leads to the complication of time-series of chips, which hinders their use in equipment with a maximum frequency of reference.

This lack of RAM is completely eliminated by the introduction into the composition of the shaper pulse recording, managed, for example, an external clock signal, the clock input circuit. Generated inside the memory device, the recording pulses have the necessary for the normal operation time characteristics defined by the design parameters of chip elements defined in the design.

This driver can be used the known device [2] the technical nature of this device is the closest to this invention.

The closest analogue contains the first D-flip-flop with inverted input D data, the second D-flip-flop with inverted input C synchronization, the delay line and the EXCLUSIVE OR element. The output of the first D-flip-flop connected to the input D of the second D-flip-flop, the output of which is connected to the input of the delay line, the input D of the first D-flip-flop and the first input of the EXCLUSIVE OR element, the second input is connected to the D which triggers are combined and input clock signals.

This shaper pulses is as follows.

When the switching signal on the clock input signal from the zero level to the unit level corresponding to the leading edge of the clock pulse, the D-flip-flop is set to be opposite to commit at this point in the second D-trigger. On the trailing edge of the clock pulse corresponding to the switching clock signal from level one to level zero, the first D-flip-flop goes into storage mode, and the second D-flip-flop switches to the opposite state. The front of the output signal of the second D-flip-flop is supplied to the first input of the EXCLUSIVE OR element, at this time on its second input, due to the action of the delay line, the previous level. The difference between logic levels at the inputs of the EXCLUSIVE OR element switches its output level from zero to one, which corresponds to the leading edge of the generated pulse recording. The unit level at the output of the shaper is maintained during the time required for passing through the delay line front signal output from the second D-flip-flop. After a time delay to the second input of the EXCLUSIVE OR element fixed at the same level, the and output the generated pulses.

The disadvantage of the described device is the lack of structural conditionality for the duration of the generated pulse recording the actual processes of switching memory elements and the propagation of signals in the record path information, the length of which changes when exposed to various manufacturing and operational factors. This makes it difficult to achieve when designing optimal pulse duration recording, while providing maximum performance and sufficient reliability of operation of the storage device in the recording mode information.

The objective of the invention is to eliminate this disadvantage.

The problem is solved in that in the pulse shaper write random access memory containing a delay line that defines the duration of the generated pulses, the delay line consists of the equivalent of the record path information storage device and the memory element is identical to the element drive information storage device, the equivalent is the input of the delay line and its output connected to the input recording information memory, the output reading which is CSO storage device through the introduction of new characteristics to achieve equality propagation time of signals in the delay line, defining the duration of the generated pulse recording, real-time required to change the state of the selected memory element under the influence of distributed storage of information signals, and preserve this equality in terms of destabilizing impact due to the structural equivalence of the elements of the delay line and an information storage random access memory.

In comparison with analogues in the device for the first time used the equivalent of the record path information and the memory element random access memory device comprising a delay line that allows you to obtain a new technical result.

Conducted patent research confirmed the novelty of the invention, and also showed that in the literature there are no data showing the impact of differences patentable inventions to the achievement of the technical result. Therefore, we must assume that the patented invention meets the criteria of novelty and inventive step.

In Fig. 1 shows a block diagram of a variant of implementation of the pulse shaper write random access memory device of Fig. 2 is an example schematic of apoapse random access memory device includes a first D-flip-flop 1 with inversion on the data input D, the second D-flip-flop 2 with inversion at the input C of the synchronization, the delay line 3 and the XOR element 4 has an output 5 of the generated pulses and the input 6 of the clock signals. Line 3 delay consists of the equivalent of 7 record path information storage device and item 8 of the memory is identical to the element drive information storage device. The output of D-flip-flop 1 is connected to the data input D of D-flip-flop 2, the output of which is connected to the input of the equivalent of 7 record path information storage device, the data input D of D-flip-flop 1 and the first input of the XOR element 4, the second input is connected to the output of the read element 8 memory, and the output is the output 5 of the generated pulses. Output equivalent 7 is connected to the input recording information element 8 memory. Inputs C sync D-flip-flops 1 and 2 are combined and the entrance 6 of the clock signals.

The pulse shaper operates as follows.

When switching the input signal 6 from the zero level to the unit level corresponding to the leading edge of the clock pulse, the D-flip-flop 1 is set in the condition opposite to the condition fixed at this point in the D-trigger 2. On the trailing edge of the clock pulse, with storage, and D-flip-flop 2 is switched to the opposite state. The front of the output signal of D-flip-flop 2 is supplied to the first input of the XOR element 4, at this time on its second input, due to the action of the delay line 3, the previous level. The difference between logic levels at the inputs of the XOR element 4 switches the output level of zero in the unit, which corresponds to the leading edge generated at the output 5 pulse recording. The unit level at the output 5 of the shaper is maintained during the time required for passing through the equivalent of 7 record path information storage device and the switching element 8 memory in an opposite condition. After this time the second input of the XOR element 4 is set to the same level as at its first input, and the output signal 5 switches to a logical zero, forming the rear edge of the pulse recording.

During the whole time presence at the output level 5 logical unit memory random access memory device will be under the influence of the information signal recording, the duration of which is sufficient for distribution and is standing. Due to the structural equivalence of the elements 7 and 8 of the delay line 3 to the corresponding elements of the drive information storage device is achieved equality propagation time of signals in the delay line 3, which determines the duration of the generated pulse recording, real time recording information in terms of the destabilizing effects of various manufacturing and operational factors, and what is the technical result of the invention.

The invention can be used in memory devices containing the memory described in U.S. patent N 3.675.218, NPK 340/173 FF, published. 1972

In this example (Fig. 2), item 8 memory comprises first and second key of the transistors 9 and 10, connected by two cross-connected base - collector, first and second load resistors 11, 12, the first conclusions of which is connected to the bus 13 of the first bias voltage, and the latter conclusions are respectively connected to the collectors of the first and second key of the transistors 9 and 10, the source 14 of the current storage, the first output of which is connected to the first power bus 15, and a second output connected to the emitters transistorise key transistors 9, 10 accordingly, the base connected to the bus 18 of the second bias voltage, and the emitters form a two-rail input recording information element 8 memory.

The equivalent of 7 record path comprises first and second transistors 19, 20 control, first and second springs 21, 22 of the write current, the first conclusions which are connected with the first power bus 15, and the latter conclusions are respectively connected to the emitters of the transistors 19, 20 are two-rail output equivalent to 7, the bases of transistors 19, 20 are two-rail input equivalent 7, the first and second load transistors 23 and 24, the base of which is connected to the bus 25 of the third bias voltage, and collectors together with the collectors of the transistors 19, 20 are connected with the second bus 28 power first and second load capacitors 26, 27, the first conclusions of which is connected to the bus 28, and the latter conclusions are respectively connected to the emitters of the transistors 19, 23 and to the emitters of transistors 20, 24.

Line 3 delay consisting of elements 7 and 8 described configuration operates as follows.

The voltage level on the bus 13 is equal to the level of a bias voltage in the drive information storage device, and the levels of the tires 18 and 25 respectively from the bound to the bases of transistors 19 and 20, compared with the level on the bus 18 in the emitter connected pairs of transistors 19 and 23, 20 and 24, as the high and low levels at the bases of transistors 19 and 20 are respectively above and below the level of the tires 18 and exceed the voltage level on the bus 25.

If the input equivalent 7 receives a logical unit, a high potential is established on the base of the transistor 19 and to the base of transistor 20 is low. In this case, the current source 21 flows through the transistor 19 in the rail 28, and a current source 22 through the transistor 17 and resistor 12 in the tire 13. Thanks trigger relations transistors 9, 10 in the resistor 12 in addition to the current source 22 flows to the current source 14 and the voltage across the resistor 12 exceeds the voltage across the resistor 11. Consequently, the collector potential of the transistor 10 is lower than the collector potential of the transistor 9, which corresponds to a logical unit on the output element 8.

When the ratio is changed logic levels at the inputs of the equivalent of 7, causing the decrease of the base potential of the transistor 19, the current source 21 is disconnected from the emitter of the transistor 19 and produces the discharge capacities of the capacitor 26 and the emitter p-n junction of the transistor 23 as long as the potential on the emitter of transistor 16 is not ponicki in the emitter of the transistor 20 by reason of the increase of the potential on its base, charges the capacitor 27 and the emitter p-n junction of the transistor 24, thereby increasing the potential of the emitter of the transistor 17 to complete the switching of the current source 22 of the transistor 17 in the transistor 20.

At least turn off the current source 22 of the resistor 12 and enable the current source 21 to the resistor 11, there is a change in the difference of the collector potentials of the transistors 9 and 10. The approach of this difference to zero causes a redistribution of the current source 14 from the emitter of transistor 10 more branches in the emitter of the transistor 9 and when the collector potential of the transistor 9 becomes lower than the potential at the collector of transistor 10, the trigger connection of transistors 9 and 10 cause an avalanche switching remainder of the current source 14 to the emitter of the transistor 9, completing the process of forming the logic zero at the output of the element 8.

Because of the symmetry of the circuit 3 delays the reverse process of switching from zero in the unit is similar in mutual change of actions performed in pairs of functionally identical elements.

To achieve the equivalence of the process of logical signals in lines 3 delays the process of changing the state of the selected ele is information you should perform identical similar in function to the components of the drive mass storage device, the current source 14 should be equal to a current storage occurring in a selected element of the drive, the emitters of transistors 23 and 24 is equivalent to the combined emitters of transistors record unselected elements of the drive, having in common with the selected information inputs, and the capacitors 26 and 27 must have a capacity equal to the capacity of current-carrying paths of information tire drive.

Thus, if certain requirements of the solution provides the dependence of the duration of the generated pulse recording a real dynamic processes in the drive information storage device under the influence of various manufacturing and operational destabilizing factors equally affect the parameters of the equivalent components of the drive pulse shaper account.

The pulse shaper write random access memory containing a delay line that defines the duration of the generated pulses, wherein the delay line consists of the equivalent of the record path information storage device and the memory element is identical to the element information storage memorize the information of the memory element, the output reading which is the output of the delay line.

 

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