Semiconductor device crash survivable memory

 

(57) Abstract:

Semiconductor device crash survivable memory refers, in particular, to an erasable and electrically programmable ROM. The device includes a network of memory cells arranged in a matrix having cells AND IS NOT formed by the set of series-connected memory cells, each of which is made by applying a layer of charge accumulation and a control gate on the semiconductor substrate and has the ability to electrical erase through the mutual exchange of charge between the layer of charge accumulation and substrate, the circuit latches data LT, a source of high voltage HV, a diagram of the current source CS, the validation scheme programming PC and the scheme for detecting the state of programming PS. It also uses the buffer pages PB erasable and electrically programmable memory having a function to page mode. 2 C.p. f-crystals, 7 Il.

The invention relates to a semiconductor device crash survivable memory and method of programming, more precisely to erasable and electrically programmable read-only memory having a cell in the form of structures AND IS NOT, and how, enabling optimized programming pokolenia and its equivalent circuit, top view of Fig. 2 conditions of control voltages during read operations and the timing diagram of the control voltage during the operations of erasing and programming erasable and electrically programmable memory having a cell structure AND NOT the first generation.

Operating conditions of the selected cell when erasing and programming in a conventional erasable and electrically programmable memory of the first generation following. First, when erasing by applying voltage erase (17) on the shutter CL 5 of the selected cell CT 5 and OB voltage on the drain of the cell from the drain into the floating gate due to F-N tunneling (Fowler-Nordheim) injections electrons, so that the threshold voltage of the cell becomes positive.

When programming by filing an OB voltage to the gate of the selected cell CT 5 and voltage programming (22V) to its drain through F-N tunneling effect of electrons amitysource from the floating gate to the drain of the cell so that the threshold voltage of the cell becomes negative (see Journal of solid-state circuits Institute of electrical engineers, October 1989, S. 1238 1243). Therefore, erasing and programming on the thin oxide layer to create tone the word write cycles) and data integrity (characteristic of conservation of charge of the floating gate cell. In particular, if the size of the cell is significantly reduced while achieving higher densities and capacities, the above characteristics reliability deteriorates even more.

Fig. 3 (a and b) are schematic views of a cell to illustrate the operation of erasing and programming erasable and electrically programmable memory having a regular cell structure AND NOT the second generation.

In erasable and electrically programmable memory of the second generation when erasing (Fig. 3,a) to the gate CG of the selected cell applied voltage OB and to the substrate SU, the source S and the drain D is the erase voltage (20V), so that the electrons amitysource from the floating gate FG of the cell to the substrate SU, which makes the threshold voltage of the cell is negative. When programming (Fig. 3,b) to gate CG of the selected cell is applied to the programming voltage (18V), and to the substrate SU, the source S and the drain D is OB, so that the electrons injections of the substrate SU in the floating gate FG of the cell, which makes the threshold voltage of the cell is positive. That is, these working conditions the opposite working conditions erasable and electrically programmable memory of the first generation and injection and emitiranje estoc. Therefore, the leakage current through the thin locking oxide layer to create a tunnel effect, which causes a shock when erasing and programming can be reduced, thereby greatly improving the reliability of the cell. In addition, the threshold voltage of the cell during the erase negative and the problem of peristernia is solved (see the Symposium on VLSI technology, 1990, S. 129 and 130).

However, as shown in Fig. 4,and, because of the large voltage changes caused by changes in process parameters during programming of the cell in the erasable and electrically programmable memory of the second generation, the characteristics of the distribution of the threshold voltage of the programmed cell is deteriorating, there is the phenomenon of reprogramming. In other words, even if within a cell chain structures AND erasable and electrically programmable memory reprogrammed only one cell, then don't read the whole chain of cells. Accordingly, in order to maintain optimal conditions programming requires some device to prevent reprogramming.

When, as shown in Fig. 4,b, programming is repeated when testing prog is commonly state programmable data erasable and electrically programmable read-only memory are checked and the external controller validation is re-programming data which performs the algorithm shown in Fig. 5, in order to optimize the programming data. The validation algorithm programming data loads data in page mode and latches the input data. Then after programming clicked data in each cell of a selected range of cell data is read to check the status of the programmed data. When the read data are the same as the expected value, the programming is completed. When the read data is different from the expected values, as shown in Fig. 6, data bits corresponding to the cell programming to "1" which failed, held at "1" and data bits corresponding to the cell in which "1" or "On" zaprogrammirovali normally set to zero. Data processed in this way are re-regulated in page view and adjustable data is re-programmed into each cell of the selected range of cells. After re-programming data is read to verify the programmed state of each cell, so that the program operation ends when the programming is in the normal state. In other words, when prog is I adjusted data is repeated, as described above (see Journal of solid-state circuits Institute of electrical engineers, April 1991, S. 492 496).

However, in accordance with the above-described conventional validation algorithm must re-run the process in which data is programmed by an external controller, read and checked, and then loaded again for re-programming until then, until it is detected normal programmed state of each cell, which degrades the characteristics of the entire system.

The aim of the invention is to provide a semiconductor device crash survivable memory that can automatically optimize the programming data by automatic one-time download of data.

Another objective of the invention is to provide a semiconductor device crash survivable memory, which can prevent the phenomenon of reprogramming data.

Another aim of the invention is to provide an optimal method of programming a semiconductor device crash survivable memory, which can automatically optimize the programming of the data inside the chip.

To achieve these and other goals izobretatel in the form of a matrix, with the cell AND IS NOT formed by the set of series-connected memory cells, each of which is formed by overlaying a layer of charge accumulation and a control gate on a semiconductor substrate, and has the ability to electrical erase through the mutual exchange of charge between the accumulation layer charge and the substrate;

the circuit latches data to ensure program data for bit lines of a network of memory cells;

diagram of the high voltage power supply for supplying predetermined high voltage to the bit line network memory cells in accordance with the state of the data circuit latches data;

a diagram of the current source for applying current to the bit line network memory cells, to confirm the programmed state of the data after programming in the network memory cells;

device test programs to invert the state of the data circuit latches the data in response to flows or not through the memory cell current validation, submitted to bit lines, when the current scan is supplied to the control gate of the memory cell to be tested;

the scheme for detecting the state of the program to generate the signal det is Verka program.

In addition, the invention provides a method for optimal programming of semiconductor devices crash survivable memory, which provides block-page mode in which many chains of cell structure AND IS NOT erased blocks, and the input data, clear the buffer pages are programmed simultaneously in the cell of the selected range of cells containing the steps

check programming, which delivers the control voltage of the scan and the current scan to each cell of the selected range of cells, verifies the programmed state of the data in each cell and converts the data buffer pages, the corresponding additional programmed cell cell having a normally programmed data in response to the verification operation;

re-programming, re-programming the data buffer pages, adjusted the specified validation phase, in each cell of the selected range of cells;

automatically repeating the steps of checking and re-programming up until a corresponding inversion of the data buffer pages will not be fully performed by normal programming data in each of the cells selected linac and a single external input data and without reprogramming.

In Fig. 1 shows a chain of cell structure AND IS NOT the usual erasable and electrically programmable read-only memory of the first generation and its equivalent circuit top view of Fig. 2 the waveform of the voltage supplied during a read operation, the erase and programming chain cell structure AND NOT the first generation; Fig. 3 (a and b) are schematic views for illustrating operations of erasing and programming erasable and electrically programmable ROM of the second generation; Fig. 4 (a and b) graphs depicting the characteristics of the distribution of the threshold voltage of the programmed cell relative to the change in the voltage programming erasable and electrically programmable ROM of the second generation with verification and without it, respectively; Fig. 5 is a block diagram showing the algorithm of the program verification erasable and electrically programmable ROM of the second generation; Fig. 6 programmed state in accordance with the algorithm verification program according to Fig. 5; Fig. 7 is a schematic diagram of a network of cells and detection scheme in erasable and electrically programmable ROM of the second generation in accordance with the invention.

The table shows the voltage EV is time to Fig. 7, which illustrates a network of cells erasable and electrically programmable memory having a cell structure AND IS NOT, and the scheme for detecting the programmed state in accordance with the invention. Each bit line BL1-BL1024 connected with cell structure AND NOT block chain CE, consisting of a selection transistor chain ST, eight cell transistors CT1-CT8 and transistor selection of land GT, which are connected in series. The selection transistor chain ST and the transistor of choice land GT have a MOS structure and their gates respectively connected to the selection lines SL1 and SL2. Each transistor cell CT1 CT8 has emaciated the MOS structure with a floating gate and control substrate, and each shutter control respectively connected to the control lines CL1 CL8. In addition, each bit line BL1 BL1024 connected to the corresponding circuit of high-voltage power source HV for submission to the bit line high voltage programming during programming data corresponding to the latch circuit of a bit line LT, which will be uploaded to the external input circuit of the current source CS for applying current to the test during the test program and the corresponding validation block progrevanie during the test program.

Diagram of high-voltage power source HV is a conventional circuit high voltage pump, which is composed of the transistors PT1 and PT2 and condenser pump C. the Drain of the transistor PT1 is connected to the source voltage Vpp programming, its gate connected to bit line BL1, and its source connected to the gate of the transistor PT2. The drain of the transistor PT2 is connected to its gate and one terminal of the condenser pump C, its source also connected to bit line BL1. When the clock signal ppsupplied to the other terminal of the condenser pump C becomes high, the condenser pump C discharges accumulated in it charges through the transistor PT2 to the bit line BL1, thereby giving the erase voltage (10V) or voltage prohibition programming (10B) on the bit line BL1.

Circuit latches the bit line LT consists of two inverters INV1 and INV2 and the transfer transistor TT1. The inverters INV1 and INV2 are connected so that the input of one inverter is connected to the output of another inverter. The gate of the transfer transistor TT1 is connected with the source clock signal 1, its first current terminal (drain or source) connected to a bit line, and the second current terminal (source or drain) connected to the input of the inverter INV2. Saaku through the transfer transistor TT1, which is unlocked when the high potential of the clock signal 1.

Diagram of the current source CS is formed of multiple output circuits OS, connected to the corresponding bit lines, and the General pattern of the setting of the reference current RC, which are connected to each other by the well known current mirror circuit so as to set the reference current for all output circuits OS. General block setting of the reference current RC is composed of p-channel MOS transistor M1 and n-channel MOS transistors M2 and M3, serially connected between the first voltage source Vcc and the second voltage source Vss (ground). The drain and gate of p-channel MOS transistor M1 are connected to each other. The gate of n-channel MOS transistor M2 is connected to the reference voltage Vref, the gate of n-channel MOS transistor M3 is connected to the source clock signal 2. Every OS is composed of p-channel MOS transistor M4 and the n-channel MOS transistor M5 are connected in series between the first supply voltage Vcc and the corresponding bit line. The gate of p-channel MOS transistor M4 is connected to the gate of p-channel MOS transistor M1 and the gate of n-channel MOS transistor M5 is connected to the source of clock signals the drain of p-channel MOS transistor M4 is supplied to the bit line BL1 as the current test, which is proportional to the current drain of p-channel MOS transistor M1, multiplied by the ratio of the currents of the MOS transistors M1 and M4.

The validation block PC is formed from a MOS transistor M6, the drain of which is connected to the input of the inverter INV1 circuit latches the bit line LT, its source connected to the second voltage source (Vss or ground), and its gate connected to bit line. Thus, when the current test applied to the bit line, flows to the ground through the cell structure AND IS NOT, the potential of the bit line becomes high, the MOS transistor M6 (test program) is activated, which, in turn, lowers the input of the inverter INV1 of the latch circuit LT to a low potential (ground). Therefore, when programming the selected cell is not satisfactory, check the PC checks poor programming, thereby inverting the data circuit latches the bit line LT.

1024 pieces of the above-described cell structure AND NOT the CE form one block, and each block has 8 pages of information, i.e., 8 KB of data. The length of one page is 1024 bits. For example, erasable and electrically programmable memory 4 Mbit includes 512 blocks. This erasable and electrically connected to the bit lines LT is the buffer pages PB.

In Fig. 7 the symbol PS refers to a scheme for detecting the state of programming. A scheme for detecting the state of programming PS shows normal signal detection, when all of the selected cell is programmed optimally, or abnormal signal detection, if unsatisfactory even programmed one any cell. A scheme for detecting the state of programming PS has a p-channel MOS transistor M7, which serves as the device forward bias PU for direct displacement of node N is 1, and depleted MOS transistor M8, which is used as the load forward bias. The source of p-channel MOS transistor M7 is connected to the first source voltage Vcc, its gate connected to the source clock signal 3, and its drain connected to the source of the depleted MOS transistor M8. The gate and drain depleted MOS transistor M8 are connected to each other and also connected to node N1. Between the node N1 and the second source voltage Vss (ground) in parallel includes a number of n-channel MOS transistors PD1 PD1024 serving as a reverse bias PD. The gate of each MOSFET is connected to the inverted output of the corresponding latch circuit of a bit line LT. Node N 1 compounds is-OR G is connected with the source clock signal 4.

Accordingly, when in test mode, all transistors reverse bias PD1 PD1024 locked, a scheme for detecting the state of programming generates the clock signal 5 high potential. Columns CJL2 COL1024 have the same structure as the column COL1.

Operation programming and verify semiconductor device crash survivable memory according to the invention (Fig. 7) will be described with reference to the table.

In order to program the data inside the network cell, at first filled erase operation on the blocks. Here during erasing, when to the control gate of each cell is OB, and to the substrate, the source and the drain is applied to the erase voltage 20V, electrons amitysource from the floating gate of the cell to the substrate, so that the threshold voltage of the cell becomes negative. When erasing is completed, the inputted external data loaded into the latch circuit of a bit line LT. At this point loading at high logic level (Vcc) to load the data "0" (- Vth) and a low logic level (ground level) to load the data "1" (+ Vth). Data is loaded into the latch circuit of a bit line LT, when the clock signal 1 becomes high. If Yes the EMA high-voltage source HV, thereby setting the voltage of a bit line BL 10B, which represents the voltage of the prohibition programming. Therefore, as explained in Fig. 7, since the potential difference between the gate and drain of the transistor of the selected cell CT6 insufficient to cause F-N tunneling effect transistor of the selected cell CT6 perpetuates negative threshold voltage (- Vth).

At the same time, if the data loaded in the latch circuit of a bit line LT represent a low logic level, the circuit of the high voltage source HV is not valid, thereby maintaining the voltage of a bit line on the OB. Thus, since F-N tunneling effect is not excited by the potential difference between the gate and drain of the transistor of the selected cell CT6, electrons injections in the floating gate so that the threshold voltage of the cell becomes positive (+ Vth). However, if the data bit "1" is programmed unsatisfactory, the selected cell CT6 can't get a predefined positive threshold voltage. This operation programming simultaneously performed on pages in page mode. Accordingly, in order to program one block (1024 x 8), runs eight operationa state of the clock signal 2 is the scheme of the current source CS, so to the bit line BL is applied to the current scan. At this time, the control lines CL1 CL5, CL7 and CL8 line SL1 and SL2 and the transistors not selected cells CT1 CT5, CT7 and CT8 voltage Vcc, and the control line CL6 selected number of cells served predetermined voltage test, for example, 0.8 Century Hence, when the threshold voltage of the transistor of the selected cell CT6 negative (data 0), the current scan through the chain of cells is shunted to the ground. Thus, the bit line BL1 maintains its level of OB.

When the threshold voltage of the selected cell is positive (i.e. + Vth > 0, data 1), the bit line BL1 receives a high level, since the current test does not leak through the chain of cells CE. However, if the cell is programmed with data "1" is programmed unsatisfactory, and this means that the threshold voltage of the cell is less than 0.8 V, the current test is shunted to ground, allowing the bit line BL1 still save your level OB.

During this scanning operation, when the bit line of the selected cell in the programmed data "1" maintains a low potential, the transistor M6, which is a screening device programming cannot be unlocked condition of the load remain at the output Q. In addition, since the inverted output of the circuit latches the bit line LT stored data is "1", the reverse bias transistor PD1 circuit detection status programming PD, the gate of which is connected to the output continuously maintained in an open condition. Therefore, the normal programming is not performed, so that the clock signal 5 circuit detection status programming PS is maintained at a low level.

During re-programming, since the data "0" of the latch circuit of a bit line LT again served to the bit line BL1 at a high level of the clock signal 1, the electrons re-injections in the floating gate of the selected cell, which is programmed unsatisfactory. Thus, the threshold voltage of the cell becomes more positive. If the selected cell is unlocked voltage check (+0.8 V) during lifting its threshold voltage to be positive, due to the consistent repetition of the programming operations, checking and re-programming, the potential of the bit line becomes a logic high level, thereby Opera transistor M6. Thus, the data "0" is loaded to the output is recorded in the data "0", so the reverse bias transistor PD1 circuit detection status programming PD is locked. Due to this repeated action, when all bits of the data buffer pages PB, i.e., the inverted output signals of all circuits latches the bit lines are data "0", in other words, when all the initial input data "1" are inverted in the data "0", the clock signal 5 circuit detection status programming PS becomes high (Vcc). That is, the cell selected input data programmed.

As disclosed above, the operations of programming and verification are repeated automatically with the data from the buffer pages only for the single input data and without any external control up until all the cells selected by the buffer pages, i.e., circuits latches the bit lines and the schema of the source of current, not optimally programmed.

In accordance with the invention, a programmed state can be optimized without the impact of changes in process parameters, reprogramming is prevented by use of the verification capabilities, and optimal program automatically performs an internal test function of the chip. As a result, oceesa response of the overall system, using this chip. In addition, the invention using the buffer pages conventional erasable and electrically programmable memory having a function to the page mode, applicable for existing products.

1. Semiconductor device crash survivable memory containing a matrix of memory cells, latches the data and the sources of high voltage by the number of columns of the matrix of memory cells, each of which is performed by the overlay layer accumulation of charge and a control gate on a semiconductor substrate, the control gates of the memory cells of each row of the matrix are combined and a corresponding address input device, connected in series to the memory cells of each column of the matrix are combined in the appropriate cell structure AND NOT, the information input-output of which is connected to the corresponding bit of the bus device, the first and second inputs of the sample cell structure AND NOT, respectively, are combined and are the first and second inputs of the sampling device, the clock input of each latch data is the first Manager of the input device, the first information inputs and outputs of each latch data, and each source of high voltage connected to the on voltage are, respectively, the second managing input and the input of the programming device, characterized in that it introduced the blocks of the test program according to the number of columns of the matrix of memory cells, the detection unit of the state of programming and a current source whose outputs are connected to inputs of corresponding blocks of the test program outputs and outputs-inputs of data latches, respectively, are combined and connected to the corresponding information input detection unit of the state of programming, the output of which is the output of the test clock signal, the clock input of the current source and the first and second clock inputs of the detection unit of the state of programming are respectively the third, fourth and fifth control inputs of the device, the input current source is connected to the bus reference voltage device.

2. The device under item 1, characterized in that the current source provides a reference current is performed on the p-channel MOS transistor, the source of which is connected with the first power source, a load n-channel MOS transistor, the gate of which is connected to the first input of the current source, the key n-channel MOS transistor, the source and gate of which are connected respectively with the second power bus and a clock input source is Lou columns of a matrix of memory cells, the gate of p-channel MOS transistor and the gates of the output p-channel MOS transistor group are United and connected to the United drains of p-channel load-and n-channel MOS transistor, the source of the latter is connected to the drain of the key n-channel MOS transistor, the sources of the output p-channel MOS transistor group connected to the first power bus of the power source, the drains of the output p-channel MOS transistor group is connected to the drains of the corresponding output key n-channel MOS transistor group, the sources of which are connected to respective outputs of the current source, the gates of the output key n-channel MOS transistor is connected to the clock input of the current source.

3. The device under item 1, characterized in that the detection unit of the state of the programming node contains forward bias signal node reverse bias signal and the output element, the output of which is connected to the output of the detecting unit of the state of programming of the first and second clock inputs of which are connected respectively to the control inputs of the node forward bias signal and the first input of the output element, the second input is via inverter connected to the output node of the direct CME is DAMI block, the output node of the forward bias signal is connected to the first power supply unit, conclusions site reverse bias signal is connected to the second power supply unit.

 

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