The system of simultaneous time grupoaranea.net
(57) Abstract:The invention can be used in communication networks, in particular in apparatus for the formation and separation of digital streams. When using the present invention allows access to subcomponents signals and even a separate digital channels primary groups at any level of the hierarchy. The system of simultaneous time grupoaranea.net contains side transmission unit generator equipment, the shaper group signal, the transmitter clock cycle, four memory block, the driver signal phasing, frequency synthesizer, switch utility bits, the transmitting unit main digital channels, and receive-side adaptive receiver frame synchronization, the distributor group signal generating unit equipment, switch the service bits, the frequency synthesizer, the receiving unit main digital channels, four memory block. 12 Il., table 4. The invention relates to digital communication systems and can be used in communication networks, in particular in apparatus for the formation and separation of digital streams.To date, slah with PCM. One of them is the European method uses positive digital equalization of speeds, in the other, used in our country, the method of bilateral clearing speeds. Both hierarchies have the same transfer rate at all levels of the hierarchy from the first to the fourth.Table 1 summarizes the technical characteristics of both hierarchies needed to clarify the nature of the proposals.In a primary transmission system PCM-30, which is the channel, a temporary bit position of any channel (main digital channel BCC) is strictly fixed in the cycle of transmission, so the transit of individual BCC it is quite easy to implement by providing appropriate bit in the desired channel interval of the cycle. Accordingly, expected and fit these items new bit of information.Of course both of these operations can be performed only after the establishment of frame synchronization on the primary group to sign an unambiguous sequential phasing of the frequency divider relative to the primary group of the signal.Devices which transport the BCC from the primary group of the signal is known and ispolzuyte this hierarchical level (aggregate signal) is achieved by time grupoaranea.net 4 group signals (component signals) from the previous stage of the hierarchy. It is assumed that the setpoint generators are sources of aggregate and component signals independent communication systems in relation to each other.Under these conditions, direct transit component signal, and furthermore the BCC group of the second signal and the higher level of the hierarchy is impossible due to changes in the number of information bits in a fixed cycle of transmission. With the growth of the hierarchy problem of transit a separate thread or BCC has become increasingly complex due to the asynchronous transformations at each hierarchical level. The execution of such transit will require at the point of transit installation of equipment at all levels of the hierarchy involved in the formation of this signal.The task is simplified if the triggering setpoint generators at all levels of the hierarchy. However this only applies to the Russian hierarchy, use two-align speeds. In the European hierarchy of the cycle frequency of the primary level of the hierarchy and all subsequent not multiples of each other and the transition from one step to the next will continue to be made through an asynchronous transformation.In the Russian hierarchy of the cycle frequency of the primary and the WTO is ity of grupoaranea.net without using equalization of velocities and accordingly transit component signal without using a full set of equipment secondary time grupoaranea.net.Further on the possibility of transit of thread or a separate BEC in aggregate signal will understand (enumeration) temporary positions we are interested signal in the cycle of the aggregate signal. In the absence of equalization of speeds number of the mentioned positions in the cycle aggregate signal will be unchanged.However, there are factors that hinder the use of synchronous grupoaranea.net, among which low wandering phase synchronous component signals. The magnitude of these errors is expressed in clock intervals of the signal depends on the feedback channel through which passed the signal received at the input equipment grupoaranea.net. The largest value of the wandering phase provide satellite communication channels, in which daily care phase, referred to the primary signal (PCM-30), is 2000 clock intervals. In synchronous terrestrial networks wandering phase should not exceed 40 clock intervals (G 823 CCITT).In commercially available equipment, grupoaranea.net memory storage device, the processing component signals, does not exceed 10-12 bits, so it does not allow synchronous grupoaranea.net, despite the previously mentioned erali leveling speed, that makes it impossible for the transit component signals and a separate BEC in domestic equipment time grupoaranea.net.Another factor limiting the use of synchronous grupoaranea.net is the lack of synchronous communication on a global scale. Synchronous network will be built in the future on the basis of individual synchronous zones, managed from independent clock generators with high frequency stability. The transition of the synchronous signal from one zone to another should take place without interruption of communication or organization ordered "slippage", the repetition period of which should be measured in weeks or even months.When the organized "slippage", caused by a slight difference of the frequencies of the sets of generators of different synchronous zones, it is desirable to provide uninterrupted frame and multiframe synchronization on the primary group signal. In this case, all established connections will be saved, but the loss of several increments of the encoded speech signals will not have a significant impact on the quality of transmitted signals. In some BCC, which is transmitted nonverbal information can occur when the supply of:
the number of bits in a loop PCM-30 (primary group signal) nC=32 KIbit= 256
the number of bits in the multiframe PCM-30 Njvac=nC16=4096
memory required memory), bit - NZU=2Njvac= 8192
The impact of plesiochronous specifies generators is illustrated in table 2.Thus, the use of memory displacement of 8,192 bits (primary signal) allows you to organize synchronous grupoaranea.net when stability setting generators from 10-8and above, including in the presence of satellite communication channels, which is consistent with the trend of development of means of communication.Another area of application of synchronous grupoaranea.net can be organization interoffice beams connecting lines or communication digital switching stations with their external modules.As a prototype of the proposed solution can be accepted as secondary time grupoaranea.net with a set of essential features, closest to the stated [1, C. 41] it Should be noted that domestic equipment all subsequent levels in the hierarchy is based on the same structural pattern.Protectione transfer block generating equipment (BGO), the output of which is connected to the shaper group signal (FGS), one input of which receives a service signal, and the other is connected to the transmitter clock cycle (PDB). The first and second outputs of the FGS are the outputs of CSAS. Receive-side CSAS contains an adaptive receiver frame synchronization (APCS), the first input being the input of the CSA is connected to the distributor group signal (RGS), a second input, which is also an input of the CSA is connected to the input BGO, a third input connected to the output of BGO. BGO also has an input connected to the output APCS, and the output connected to the RGS. In addition, CSG has access service signal, which is output CSAS.The disadvantage of the prototype is the inability of transit signal any associate's degree and BCC without the use of equipment at all levels of the hierarchy involved in the generation of this signal. In the inventive system, it is advisable to keep all the speed of hierarchical levels the same as in the prototype that will allow you to use the already built linear paths (radio or cable).The purpose of the proposed invention is to provide a system synchronous grupoaranea.net, after which the aggregate signal the use of equipment at all levels of the hierarchy.To implement the proposals should
synchronisation sets of generators of all levels of the hierarchy from a common master oscillator;
frequency group signal any level of the hierarchy is equal to 8 kHz, which coincides with the frequency of cycles of the primary group of the signal.Table 3 provides one possible synchronous hierarchy with a constant cycle and its capabilities.The essence of the proposed invention is the synchronization of signals at different hierarchical levels and the transition to a single frequency cycles that allows you to select an individual component flows at the different levels of the hierarchy.In Fig. 1 shows a block diagram of a system synchronous time grupoaranea.net on the side of the transmission.In Fig. 2 presents a block diagram of a system synchronous time grupoaranea.net on the receiving side.In Fig. 3 shows a block diagram of the frequency synthesizer.In Fig. 4 shows a structural block circuit diagram of the generator equipment.In Fig. 5 shows a block diagram of the shaper signal phasing.In Fig. 6 presents snowdownia blocks BCC.In Fig. 10 shows the block diagram of the shaper group signal.In Fig. 11 shows a structural diagram of the distributor group signal.In Fig. 12 presents a structural diagram of the memory unit of small capacity.In Fig. 1: 1-4 butt regenerators receiving component signals (SRPX), 5 unit generating equipment (BGO), 6 shaper group signal (FGS), 7 transmitter clock cycle (PDB), 8 - butt regenerator transfer aggregate signal (SCEAS), 9 synthesizer frequency (MF), 10 shaper signal phasing (PSF), 11-14 random access memory blocks (OSB), 15 switch service bits (KSF), 16 emitting unit main digital channels (BEC).In Fig. 2: 17 butt regenerator receiving the aggregate signal (SCAS), 18 adaptive receiver frame synchronization aggregate signal (APCS), 19 generating unit equipment (BGO), 20 allocator group signal (RGS), 21-24 butt regenerators transmission component signals (SCEX), 25 switch service bits (KSF), 26 frequency synthesizer (component and subcomponents) (MF), 27 receiving unit main digital channels (BCC), 28-31 memory the Finance component signal, 34 switch bit service component signal, 35 allocator component signal (SW) 36 - receiving unit of the main digital channels, 37 memory unit 38 butt regenerator subcomponents signal.In Fig. 3: 39, 44, 49 frequency dividers, 40, 45, phase detectors, 41, 46 filters low pass, 42, 47 generators, voltage controlled, 43, 48 shapers signal.In Fig. 4: 49 divider distributor 1:4, 50 group frequency divider, 51 block decoders, 52 cyclic divisor.In Fig. 5: 10 driver signal phasing, 53 frequency divider, decoder 54.In Fig. 6: 55 scheme 2I-drinking, inverter 56.In Fig. 7-9: element 57 And 58 of the counting trigger, 59, 60 elements AND, 61 transformer, transformer 62, 63, 64 Comparators, 65 - serial register, 66 parallel register, 67 element 2I-ILI, element 68 OR 69 serial register, 70 parallel register 71 - series-parallel register.In Fig. 10: 72-75 elements And, 76, 77 elements OR 78 of the switch.In Fig. 11: 79-82 elements OR NOT, 83-86 elements And, 87-91 elements And.In Fig. 12: 92 dispenser frequency recording, 93 frequency divider reading, 94 block of memory cells, 95 commute is passing four USB 11-14, the first and second inputs, which are inputs SVG. On the third inputs of OSB 11-14 signal from output PSF 10. In turn, the input PSF 10 is output SVG and is connected to the second output BHO 5. The third output BHO 5 is connected to the fourth inputs of OSB 11-14, the first input BHO 5 is input SVG, a second input connected to the output of SCH 9, the input MF 9 is input SVG. The first output BHO 5 connected to the first input 6 FGS. Inputs FGS 6 4 through 7 are connected respectively to the outputs of OSB 11-14. The third entrance FGS 6 is input SVG. The first and second outputs FGS 6 are outputs SVG. Second input of the FGS 6 is connected to the output PDB 7, an input connected to the third output of the KSF 15. The second output of the KSF 15 is connected to the fifth input OSB 11-14. The first output of the KSF 15 is connected with the 8th sign-6 FGS. First entry KSB 15 is connected to the fourth output BHO 5, the fifth output of which is connected to the first input of the transmitting unit BCC 16, a second input connected to the fourth output of the KSF 15. The first output of the emitting unit BCC 16 is connected to the ninth input 6 FGS. The outputs of the transmitting unit BCC 16 2 th to (K+1) th outputs are SUG. Inputs emitting unit BCC 16 3 th to (K+2)-th input SVG. At the receiving side SVG contains APCS 18, the first and third inputs which evlaution BHO 19 and the inlet SC 26. The first input BHO 19 is connected to the output APCS 18, the first output BHO 19 is connected to a second input RGS 20, the third output BHO 19 is connected to the input of the KSF 25, the fourth output BHO 19 is connected to a second input receiving unit BCC 27. The first output of the KSF 25 is connected with the third input RGS 20, the second output KSF 25 connected to the first input receiving unit BCC 27, the third output KSF 25 is connected with the first inputs of OSB 28-31. The second output MF 26 is output SVG. The first midrange output 26 is connected to second inputs of OSB 28-31. 2K outputs of the receiving unit BCC 27 are outputs SVG. A third input receiving unit BCC 27 connected to the first input APCS. The second output of BGO 19 is connected to a second input APCS and third inputs USB 28-31. The first output RGS 20 is output SVG. Outputs RGS 20 from 2 through 9 are the outputs SVG and connected to respective fourth and fifth inputs of OSB 28-31. The first and second outputs of OSB 28-31 are outputs SVG.The inventive system operates as follows.On the transmission side (see Fig. 1) on the signal input system receives a synchronous component signals that have passed the communication channels of varying configuration and length. Butt regenerators receiving component signals 1-4 compensate for the attenuation in the butt C the LASS="ptx2">The regenerated signals and their accompanying clock sequence received on the 1st and 2nd inputs 4 random access memory blocks (OSB) 11-14, where the account information of parcels in the memory cell. Reading the recorded information is performed by the clock pulses on the 4th inputs USB 11-14 from the third output unit generating equipment (BGO) 5.In turn, BGO 5 starts from frequency synthesizer (MF) 9 generating a clock sequence of the desired hierarchical level. MF 9 is synchronized from an external signal, which may be a clock signal of frequency component signals or clock frequency any level of the hierarchy. It is significant only that frequency component signals and the clock signal must be synchronous.BHO 5, having in its composition cyclic frequency divider and a set of shapers clock sequences, controls the operation of all equipment of the transmitting side system and participates in the formation of the cyclic transmission of the aggregate signal. The repetition of cycles constant for any hierarchical level and is 8 kHz.Reading poladay heartbeats forming a service group cycle. However, the average frequency of the read sequence is exactly equal to the clock frequency of any component of the signal.Switch service bits 15 receives at its inputs the clock pulses corresponding to the service bits cycle in aggregate signal from the fourth output of BGO 5. Some of these impulses through the third output switch utility bits 15 to the transmitter clock cycle 7, which is a record of the parcels of a cyclical clock signal at the predetermined service position cycle aggregate signal.To ensure connectivity in the inventive system plesiochronous signal on the first output switch utility bits 15 provides additional pulses, which are clearing transaction speeds and the transfer of appropriate control commands matching speeds. Thus instead of the corresponding USB 11-14 is set to block asynchronous pairing of transmission, similar to that used in the prototype. If plesiochronous signals not, input 5 V memory blocks not in use.To implement p the capacity provided shaper signal phasing 10, representing a combination of the connected frequency divider and decoder signals, by means of which produces a narrow pulse with a repetition frequency corresponding to the selected memory capacity. For the above case, the processing of the primary signal with a memory capacity of two multiframe 8192 bit repetition frequency of the pulse phasing should not exceed fh:32=8 kHz:32=250 Hz. Environment impulse through 3rd entry OSB 11-14 performs phasing reading process.Part of the official positions of the aggregate signal can be used to transmit service signals such as a signal "notice" about the accident the remote station. These signals are received at the third input 6 FGS. In addition to all the above-mentioned signals provides for the transfer of the main digital channels - BCC. To transfer a single BCC requires eight temporary (service) positions in each cycle of transmission. The junction with the subscriber terminals of opposite direction is carried out in accordance with p. 2.4 GOST 26886-86.Combine all components into a single aggregate signal is performed in block 6 FGS, which with the help of signals through the 7th sign, the recording of information on service marovany aggregate signal and the associated clock sequence with outputs 6 FGS come to butt regenerator aggregate transmission signal 8, where this signal is converted to a play-off signal of the given hierarchical level.To ensure mutual phasing generator equipment subsequent and previous levels of the hierarchy provides input and output phasing BHO 5. Through its first input is the phasing of BGO 5 from BGO higher level of the hierarchy, and with the second output BHO 5 gaziruetsya BHO lower level of the hierarchy.In grupoaranea.net two or more levels of the hierarchy corresponding to butt the regenerators of the inventive circuit can be omitted. Connection point signal for this case is shown in Fig. 1 and 2.The sample loop of the secondary signal with the transfer of one plesiochronous signal at the positions of the first component signal is presented in table 4.If the loops of the primary and secondary signals spairani, which is achieved by use of USB high capacity (8,192 bits) or mutual phasing units generating equipment, you can specify the position of a separate BEC in the second group signal. So, zero channel interval of the second primary thread will be located in the first group of secondary signal and will take place following the interact (OMS), will take a temporary position with the same numbers, but in the third group of cycles of the secondary signal. Similarly, under the same conditions, you can specify the positions of individual BCC in the third and fourth signal.At the receiving side the aggregate signal is fed to the input of butt regenerator receiving the aggregate signal 17. On its outputs appear decoded signal and the accompanying clock sequence. Adaptive receiver frame synchronization 18 detects in the aggregate signal of the digital clock signal, which gaziruetsya work unit generator equipment 19 through its first input. In a cyclical condition of synchronism signal on the second output BHO 19 coincides with the environment impulse.The first output signals of BGO 19 control the operation of the distributor group signal 20 (group signals input through the first input). Four pairs of component outputs 2-9 RGS 20 allocated component signals with accompanying clock sequences. These pairs of signals are received on the fourth and fifth inputs of the respective memory blocks 28-31. Mentioned clock sequences have gaps clock is="ptx2">Reading recorded in OSB 28-31 information is uniform clock sequence generated by the frequency synthesizer 26 at the first exit, which is common to all component signals. The frequency synthesizer 26 of the aggregate clock sequence produces a clock sequence component and (if necessary) subcomponent signals.Signals from OSB 28-31 and accompanying clock sequences are received at the inputs butt regenerators transmission component signals 21-24, where they are converted into butt signals corresponding hierarchical level and then fed to the system outputs.In the receiving unit of the main digital channel 27 by the formation of the signals BCC, sent as official positions of the aggregate signal, and the positions of the component signals and even BCC in a separate primary groups, if their cycles in phase with the cycle of the aggregate signal.The outputs of the receiving unit BCC 27 produces signals corresponding to the requirements of GOST 26886-86, then flows to the subscription endings. The generation of these signals is performed using a clock sequences with Thu the local synchronous, is the switch a service bit 25. Service bits allocated for maintenance plesiochronous signal (see table 4), with the help of this switch are on the appropriate component outputs RGS 20. At the same time instead of the corresponding USB 28-31 included block asynchronous interface similar technique to the one used in the prototype. Output 1 frequency synthesizer 26 may not be used.If desinfecte component signal relative to the aggregate you can enable the receiving node below the level of the hierarchy, consisting of a set of already considered blocks 32-38. Using this node can be allocated subcomponents signal or BCC entered on the official position of the component signal. The principle of this site is similar to the above, with one exception, namely that the clock sequence subcomponents signal produced by the General frequency synthesizer 26.The site below the level of the hierarchy can connect to any pair of outputs 2-9 RGS 20, where there are simultaneous signals. Uneven heartbeat sequence does not affect the operation of the node, as the number of clock pulses in the cycle strictly constant.CNA the ability of a system (see table. 3);
completely eliminates the parasitic phase fluctuations introduced by the asynchronous pairing;
reduced equipment and simplifies its manufacture and operation;
by providing access to subcomponents signals and even to individual BCC primary groups at any level of the hierarchy are achieved greater flexibility and maneuverability of the system;
the system contains fewer analog devices (excluded blocks of the PLL are enabled for processing component signals) that facilitates the microminiaturization of equipment.Further information on the possibility of implementing system.Butt regenerators 1-4, 8, 17, 21-24, 38 standard and can be identical to the corresponding regenerators prototype.Adaptive receiver frame synchronization can be built according to the scheme given in Fig. 2.20, S. 62  frequency Synthesizers 9 and 26 can be constructed according to the scheme given in Fig. 3.To the input of the synthesizer receives clock frequency of the control oscillator. The frequency divider 39 divides the incoming signal to a frequency of 64 kHz. The divider 39 depends on the frequency control signal and is 32, 132, 537 and 2176 for Lebane with the desired frequency f2and f3of the above series. These oscillations are converted into a clock sequence shaper signal 43 and 48. These sequences in the frequency dividers 44 and 49 are also divided to a frequency of 64 kHz. The received signals are compared in phase in the phase detectors 40 and 45 with a frequency of 64 kHz, obtained in the frequency divider 39. The resulting comparison signals are filtered by low pass filters 41 and 46, and controls the frequency of the generators 42 and 47. Thus, both output signals are synchronous with the incoming signal. If necessary, may include the third branch or excluded one of the two.In Fig. 4 shows an example implementation of block TH 5 and TH 19, and Fig. 5 - block signal phasing 10.Blocks TH 5 and TH 19 constructed according to the scheme, as shown in Fig. 2.22  Each of the blocks TH contains three frequency divider 49, 50 and 52 and the block decoders 51. The divider-dispenser (1:4) 49 divides the clock sequence, entering through the inlet (1) into four shifted relative to each other clock sequence with a frequency of four times lower than the input. Next one of these sequences is divided by group frequency divider 50 to the frequency of repeating the interest of the hierarchy. The initial phasing of the frequency dividers is provided through input (2) external signal on the transmission side or the signal of the adaptive receiver frame synchronization 18 on the receiving side. The block decoders 51, receiving signals from all of the digits of frequency dividers, allows to obtain a clock sequence corresponding to any desired position in the cycle group signal. So at the output (4) produces a sequence of narrow pulses with a repetition frequency equal to the frequency of 8 kHz, and the repetition rate of the clock.Outputs (2) produces a clock sequence used to interface with the BCC with the repetition frequency of the pulses 64 kHz and 8 kHz. Outputs (3) are formed in the clock sequence corresponding to the service bits in each group (1 to K) of the transmission cycle. Output (5) is generated clock sequence with divider-dispenser (1:4) 49 from which removed all pulses corresponding to the official positions of the loop.Implementation of the transmitter clock cycle 7 by using the inverter 56 and logic circuits 2I-drinking (see Fig. 6). The inverter input is at a potential of the common wire, which corresponds to a logical input or output of the inverter depending on the type formed of a cyclical clock. On the second outputs are served pulse sequence with switch utility bit 15, which should follow the digital signal. After the merger OR all n signals from the elements And to the output of the circuit 2I-drank 55 is formed to the desired frame sync signal, disposable time on the selected position of the transmission cycle.Switches the service bits 15 and 25 in the simplest case can be a mechanical switch. A portion of the service position (pulses) in the process may not change the purpose (for example, the pulse cycle allocated for transmission of a cyclical clock signal notification, etc ). While the other part of the pulse can vary from signaling support plesiochronous component signal (as in the prototype) to transfer information organized by the BCC. If not required switching operations of the service position (pulses), a mechanical switch can be replaced by the installation of a fixed number of jumpers.For example, for the implementation cycle according to table 4 jumper must be installed so that the outputs (2) switch 15 appeared pulses corresponding to positions 1-8 group 1 and G3 and 1.5 and 9-G4. Outputs 3 should be all pulses except those that are available at the outputs 1.The line switching service bits for different levels of the hierarchy requires a separate study and is essentially a question of process, the same applies to the transit component and subcomponent signals and a separate BEC.In Fig. 7-9 are examples of complete equipment BCC transmitting and receiving sides 16 and 27 in relation to the requirements of p. 2.4 GOST 26886-86 opposite to the junction of the BCC. Toward the subscribers BCC emitting unit BCC 16 must pass the clock signal with octet mark. Code of the transmitted signal AMI violation sequence at the beginning of the octet. The driver of such a signal (common to all include BCC) is shown in Fig. 7.At the first input element And 57 receives a sequence of pulses of negative polarity with a pulse repetition rate of 8 kHz and a pulse duration of one clock interval frequency 64 kHz (15.6 μs). To the second input element And 57 receives the clock sequence with a pulse repetition frequency of 64 kHz with a duty cycle of 0.5. Output element And 57 receive the clock sequence, with one exception that is NOT 59 and 60 and the transformer 61 is a well-known signal Converter in the AMI code. By eliminating one clock pulse disturbance sequence on the place of the excluded pulse. Similarly, the driver clock signal with octet mark can be used in the receiving unit BCC. This signal is common to all subscribers BCC receiving side.Coming from the individual subscriber BCC information signal in the code AMI, transferable, is processed by the circuit of Fig. 8. The signals from the secondary winding of the transformer 62 receives the outputs of the Comparators 63 and 64, the reference input of which is filed with the reference voltage U0. At the joint Assembly OR the outputs of the Comparators produces a unipolar signal caller BCC, which is recorded in successive 8-bit register (clocked sequence of 64 kHz transferor). Octets subscriber signal is recorded in the parallel register 66 clock sequence 8 kHz transmission. These octets are held in registers 66 throughout the transmission cycle of the aggregate signal. Overwriting of the signal at the selected time position in the aggregate signal is performed using the element 2I-ILI 67 and signals on the bus are reserved this BCC. Similarly, the scheme vklyucheno in the primary signal.Separate signal BV from the aggregate signal (27) can be made using the scheme in Fig. 9. Group aggregate signal input (3) is supplied to the D-input of the serial register 69, the clock input of which is through the element OR 8 receives the clock pulses corresponding to the positions occupied by the data BCC in the aggregate signal. The octets of the selected signals are overwritten in the parallel register 70 clock sequence 8 kHz receiving side. In the parallel-serial register 71 converts the signal from a parallel form to serial, stepping sequence 64 kHz receiving side. The number of blocks shown in Fig. 9, is equal to the number of BCC.To transmit the information signal to the subscriber at the receiving side in accordance with the requirements of the standard interface you can use already discussed the diagram shown in Fig. 7.While at the first input element And 57 should submit a clock sequence of 64 kHz reception, and to the second input of the output register 71.Shaper group signal 6 (see Fig. 10) performs the same functions as the same block of the prototype, but due to the existing differences in Festplatte Gating, i.e. oburzenie parcels component signals on respective signals from the block generator equipment 5. The obtained fitted signals are collected into a single signal element OR 76. In another element OR 77 is a temporary Union of the service signals, signals BCC and the frame synchronization signal. The signals from both elements 76 and 77 are received on the switch 78, controlled by the pulses from the switch service bit 15. In the presence of a pulse at the control input of switch 78 at its output is the signal from the element OR 77, and in the absence of the pulse signal from the OR element 76. At the output of the switch 78 is formed, thus, the full aggregate signal.In Fig. 11 presents an example implementation of the distributor group signal 20. On the first inputs of elements And 83-86 receives a clock sequence from the first outputs of BGO 19. In the elements OR NOT 79-82 merged impulses that are not associated with the translation of the corresponding component signals. Due to the inversion in these elements collected together pulses are prohibiting, resulting in a sequence of pulses at the outputs of the elements And 83-86 will be skipping pulses corresponding to the temporary position signals, coming together with the accompanying clock sequences to corresponding outputs RGS 20, by means of the elements And 91 are allocated to other service signals, such as signal "notice".In the claimed system as a random access memory blocks assumes the use of three types of devices. The first type is relatively small capacity (8.120 bit) can be used as USB receiving side (28-31) and on the transmission side (units 11-14) if the source component flows near the system grupoaranea.net or in the presence of grupoaranea.net two or more levels of the hierarchy simultaneously. In these cases, the phase deviation is caused only by the unevenness of the standard positions when writing, reading or both when writing and reading. An example of the implementation of this scheme is shown in Fig. 12. From clock record sequence (1) with the help of the distributor of the recording frequency 92 is formed by a sequence of address signals that result in the entry information (2) in the block of memory cells 94. Of the clock sequence reading (3) a frequency divider read 93 are formed in sequence reading. Signals from the outputs of the frequency divider read vychod, due to which the incoming signal is rewritten at a clock frequency of reading. Due to the synchronism of the clock frequency of the read / write is possible to install the distributor divider 92 and 93 once per cycle of 8 kHz, which is the signal input through the fourth input of the unit OSB. This setup eliminated the need for tracking the phase shift between the sequences of read and write.If necessary broadcast plesiochronous component signal instead of the corresponding memory blocks are activated cell asynchronous pairing: AUtrans.on the transmission side and the AUAveat the receiving side. In their scheme, these blocks may be identical with the blocks of the prototype. Additional clock sequence required for leveling speed, proceed through the fifth input units 11-14 and 28-31, in the case of synchronous signals unused.If necessary, enable the storage of large capacity unit as OSB 11-14 transferor may be used a known device synchronization digital streams (USCP) 
Thus the first input of OSB will fit the SIG is th input OSB installation log USCP.Due to the complexity of the driven device  the use of such OSB will be justified only in the presence of satellite communication channels or quasisynchronous working with independent high-stability oscillators component and aggregate signals with the introduction of ordered slippage.For the case of terrestrial channels in synchronous zones with a limited amount of walks phases can be used already considered in Fig. 12 scheme with storage capacity, part of a hundred or several hundred bits.The sources of information.1. "Equipment PCM-120". / Edited by L. S. Levin. M. Chapman and hall, 1989, S. 41 (prototype).2. Patent application 92-015648/09 (061305) from 28.12.92, a positive decision from 30.01.1995, CL H 04L 7/08. The system of simultaneous time grupoaranea.net containing on the transmission side unit generating equipment, the first output of which is connected to the first input of the shaper group signal, a second input connected to the output of the transmitter clock cycle, the third input of the shaper group signal is input utility signal system, the first and second outputs of the shaper group stepny receiver frame synchronization, the first input information which is input aggregate signal system and connected to the first input of the distributor group signal, a second input connected to the first output unit generating equipment, the second output of which is connected to a second input of the adaptive receiver frame synchronization, the output of which is connected to the first input unit generating equipment, the second input is a clock input aggregate signal system and is connected to the third input of the adaptive receiver frame synchronization, and the first output of the distributor group signal is output service system signals, characterized in that on the transmission side put four memory block, the driver signal phasing, the frequency synthesizer switch service bits, the transmitting unit main digital channels, the first and second inputs of the memory blocks are respectively the information and clock inputs of the component signals, the third inputs of the memory blocks connected to the output of the shaper signal phasing, the inlet of which is connected with the environment of the system output and the second output unit blocks, the outputs are connected to respective inputs from the fourth to the seventh shaper group signal, the eighth input connected to the first output switch service bits, the first input connected to the fourth output unit generating equipment, the fifth output of which is connected to the first input of the transmitting unit main digital channels, the first output of which is connected to the ninth input of the shaper group signal, the second output switch service bit is connected to the fifth input of random access memory blocks, the third output switch service bit is connected to the transmitter input clock cycle, the fourth output switch service bit is connected to a second input of the transmitting unit main digital channels whose outputs from the second to the (K + 1) th outputs are the butt of main signals of the digital channels and the inputs from the third to the (K + 2)-th input of the butt of the main signals of the digital TV system, the first input unit generating equipment is the environment entry system, the second input unit generating equipment connected to the output of the frequency synthesizer, the input of which is the clock photometric channels, four memory unit, and the input switch service bit is connected with the third output unit generating equipment, the first output switch service bit is connected to the third input of the distributor group signal, the second output switch service bit is connected to the first input receiving unit main digital channels, and the third output switch service bit is connected with the first inputs of the memory blocks, the second inputs of which are connected with the first output of the frequency synthesizer, the second output of which is a clock output subcomponent signals, and the input of the frequency synthesizer is connected to the second input of the generator equipment, the fourth output of which is connected to a second input receiving unit main digital channels, a third input connected to the first input of the adaptive receiver frame synchronization, 2K outputs of the receiving unit of the main digital channels are outputs butt of main signals of the digital TV system, the second output unit generating equipment connected to the third inputs of the memory blocks, the fourth and fifth inputs of which are connected with information and clock outputs the signal, the first and second outputs of the memory blocks are the butt of information and clock outputs the component signals of the system.
FIELD: radiophone groups servicing distant subscribers.
SUBSTANCE: proposed radiophone system has base station, plurality of distant subscriber stations, group of modems, each affording direct digital synthesizing of any frequency identifying frequency channel within serial time spaces, and cluster controller incorporating means for synchronizing modems with base station and used to submit any of modems to support communications between subscriber stations and base station during sequential time intervals.
EFFECT: enhanced quality of voice information.
12 cl, 11 dwg