Device for detecting and tracking the synchronization signal in satellite communication systems for receiving

 

(57) Abstract:

The invention relates to a multi-channel communication system constructed according to the principle of "each other, and can be used in systems synchronization of such systems. The technical result from the use of the invention consists in expanding Arsenal of technical means, the reduced frequency search, improving the signal-to-noise ratio in each channel search and improving the quality filtering of the signals in each channel search. The device contains four channels of search, each of which consists of a correlator detector and integrator, the ring phase-locked loop, ring-locked loop frequency block allocation of the maximum signal, the driver code channel, two pseudo-random sequence generator, switches, delay, driver control signals. 14 Il.

The invention relates to a multi-channel communication system constructed according to the principle of "each other, and can be used in systems synchronization of such systems.

In the prior art it is known device synchronization [1] consisting of the first and second multiplier products, the first inputs of which are I is arenosella connected respectively to the inputs of the modulator signals, clock input connected to the output of the control unit and control input of the threshold unit, the output of which is connected to the input of the control unit, the outputs of the modulator signals are connected respectively to the inputs of the integrators, the outputs of odd integrators are connected respectively to the inputs of the first adder, and outputs the even-numbered integrators with the inputs of the second adder, the outputs of the first and second adder through the respective Quad connected to respective inputs of the third adder, the output of which is connected to the input of the Converter type "square root", the first of which is the first output and the second output is connected to the information input of the threshold unit.

It is also known device synchronization of noise-like signals [2] which is complementary to [1] additionally contains one United block of memory, a comparison circuit, an additional adder and the block frequency control, the output of which is connected with the control input of the oscillator carrier frequency control inputs of the comparison circuit and the memory block are connected with the corresponding outputs of the threshold unit, and the information input of the memory block coupled to the output control unit

The prior art closest to the invention is a device for finding pseudo-random signal 3, which consists of the first multiplier, a first input which is the input device, and a second input connected to the output of the controlled oscillator and the output of the first multiplier is connected with the first inputs of the second, third and fourth permenately, second input which is connected to the output of the corresponding digit of the shift register, the output of the second multiplier is connected to the inputs of the first and second intermediate frequency amplifiers, the outputs of which respectively through the first and second detectors connected to respective inputs of the first adder, the output of which through an amplifier connected to the input of the controlled oscillator, the outputs of the third and fourth multiplier products are connected respectively to the inputs of the third and fourth intermediate frequency amplifiers, the outputs of which respectively through the third and fourth detectors are connected respectively to the inputs of the second adder, the output of which is connected to the input of the lowpass filter, the output of which is connected to the input of the controlled oscillator, the output of which is connected to a clock input of the shift register.

This is com device, implements a parallel search method and tracking synchronization signal is a redundancy of equipment, much of which is not used in the mode of synchronism after the end of the search.

The disadvantage of this device that implements a sequential search method according to the frequency of the synchronization signal is a quite time-consuming search procedure.

In addition, all of the known device is not suitable for use in satellite communication systems, built on the principle of each other and using different pseudo-random sequences for transmitting information and for the transmission of synchronization signals.

The technical challenge which sent the unit is the development of a device for detecting and tracking the synchronization signal in satellite communication systems with noise-like signals, based on the principle "each other and use different pseudo-random sequences for transmitting information signals and synchronization signals.

The technical result from the use of the device is to expand the Arsenal of technical means to solve this problem, the reduction in the duration of search is often the om channel.

This technical result is achieved in that the device for detecting and tracking the synchronization signal in satellite communication systems (SCS) for receiving, containing the first frequency Converter, the first input by the information input unit and the second input is connected to the output of the controlled oscillator, a low pass filter, four detectors, three correlator, multiplier, adder, controlled clock oscillator and discriminator phase-locked loop, the outputs of the first, second and third correlator connected to inputs of respectively the first, second and third detectors, introduced the amplifier high frequency, the second frequency Converter, lo, fourth, the fifth and sixth correlators, fifth and sixth detectors, resonant amplifier, a threshold element, five integrators, block allocation of the maximum signal, the driver code channel, a frequency discriminator, the frequency generator marker, shaper signal adjustment of the controlled generator for pseudo-random sequence generator, two switch delay, the frequency divider pulses, key, generator control signals, the generator frequency reference unit sample-hold proportionally with the stroke of the first frequency Converter via the amplifier high frequency is connected to the first input of the second frequency Converter, a second input connected to the output of the local oscillator, and the output of the second frequency Converter connected to the input of the lowpass filter, the output of which is connected with the first information input from the first to the sixth correlators, the outputs of the fourth and fifth correlators connected to inputs of, respectively, the fourth and fifth detectors, the outputs of the first-fifth of detectors connected respectively to the information inputs of the first to fifth integrators whose outputs are connected respectively to the inputs of the block selection signals, the outputs of which are connected respectively to the inputs of the driver code channel, a group of four outputs which are connected respectively with the first to fourth control inputs of the first and second switches delay, the fifth control inputs which control input mode driver control signals are combined and connected to the output of the lack of detection signal shaper code channel, the fourth output group output of which is connected with the inlet of bandwidth proportional-integrating filter, an information input connected to the output of the sample-hold information whose input is the, which is connected to the outputs respectively of the second and third integrators, the reset inputs of all of the integrators are combined and connected to the output of the Reset driver control signals, the input of the start of which is the input of the start device, and outputs the detection Signal information" and "End of search" driver control signals are the respective outputs of the device, the output of the sixth correlator connected in series through a resonant amplifier and a sixth detector connected to the information input of the threshold element, the reference input threshold which is a reference input of the threshold device, and the output of the threshold element is output marker signal synchronization device, the generator output frequency marker connected to the first input of the multiplier, the output of which is connected with the second information input of the sixth correlator, the output of the fourth correlator is connected also to the input of a frequency discriminator, the output of which is connected to the input of the shaper signal adjustment of the controlled oscillator, the outputs of which are connected respectively to the inputs of the controlled oscillator, the output of the proportional-integrating filter connected to the input of the detector absolute values, the information output of which is connected to the input of the Converter is, the second control input which is connected to the sign detector output of the absolute value, and a clock input controlled oscillator connected to the generator output frequency reference, output controlled oscillator is the output clock of the device and is connected with the information input key and the first clock input of the shaper control signals, the first clock output of which is connected to the control input of the key, the output of which is connected to the input of the frequency divider pulses and clock inputs of the first and second pseudorandom sequence generators, the output of the first pseudo-random sequence generator connected to the first input of the adder and an information input of the first switch delay the first to fourth outputs of which are connected to the second information inputs, respectively, of the first-fourth correlators, the fourth output of the first switch delay is connected with the second input of the multiplier, the output of the frequency divider pulses connected to the second tattoonow input shaper control signals, the output of the second pseudo-random sequence generator is connected to the second input of the adder and the information is device, and the output of the adder is connected to the second information input of the fifth correlator, the input signal recording unit sample storage and input reading proportional-integrating filter combined and connected to the second clock output driver control signals.

In Fig. 1 and Fig. 2 is a diagram of the device of Fig. 3 embodiment of the driver control signals of Fig. 4 embodiment of the block selection signals, and Fig. 5 embodiment of the switch delay, Fig. 6 embodiment of the driver code channel, Fig. 7 embodiment of the detector of the maximum signal in Fig. 8 diagram illustrating the principle of proportional-integrating filter of Fig. 9 embodiment of the frequency discriminator of Fig. 10 embodiment of the driver signals the adjustment of the controlled oscillator of Fig. 11 diagram of the correlator of Fig. 12 the structure of the synchronization signal in the system of Fig. 13 table of correspondence signals of the decoder block allocation of the maximum signal in Fig. 14 table of correspondence signals of the decoder driver code channel.

The device comprises an input 1, which is the first input of the first Converter 2 Chignik frequencies, the output of the first frequency Converter 2 is connected to the input of the amplifier 3 high frequency, and the other input of the second inverter 4 frequency connected to the output of the local oscillator 6. The output of the filter 5 of the lower frequencies is connected with the first information input of the first 7, second 8, the third 9 and fourth 10, 11 fifth and sixth 12 correlator, the output of the first correlator 7 through the first detector 13 is connected to the information input of the first integrator 14, the output of the second correlator 8 through the second detector 15 is connected to the information input of the second integrator 16, the output of the third correlator 9 through the third detector 17 is connected to the information input of the third integrator 18, the output of the fourth correlator 10 through the fourth detector 19 is connected to the information input of the fourth integrator 20, and the fifth output of the correlator 11 through fifth detector 21 is connected to the information input of the fifth integrator 22, the outputs of the first 14, second 16 and third 18 and fourth 20 and 22 fifth integrators are connected respectively to the inputs of the block 23 allocation of the maximum signal, the outputs of which are connected respectively to the inputs of the driver 24 of the code channel, the first four outputs of which form the group of outputs 25 and the outlet 26 is the output of Ostrov, and the installation of the inputs of the first 14, second 16 and third 18 and fourth 20 and 22 fifth integrators combined and indicated by the position 29. The sixth output of the correlator 12 through serially connected resonant amplifier 30 and a sixth detector 31 is connected to the information input of the threshold element, the input 33 of threshold setting which is the appropriate input device and the output 34 of the threshold element 32 is output marker signal synchronization device. Positions 35, 36, 37, 38 and 39 identified second information inputs, respectively, of the first 7, second 8, the third 9 and fourth 10 and 11 fifth correlators. The first input of multiplier 40 is connected to the output of generator 41 frequency of the marker, and the output of multiplier 40 is connected to the second information input of the sixth correlator 12, the output of the fourth correlator 10 is connected to the input of a frequency discriminator, the output of which is connected to the input of the shaper signal adjustment of the controlled oscillator, the outputs of which are connected with inputs of the controlled oscillator 44 whose output is connected to a second input of the first Converter 2 frequency.

The device also contains the first 45 and second 46 generators pseudo-random sequence, the divider 47 Castolovice generator 50, the output of which is a clock output 51 and is connected with the information input key inputs 27 and 28 of the discriminator 52 phase-locked loop connected respectively to the outputs of the second 16 and third 18 integrators, and the output of discriminator 52 is connected with the information input unit 53 sample-and-hold, the output of which is connected to the information input of the proportional-integrating filter, the output of which is connected to the input of the absolute value detector 55, the information output of which is connected to the input of inverter 56 "voltage-frequency", the output of which is connected to the first information input of the control clock generator 50, the second information input of which is connected with a significant output of the detector 55 absolute values.

The device also contains a second 57 58 and the first switches delay the first four control input which is connected to the group of outputs 25 shaper 24 code channel, and their fifth control inputs and control input mode shaper 59 control signals are combined and connected to the output 26 of the shaper 24 code channel, the fourth output group 25 outputs connected to the input set the operation mode proportion of integriertes control signals, the input of the start of which is the input 61 and the second clock input 60 is connected to the output of the divider 47 frequency pulse, the first clock output 62 of the driver 58 of the control signals is connected with the control input of the key 48, the output of which is connected to the input of the divider 47 frequency pulses and clock inputs of the first 45 and second 46 generators pseudo-random sequence. The output Signal of the detection information is output 63, and the output signal "End of search" is the output 64 of the shaper 59 control signals, the output 65 which is the second clock output and is connected to the input recording signal block 53 sample-hold and input reset proportional-integrating filter 54. The output of the first generator 45 pseudorandom sequence connected to the first input of the adder 66 and the information input of the first switch 58 delay, the first 35 and second 36, 37 third and fourth 38, the outputs of which are connected respectively with the second information input of the first 7, second 8, the third 9 and fourth 10 correlators, the output 38 is connected with a second input of multiplier 40. The release of the second part 46 of the pseudo-random sequence generator is connected to a second input of adder 66 and information shoewith, and the output of the adder 66 is connected to the second information input of the fifth correlator 11.

Shaper 59 control signals (Fig. 3) contains the trigger 67 inverted output of which is connected to negative input element And 68 and the first input element And 69, the second input and the first direct input element And 68 are combined and the first clock input 51 of the shaper, the output of the element 69 is connected to the information input of the counter 70, the output of the overflow through which the imaging unit 71 of pulses connected to the first input element OR 72, the output of which is connected to the zero input of the trigger 67, a unit whose input is connected to the output of the shaper 73 pulses and a single input trigger 74, direct the output of which is the first clock output 62 of the shaper, and the zero input of the trigger 74 is connected to the output element And 68 and an information input of the counter 75 pulses, the output of the overflow which is connected to the input of the shaper 73 pulses. Installation inputs of the counters 70 and 75 pulses connected to the output of the shaper 76 pulse, the first input element OR 77 and a single input trigger 78, zero input connected to the output element OR 79 and the second input of the OR element 72, and direct access Proc. of the third direct input element And 68 of the joint and is connected to the output element, And 80, the input of the shaper 76 pulses and the input of the shaper 81 pulses, the output of which is connected to the first input element 79, a second input which is the input 61 of the start of the shaper 59 control signals, and the third input element 79 is connected to the output of the overflow of the timer 82 and the zero input of the trigger 83, direct the output of which is connected to the first input element And 80, a second input which is the input 26 of the shaper 59 control signals and connected to the inverted inputs of the And elements 84, 85, 86, the output of the element 86 is connected to the input of the shaper 87 pulses, the output of which is connected to the second input element OR 77, the output of which is connected with the installation of the entrance of the timer 52, the enable input of which direct input element 86 is connected to the inverse output of the trigger 83, unit whose input is connected to the output element And 88, which is the output 63 "Signal detection information" shaper 89 control signals, the second clock input 60 shaper 59 of the control signals is input counter 89, the output of the overflow which is connected to the input of the shaper 90 pulse and the input of the counter 91 pulses, the output of the overflow of which is the output 64 "End of search" shaper 59 Santa And 84, the output of which is the second clock output 65 and connected to the first input element And 88 and the input element 92 delay, the output of which is connected to the direct input element And 85, the output of which is connected to the second input element And 88 and the input of the element 93 delay, the output of which is connected to the third input element And 88.

Unit 23 the allocation of the maximum signal (Fig. 4) contains the schema 94 comparison, the first input of which an information input key 95, and an information input key 96 is the first input unit, a second input which is the second input of the comparison circuit 94, an information input key 97 and information input key 98, the third input is the first input of the comparison circuit 99, the information input key 100 and an information input key 101, the fourth input is a second input of the comparison circuit 99, the information input key 102, and an information input key 108, the fifth input of the unit is an information input key 104 and the first input of the comparison circuit 105, the release of "more" of the comparison circuit 94 is connected with the control input of the key 95, the output of which is connected to the first input of the OR element 105, a second input connected to the output of the key 97, the control input of which is connected to the output less than or equal otklyuchen to the first input element OR 106, a second input connected to the output of the key 102, the control input of which is connected to the output less than or equal to schema 99 comparison, the output of the OR element 105 is connected to the first input of the comparison circuit 107, and an information input key 108, and the output of the OR element 106 is connected to the second input of the comparison circuit 107, and an information input key 109, the control input of which is connected to the output less than or equal to circuit 107 comparison, the release of "more" which is connected with the control input key 108, the output of which is connected to the first input element OR 110, a second input connected to the output of the key 109, the output of the OR element 110 is connected to the second input circuit 105 comparison, the decoder 111, the input of which is connected respectively to the outputs of the circuits compare 94, 99, 105 and 107, the outputs of which are respectively control inputs of the keys 96, 98, 101, 103, and 104, the outputs of the keys are the outputs of the block.

The switches 57, 58 delay made the same way and contain (Fig. 5) serially connected delay elements 112, 113, 114, 115, 116 and 117, the information input switch is the input of the delay element 112, which is connected with the information input key 118 and an information input key 119, the output of delay element 112 is also connected to the output of the delay element 114 is connected to the information input key 123, and the output of the delay element 115 is connected to the information input keys 124 and 125, the output of delay element 116 is connected with the information input key 126, and the output of delay element 117 is connected to the first input element OR 127 and information input key 128, the first output switch is the output of the key 119, the second output switch is the combined output of the keys 118, 122 and 124, the third output switch are combined outputs of keys 121 and 125 and the output element OR 127, the fourth output switch are combined outputs of keys 120, 123, 126, and 128, first managing the switch input are merged control inputs of the keys 118, 120 and 121, the second and third control inputs of the switch are respectively the first and second inputs of the element OR 129, the output of which is connected with the control input key 123 and the first inputs of the elements OR 130, 131 whose output is connected to the control inputs respectively of keys 122 and 125, the fourth managing the switch input are merged control inputs of keys 124 and 126 and the second input of the OR element 127, and the fifth managing the switch input are merged control inputs of the keys 119 and 128 and second input elements OR 130, 131.

Pho is, 40, 141 and 142. The first to fifth inputs of the driver are zero inputs respectively triggers 133-137. The first to fifth inputs of the decoder 132 are connected respectively with the first to fifth inputs of the driver, the first five outputs of the decoder are connected to the inputs respectively of the pulse shapers 138-142, the outputs of which are connected to individual inputs respectively triggers 133-136, outputs, triggers 133-136 form the group of outputs 25, the output of the trigger 137 is output 26 of the driver.

The absolute value detector may be in the form (Fig. 7) peak detector 138 and the comparison circuit 139, the output of the "greater or equal" which is a landmark detector output information output which is the output of the peak detector 138, which input and the first input of the comparison circuit United and is the input of the detector, and the second input of the comparison circuit connected to the bus zero potential.

Proportional-integrating filter 54 (Fig. 8) may be made in the form of an operational amplifier 140 with capacitors 141 and 142 in the feedback circuit and keys 144, 145, information input keys combined and connected to the input of the operational amplifier, the output of the key 143 is connected to the middle point of the condenser base is B>4and the control input of the key 144 is input 65 of the filter.

Frequency discriminator 42 (Fig. 9) may be made in the form of serially connected analog-to-digital Converter 145, speed meter 146 and circuit 147 comparison of codes, another group of inputs which are connected to the output of the sensor 148 nominal frequency value of the input of the discriminator is the input of analog-to-digital Converter 145, and output-output greater than or equal to the schema 147 comparison codes.

The driver signals the adjustment of the controlled generator 43 (Fig. 10) may be made in the form of the item 149, the output of which is connected to the input of the first element And 150, the input of the shaper is the input element is NOT 149 connected to the first input of the second element and 151, the second inputs of the And elements 150, 151 is connected to the generator output pulses 152, and outputs driver outputs are elements And.

The correlators 7-12 (Fig. 11) is executed in the form of a multiplier 152, the inputs of which are the inputs of the correlator and the output of the multiplier is connected to the input of bandpass filter 154, the output of which is the output of the correlator.

Satellite communication system that is targeted for this device is the t simultaneously to provide connections with several people in different directions and addresses (the principle of "each other").

In this case, all subscriber stations of the same type. Each of them can operate in mode, the Central station transmitting the synchronization signal, which are in synchronism other station and peripheral stations, when it is in the mode of reception of the synchronization signal to the Central station and the synchronization of their work provides the clock to the Central station. Receive mode clock and is addressed in this invention.

The structure of the synchronization signal, which is transmitted in the service channel, shown in Fig. 12.

Super-frame of the synchronization signal is 8C (TSP=8C) and is divided into 32 frames, each of which has a duration of TCR=250 MS. Each frame is divided into 15 cycles duration TC=16, (6) MS. He, in turn, consists of five frequency-time slots (positions) duration of Tonline=3, (3) MS.

In service frequency channel transmits signals to the Central (CA) peripheral (PS) stations, signals of employment information frequency channels and service signals for communication between stations.

The content of any cycle except the first, in the same way.

1. In the 1st cycle p is Auteuil to 14.4 kHz and the duration of the marker of 3.3 MS;

on the second and third time intervals information circular;

on the fourth and fifth time intervals signals of employment frequency-time positions in the information-frequency channel.

2. In the first cycle of any frame except the first, is passed:

on the first three frequency-time intervals information circular;

on the fourth and fifth frequency-time positions of the signals of employment frequency-time positions in the information-frequency channel.

3. In all cycles except the first, is passed:

at the first time interval of the synchronization signal CA transmission;

on the second and third time intervals, the signal communication between the subscribers (the ringtones);

on the fourth and fifth time intervals signals of employment frequency-time positions in the information-frequency channel 7.

Video service frequency channel (SCC) are functions Walsh, forming a space of orthogonal signals. The repetition rate of the Walsh function (clock frequency) is 57.6 kHz. The video signals are multiplied with a cyclic pseudo-random sequence (DSPS). Each cycle DSPS consists of 1024 elements, with the following cha SRP:

1. Singaporelovelinks.com CA (SP CA). After multiplying SP CA and Walsh functions N 1 (DC) is formed on the CA signal SSCAthat is transmitted to all stations on the network. It is transmitted by the Central station continuously except for those time intervals where the CA transmits the information circular, or ringing signals, or signals of employment. Any station when operating in the mode formed by the same synchronization signal SSCA.

2. Singaporelovelinks.com CA (SC SS). It is used to generate clock CCCAby which includes in synchronism transmission of the peripheral station. The signals CCPStransmitted at the first time intervals of cycles.

3. Information of the SRP. After multiplication of the information pseudorandom sequence with the information signal of any station produces an information signal, which can receive and process each station on the network as the information sequence for all stations the same.

Information pseudorandom sequence is multiplied by also signals the circular of information, with the ringing signals and signals of employment frequency-temporary the ACI CCPS.

The principle of operation of the device is as follows.

Sync is singaporelovelinks.com Central station (SP CA) is an almost continuous pseudo-random sequence with a period of 1.1 MS, clock frequency 921,6 kHz, the number of 1024 elements. Every 8 C for 3,3 MS signal superimposed on the square wave frequency of 14.4 kHz, forming a multiframe marker.

The task of the device is that during operation of the subscriber station as peripheral (receive mode) to provide a reliable determination of the synchronization signal to the Central station and to ensure the addition is followed by frequency and delay, to develop the multiframe marker and other signals to control the operation of the station.

The search feature noise-like signal is that the body area of uncertainty in time-frequency space is small. Therefore, the signal can be detected at a sufficiently close values of the frequency of the reference signal when the correlation detection method. It is also necessary to consider that in satellite communication systems, the frequency and the delay of the signal changes slowly. Therefore, the device is put in series-parallel detection method, susn the Noah frequency (28.8 kHz) and fed into the multiplier, to the other input of which is fed a reference signal with the same SRP, and accept. In the result of multiplying the coincidence of signals in time manipulation is removed, and a narrow-band filter is allocated monochromatic signal. The bandwidth of the filter determines the integration time of the signal is narrow-band filter. The amplitude of the signal at the output of the correlator depends on the degree of closeness in the timeline the received and reference signals. Therefore, after the detection and the additional integration over the interval equal to the duration of four DSPS, the output signal is fed to a threshold device. For faster search the device uses four parallel channel, wherein each one of the reference SRP delayed for one clock cycle relative to a reference SRP in the previous channel detection. The excess in the channel of the received signal above the threshold level provides a basis for making decisions about the presence of a signal. Such a construction of a channel detection with two stages of integration eliminates the necessity of selection of the carrier oscillation, up to a phase, that it is very difficult to implement.

The threshold level is formed in the additional fifth channel. He distinguishes. agodnym effect of the channel is the average level of the noise component of the correlation convolution of signals. Exceeding that level in any channel is an indicator of signal presence.

This effect is achieved only if the input signal is not only coincides with the reference, but the signal frequency close to the resonant frequency of the filter. Therefore, by rebuilding gatheredin you can achieve maximum output effect. Two-step integration allows you to resolve the contradiction between the requirement to provide a large accumulation interval and the need to measure the frequency in a wide frequency range. This allows you to make a frequency measurement on the output of the bandpass filter, the comparison of measurement results with the nominal value and fine-tuning of the lo frequency to the desired value. Therefore, the search frequency and the delay is a little sensitive. The measurement process can occur and if the match is partial accept and reference DSPS.

After detection in any of the four channels of the signal, the device enters auto-tracking frequency and delay, when switching channels so that the contour of post signal the signal of the fourth channel, enabled by the delay now between the second and third channel. In case of a short interruption of the received signal the state of the system synchronization is memorized, and when exceeding the failure signal greater than the set value, the search mode is resumed. The construction of the frequency and phase is possible only in the presence of the detected signal.

The device operates as follows.

In the initial condition generators 44 and 50 to produce a signal with a nominal frequency, their adjustment is missing. Clock generator 50 generates clock pulses which are received in the other blocks of the system, the information input key 48 and the clock input of the shaper 59. After it is started by a signal from input 61 the former is the expense of clock pulses and at the same time at the output 62 of a signal, which closes the key 48. Heartbeats begin to enter the clock inputs of the generators 45 and 46 begin to generate a pseudo-random sequence. The generator 45 generates singaporelovelinks.com SP, PS, and alternator 46 information singaporelovelinks.com PI. They are logically summed in the adder 60, which is formed by the sequence PI+SP, and arrive at one of comop (one for each channel detection) characterized in that on each subsequent output singaporelovelinks.com delayed by one clock cycle relative to the sequence in the previous output. The switch 57 delay use only one output, the delay is equal to the delay of the signal on the fourth output 38 of the switch 58. After the shaper 59 will be counted 1024 pulse it prohibits the passage of the next four clock pulses from generator 50 through the key 48. Thus changing the delay phase formed singaporelocalnews. The delay variation will be up until no signal is detected by the Central station or will not expire specified time search. From the outputs of the switch 58 and adder 66 singaporelovelinks.com arrive at the second input of one of the correlators 7-11.

The output signal from the dump receiver is fed to the input of the Converter 2, which converts the signal to a frequency 7020 MHz, amplified by the amplifier 3 and through an inverter 4 is the second transformation to the frequency of 28.8 kHz and after filtering and amplification filter 5 is fed to the correlators. Double frequency conversion of the input signal allows you to bring the intermediate frequent Lebane envelope.

Consistently connected correlator detector and integrator form four channel detection signal, and the channel formation of the reference voltage, in relation to which a decision is made about the detection signal consists of a correlator 11, the detector 21 and the integrator 22. While in any of the channel search signal will not exceed the reference voltage, there is a signal on the fourth output unit 23 and the output 26 of the driver 24.

In each of the detection channels using multiplier products 153 is removed manipulation of the input signal and band-pass filter 154 is the first integrator channel. Held the lower intermediate frequency signal allows you to perform band-pass filter with a very high q, his band is comparable with the duration of the SRP, which provides a good integrating filter properties and a sufficiently high signal-to-noise ratio at its output. The detectors 13, 15, 17, 19 and 21 are made in the form of amplitude linear detectors, so their output is reproduced correlation function signal. Re-integration using integrators allows you to extend the interval of integration for the duration of several of the SRP (in this case 4).

When exceeding in any Caen is sootvetstvuuschem the output 25 of the shaper, you receive a single signal, and the output signal 26 is set to zero. In the switches 57 and 58 is the switching delay of the SRP, and the imaging unit 59 includes a phase-locked loop circuit. The switching of outputs of the switches 57 and 58 carried by the following rule.

If the detection occurred in the first channel, the output 35 is connected to the output 36, the output 36 output 37 and the outlet 38 is connected to the output of the delay element 112, i.e., the fourth channel is the delay between the second and third channels. The first channel is not used.

If the detection occurred in the second or third channel, the delay does not change, and the fourth output 38 is connected to the output of the delay element 114, i.e., again for the delay forms the middle point.

If the detection occurred in the fourth channel, in its place connects the third channel, the third the second channel and the fourth channel is again connected to the middle point on the delay between the output of the delay element 116.

With the loss of signal detection channels and the signal at the input 26 is automatically restored to the original wiring of the outputs 35-38.

After switching process starts TNA output of the fourth channel. In the beginning of the process-locked loop bandwidth of the PLL is selected wider due to open the switch 143 in the filter 54. As soon as the signal at the output 254unit 24, the bandwidth of the filter is reduced. For the formation of the discriminatory characteristics of the signals taken from the output of the integrator 16 of the second channel and the output of integrator 18 of the third channel. They arrive at the discriminator 52, made in the form of the subtraction unit, and a differential signal is supplied to the fetch block storage. Signal with a clock output 65 shaper 59 is a signal capture unit 53 and the nulling filter 54, which after reset starts.

The output of filter 54 is supplied to the detector 55, which determines the maximum (peak) value of the input signal and the sign signal by comparison with a zero potential. When exceeding the zero level at the output of the circuit 139 comparison is formed of a single signal, otherwise, zero. These signals are fed to the input of generator 50 to determine the direction of the frequency adjustment. The magnitude of the adjustment is determined by the frequency of pulses from the output of the Converter 56 which converts the output signal from the detector 55. This ptx2">

The search signal frequency is as follows.

The signal on the output of the correlator 10 is fed to the input of the frequency discriminator 42, which with the help of analog-to-digital Converter 145 is converted to digital form and fed to the meter 146 frequency. With schema 147 code compares compares the measured and the nominal frequency value. The signal of the logic zero at the output of the circuit 147 comparison corresponds to the condition FMr.FISMand a signal of the logical unit to the condition FMr.FISM. Using the shaper 43 signal of the logic zero passes through the element And 150 on reducing the frequency of the controlled oscillator 44, and a signal of logical units through the element And 151 increases the value of the frequency generator 44, which may be performed by known circuits of frequency synthesizers.

The selection marker of the multiframe is carried out using a correlator 12, to the second input of which is the result of multiplying the SRP input 38 and signal generator 41. Resonance amplifier 30 and the detector performs the role of integrator, the signal which exceeds the threshold level set at the input 33, the threshold element 32 is used far is P CLASS="ptx2">

In block 23 the allocation of the maximum signal (Fig. 4) circuit 94, 99, 107 and 115 to produce a single signal at the upper output (as shown in the drawing), if the signal on the upper input more signal on the lower input. Otherwise, the signal on the upper input equal to or less than the signal on the lower input) single potential appears on the lower output schema comparison. The decoder 111 analyzes the state schema comparison and depending on it produces a signal on one of its outputs. The table of correspondence of the signals at the input and output of the decoder shown in Fig. 13. So always be open only one of the keys 96, 98, 101, 103, 104, while in the search mode will be opened key 104.

In the shaper 24 code signal (Fig. 6) input signal corresponding trigger set in the condition in which its forward end there is a single signal, and the other triggers with encoder and pulse shapers are translated into a condition in which their direct outputs is set to zero potential. Table of correspondence between input and output signals of the encoder 132 is shown in Fig. 14. The pulse shapers produce a short pulse on the front differential voltage n is eaten when the signal on the other input.

The switches 57, 58 delay (Fig. 5) delay in each of the elements are the same and equal to 0.5 t where t is the symbol duration of the SRP (heartbeat interval). In the search mode, the input signal 26 are closed keys 119, 122, 125 and 128. In the first channel delay SRP zero, in the second t in the third 2 t in the fourth 3 t When the signal on one of the inputs 25, the keys are switching channels in accordance with the above rule.

Shaper 58 control signals (Fig. 3) works as follows. shaper 59 control signals solves the following tasks:

in "search" mode prevents the passage of four clock pulses through the key 47 on the generators of the SRP with a period of 4TCOI;

after a predetermined time when the non-detection signal generates a signal "End of the visible";

upon detection of a signal in one channel stops restructuring delays and generates an internal signal permits adjustment of the clock frequency, which is carried out only when a signal is detected;

despite a threefold repetition of the detection signal generates the external signal SDI (signal detection);

when short-term loss of signal after fixen waiting the signal initial setup, which resumes the search mode.

In the initial state (Fig. 3) all counters are reset to zero, the timer is not running, the trigger 67 is installed in a state in which its inverse output signal has a logical unit that opens the corresponding input element And 69 and closing by the inverse of the input element And 68, the trigger 78 is installed in a state in which to direct the output signal has the logic zero, the closing on the corresponding inputs of the And elements 68, 69, trigger 83 is in the state in which to direct the output signal has the logical unit, the opening element And 80 on the corresponding input. The trigger 74 is installed in a condition in which a single signal is available on its inverted output and the key 47 is open.

As if no signal is detected at a single potential exists at the output 26 of the imaging unit 24, it passes through the elements And 80 and opens the corresponding inputs of elements And 68, 69.

The signal to start the search from the input 61 through the element OR 79 moves the trigger 78 in a condition in which a single signal with its direct access opens the corresponding input elements And 68, 69. And through the element OR 72 trigger 67 is translated in sostoyaniye element And 69.

Clock pulses are received through the element And 68 on the counter 75, the capacity of which is equal to 4nSRPwhere nSRPthe number of elements of the pseudorandom sequence. At the same time the first clock pulse from the output element And 68 translates the trigger 74 in a state in which a single signal with direct access permit the passage of clock pulses to the generators of pseudorandom sequence through the key 48.

The overflow signal of the counter 75, which bears the potential character, arrives at the shaper 73 pulses, which edge signal produces a short pulse, tipping the trigger 74, and the clock pulses through the key does not pass. At the same time the trigger 67 is transferred in a state in which a signal with its inverted output opens the item And 69 and closes the element And 68. Now the counter 70, the volume of which is equal to four. After overflow of the counter 70, the imaging unit 71 generates a short pulse through the OR element 72 moves the trigger 67 in a state in which a zero signal with its inverted output element And 69 closes and the item And 68 opens. First last pulse passed through the element And 68, tipped the trigger 74 and clock them sluchainyh sequences supplied to the correlators. This delay variation is periodically up until one of the four channels will not happen detection signal.

The counter 89, the volume of which is equal to four, said pulses Of PFP" corresponding to the beginning of the pseudorandom sequence. By flooding the imaging unit 90 generates a short pulse, which is output 29 is supplied to the reset integrators.

Upon detection of a single signal potential at the input 26 disappears, with inverted inputs open elements 84, 85, 86, removed the voltage at the input of the trigger 83 and the slice signal shaper 81 pulse generates a pulse, which sets the initial state of the counters 70 and 75 and close trigger 78 on the appropriate input elements 68, 69 and confirmed the initial state of the timer 82. Occurred end of the search mode and started the trim mode on delay. When the pulse from the output of the driver 90 receives the fetch block-storage and proportional-integrating filter through the open by the inverse of the input element And 84.

With the loss (the loss) of the signal of a single potential reappears at the input 26 of the driver, proceed to Element And 84, stopping mode-locked loop. With the output element And 80 signal opens the corresponding inputs of the And elements 68, 69, and a short pulse from the output of the shaper 81 generated edge signal at input 26, through the element OR 79 moves the trigger 78 in a condition in which a single signal appears on its direct output and the trigger 67 single signal appears also to direct the output. The search mode is resumed.

If the delay locked loop signal failure does not occur, then the element 88 is a match three pulses sequentially generated by the imaging unit 90. This is because the magnitude of the delay elements 91, 92 delay equal to the duration of the four SRP. As a result of coincidence output element And 88, a signal is generated detection information SDI. This signal is fed to the system output and simultaneously tilt the trigger 83, which allows starting the timer 82 and closes the item And 80 on the corresponding input.

Now, when short-term loss of signal and the emergence of the potential at the input 26 of resuming the search mode will not happen, because the element 80 is closed and the trigger 78 is placed in the state that opens algo testing the output signal from the timer through the open item OR 79 tilt trigger 78 and resumes the search mode. If before the end of the timer signal is resumed, the imaging unit 87 generates the momentum through the element OR 77 sets the timer to its original state.

Thus from the structure of the device and a description of his work can be seen that the appointment is implemented and specified technical result is achieved.

The source of information

1. Device synchronization of noise-like signals. Auth. mon. USSR N 576669, CL H 04 J 3/06, 1975.

2. Device synchronization of noise-like signals. Auth. mon. USSR N 634473, CL H 04 J 3/06, 1977.

3. Interference protection radio systems with complex signals /G. I. Tuzov, V. A. Sivov, V. I. Prytkov and others, Ed. by G. I. Tuzov. M. Chapman and hall, 1985, S. 129, Fig. 4, 12 (nearest equivalent).

Device for detecting and tracking the synchronization signal in satellite communication systems for receiving, containing the first frequency Converter, the first input by the information input device, the output of the first frequency Converter connected to the input of the amplifier high frequency, and a second input connected to the output of the controlled oscillator, a low pass filter, two pseudo-random sequence generator and four channels of detection is locked loop and key characterized in that it introduced the channel forming the reference voltage, consisting of serially connected correlator detector and integrator, channel selection marker synchronization, consisting of serially connected correlator, the resonance amplifier and a threshold element, the second frequency Converter, lo, the block selection signals, the driver code channel, a frequency discriminator, the frequency generator token, the multiplier, the signal shaper adjustment of the controlled generator, adder, two switch delay, the frequency divider pulse driver control signals, the generator frequency reference unit selection, storage, proportional-integrating filter, the absolute value detector and the Converter voltage frequency, and in each channel of the detection signal is entered consistently United detector and integrator, and the output of the correlator is connected to the input of the detector, and the output of the amplifier high frequency is connected to the first input of the second frequency Converter, a second input connected to the output of the local oscillator, and the output of the second frequency Converter connected to the input of the lowpass filter, the output of which is connected conjugation and selection channel marker synchronization the outputs of the integrators channel detection signal and the output of the integrator channel forming the reference voltage connected to the corresponding inputs of the block selection signals, the outputs of which are connected to respective inputs of the driver code channel, four outputs which are connected to respective control inputs of the first and second switches delay, the fifth control inputs which control input mode driver control signals connected to the output of the lack of detection signal shaper code channel, the fourth output of which is connected with the inlet of bandwidth proportional-integrating filter, an information input connected to the output of the sample-hold an information input connected to the output of the discriminator phase-locked loop, the first and second information inputs which are connected to the outputs of the integrators respectively the second and third channels of the detection signal, the reset inputs of the integrators channel signal detection and channel formation of the reference voltage is connected to the output of the Reset driver control signals, the input of the start of which is Fushimi output device, the reference input of the threshold of the threshold element of a channel selection marker synchronization is the corresponding input device and the output of the threshold element is output marker signal synchronization device, the generator output frequency marker connected to the first input of the multiplier, the output of which is connected with the second information input of the correlator channel selection marker synchronization, the output of correlator fourth channel detection signal is also connected to the input of a frequency discriminator, the output of which is connected to the input of the shaper signal adjustment of the controlled oscillator, the outputs of which are connected to the corresponding inputs of the controlled oscillator, the output of the proportional-integrating filter connected to the input of the detector absolute values, the information output of which is connected with the inverter input voltage frequency, the output of which is connected to the first managing input of the control clock generator, the second control input which is connected to the sign detector output of the absolute value, and a clock input controlled oscillator connected to the generator output frequency reference, output controlled oscillator is wreathes control signals, the first clock output of which is connected to the control input of the key, the output of which is connected to the input of the frequency divider pulses and clock inputs of the first and second pseudorandom sequence generators, the output of the first pseudo-random sequence generator connected to the first input of the adder and an information input of the first switch delay, four outputs which are connected to the corresponding second information inputs of the correlators of the four channels of the detection signal, the fourth output of the first switch delay is connected with the second input of the multiplier, the output of the frequency divider pulses connected to the second clock input shaper control signals, the output of the second pseudo-random sequence generator is connected to the second input of the adder and the information input of the second switch delay, the output of which is the output Information sequence" of the device, and the output of the adder is connected to the second information input of the correlator channel forming the reference voltage, the input signal recording unit sample-hold and input reading proportional-integrating filter connected to the second clock output which

 

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FIELD: radio engineering; construction of radio communication, radio navigation, and control systems using broadband signals.

SUBSTANCE: proposed device depends for its operation on comparison of read-out signal with two thresholds, probability of exceeding these thresholds being enhanced during search interval with the result that search is continued. This broadband signal search device has linear part 1, matched filter 2, clock generator 19, channel selection control unit 13, inverter 12, fourth adder 15, two detectors 8, 17, two threshold comparison units 9, 18, NOT gates 16, as well as AND gate 14. Matched filter has pre-filter 3, delay line 4, n attenuators, n phase shifters, and three adders 7, 10, 11.

EFFECT: enhanced noise immunity under structural noise impact.

1 cl, 3 dwg

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