Storage device with switchable structure

 

(57) Abstract:

The invention relate to computing and can be used in computing devices and systems for processing multi-dimensional arrays of data. The aim of the invention is to expand the functional capabilities of the device. The device contains modules 1 memory output 4 unit ready, the decoder 5, entry 7 select a memory module, the encoder 8, the inlet line 12 address line input 13 format that represent additional opportunities when forming the address of an arbitrary memory cell device. New device encoder 8, which allows for accessing arbitrary memory cell to use different address formats. 2 Il.

The invention relates to computer technology and can be used in computing devices and systems for processing multi-dimensional arrays of data.

A device containing blocks (modules) of memory, the same line of address inputs, control inputs, data inputs and data outputs of which are connected and are respectively lines of input addresses of the first group, the lines of control input, the line input is tificatio (ready) device and decoder, inlet line which are respectively lines of input addresses of the second group, and the outputs of which are connected with inputs of the selection module corresponding blocks (modules) of memory. The address of any element of a multidimensional array, the set of elements which are mutually clearly visible in many of the memory cells of this device can be represented in binary digit grid by a set of vectors that define the addresses of array elements in the corresponding dimension. With the address of any element of a multidimensional array in this device may only be presented in the same address format that allows for any two adjacent elements in an arbitrary dimension of a multidimensional array to refer to a single element at the address obtained by modifying the addresses of the other element to a constant value which is different for different dimensions of array [1]

However, this device does not allow for any two adjacent elements in an arbitrary dimension of a multidimensional array, the set of elements which are mutually clearly visible in many of the memory cells of this device, refer to the same item at the address obtained by modificirovana line inputs address, control inputs and input-output data which are interconnected and are respectively lines of input addresses of the first group, the lines of control input and line input-output device data, and outputs the readiness which are outputs of the readiness of the device, and the decoder, the inlet line which are respectively lines of input addresses of the second group, and the outputs of which are connected with inputs of module selection of the appropriate memory modules. The address of any element of a multidimensional array, the set of elements which are mutually clearly visible in many of the memory cells of this device can be represented in binary digit grid by a set of vectors that define the addresses of array elements in the corresponding dimension. With the address of any element of a multidimensional array in this device may only be presented in the same address format that allows for any two adjacent elements in an arbitrary dimension of a multidimensional array to refer to a single element at the address obtained by modifying the addresses of the other element to a constant value which is different for different dimensions of array [2]

However, this device does not pozwalaaaca one-to-one appears in many memory cells of this device, to refer to a single element at the address obtained by the address of another modification of a menu item.

The closest technical solution to the described invention is a device that contains the memory modules of the same line of address inputs, control inputs and input-output data which are interconnected and are respectively lines of input addresses of the first group, the lines of control input and line input-output device data, and outputs the readiness which are outputs of the readiness of the device, and the decoder, the inlet line which are respectively lines of input addresses of the second group, and the outputs of which are connected with inputs of module selection of the appropriate memory modules. The address of any element of a multidimensional array, the set of elements which are mutually clearly visible in many of the memory cells of this device can be represented in binary digit grid by a set of vectors that define the addresses of array elements in the corresponding dimension. With the address of any element of a multidimensional array in this device may only be presented in the same address format that allows for any two neighboring elemen modification addresses a different element to a constant, the value of which is different for different dimensions of the array.

This device does not allow for any two adjacent elements in an arbitrary dimension of a multidimensional array, the set of elements which are mutually clearly visible in many of the memory cells of this device, refer to the same item at the address obtained by the address of another modification of a menu item.

The aim of the invention is to expand the functional capabilities of the device.

This goal is achieved due to the fact that the device contains modules 1 memory eponymous line inputs, 2 control inputs and outputs 3 data which are interconnected and are respectively the lines of the control input and input-output data of the device, and outputs 4 readiness which are outputs of the readiness of the device, and the decoder 5 outputs 6 which is connected to the input 7 selection of relevant modules module 1 memory entered the encoder 8, the output line 9 of the first group and the output line 9 of the second group which are connected respectively with the same line inputs 10 addresses of modules 1 memory and with the lines of the input 11 of the decoder 5, and the inlet line 12 of the addresses of the first group, line whooi group, lines of input addresses of the second group and lines of the input format.

The address of any element Q-dimensional array can be represented in binary digit grid by a set of Q vectors, for which it is true that the value of the q-th vector, where q is an integer satisfying the condition

1q Q,

is determined by the value of the q-th index. The number of binary bits in the address i needed for addressing element Q-dimensional array can be determined by the formula

< / BR>
where iqthe number of binary bits in the address that is required for addressing the item in the q-th dimension of the array. The value of iqis an integer satisfying the condition

0 (iqlog2Dq)<1,qthe maximum value accepted q-th index. Obviously, in many memory cells of memory) can be one-to-one mapped many elements of a multidimensional array, dimension of which Q is defined by an integer satisfying the condition

1 Q M,

where M is the number of lines of the input memory address, if the number of binary bits in the address i needed for addressing element Q-dimensional array that satisfies the condition

1 i m


0 k M,

and, determined by the number of discharge address represented in the basic format corresponding to the low order of the q-th vector. Thus the q-th address format can be assigned a code format, the value of which is determined by the number of discharge address represented in the basic format corresponding to the low order of the q-th vector. Since the low order q-th vector can match any room category addresses represented in the basic format, in order to implement the q-th data structure in a memory, enough for this memory was a hardware implemented function of cyclic shift to the left of the address received at the input of the memory address, the argument of which is the number of digits k that is shifted address. As a fixed ordered set of objects and relationships between them forms the structure, and the structure objects can be considered the memory cells of the memory, to change the structure of memory is enough to change the arrangement of the lines of the address of the input address. Hardware implementation of the functions of cyclic shift to the left of the address input address memory argumentative device, allowing, if necessary, modify its structure. To switch patterns ZU (to allow selection of implemented data structures) requires that memory had input format for transmission in the memory the values of the format code. The number of lines of the input format, L can be set to an integer satisfying the condition

0 (log L2M) <1.

In Fig. 1 shows the structural diagram of predlog address which contains four address lines, where A0, A1, A2, A3 address inputs of the encoder, B0, B1, B2, B3 outputs of the encoder, C0, C1 input format encoder.

The device shown in Fig. 1, operates as follows.

To many memory cells of the device is one-to-one to represent the set of elements of a multidimensional array and use the ability to switch implemented data structures for efficiency calculation of the addresses of neighboring elements in arbitrary dimension of the array, you must select a base address format, and to determine all address formats, which only can be obtained by cyclically shifting to the right vectors addresses represented in the basic format. Then each address format must assign a unique value format code, equal to the number of bits in the address that you want cyclically shift to the right address, presented in a basic format to get the address in the address format. Moreover, the format of the address is selected as the base address format, you must assign a code whose value is zero.

Before accessing the device at the input 13 of the format of the encoder 8, which is the input format of the proposed device you selected for implementation during subsequent access to this device. The value of the format code should be maintained at the input device format, at least until completion of the subsequent references to this device.

When accessing the device at the input 12 address encoder 8 receives m-bit address, which is used in the proposed device address with the specified format, and output 9 encoder 8 input 10 modules 1 memory and to the input 11 of the decoder 5 receives respectively lower and upper bits of the addresses represented in the basic format. High-order bits of the address are the address of the M memory blocks. On one of the 6 outputs of the decoder 5 generates the select signal to the memory module, which is fed to the input 7 selection module, the corresponding module 1 memory, and permits the further spread of signals received at the input 2 of the control of this module 1 memory from a control input device.

When performing recording on line input-output device data serves data on inputs and outputs 3 data modules 1 memory and written to the module 1 memory, the number of which determines the decoder 5. When the procedure is executed, the read module 1 memory, the number of which determines the decoder 5, selects the line input is gotovnosti marks a period of employment of the relevant module 1 memory.

An example implementation of the encoder IC CK for the device, the input address contains four address lines, shown in Fig. 2.

Thus the ability to use different address formats when referring to the proposed device allows multiple memory cells of the device to display many elements of a multidimensional array so that for any two adjacent elements in arbitrary dimension of the array, you can calculate the address of one element by modifying the address of another item.

Storage device with switchable structure containing the memory modules of the same line of control inputs which are connected and are the lines of the control input device, the eponymous line of input-output data of the memory modules are interconnected and are lines of input-output data of the device, the line outputs ready memory modules are line outputs ready device, and a decoder whose outputs are connected to inputs of the module selection of the corresponding memory module, characterized in that it comprises an encoder that implements at the output of the encoder function cycle which shifts the address, set the input format of the encoder, the output line of the first group which is connected to the same lines of the address inputs of the memory modules, the output line of the second group of encoder connected to the same lines of the input of the decoder, the line of input addresses of the first group of encoder lines are input addresses of the first group of devices, the line of input addresses of the second group of encoder lines are input addresses of the second group of devices, inlet line format encoder lines are input format of the device.

 

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3 cl, 11 dwg

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2 cl, 23 dwg

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4 cl, 12 dwg

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