Device for controlling access of a terminal to the data bus

 

(57) Abstract:

The invention relates to the field of data transmission in multiplex channels of information exchange and can be used for access control stand-alone terminal to the data bus. The purpose of the invention is to enhance reliability. The device contains two sets of timers 3, 4, block 5 Comparators mismatch, block 1 of the selector switches, registers unit 2, two elements And 6.7. The device ensures the autonomy of the terminal to the data bus Protocol-based multiple access with carrier detection and collision avoidance, and has a high functional reliability due to the implementation of the device special algorithm signal allowing access terminal to the data bus, self-control and dynamic organization improve its capacity in the event of a failure. 7 Il.

The invention relates to the field of data transmission in multiplex channels of information exchange and can be used for access control stand-alone terminal to the data bus Protocol-based multiple access with carrier detection and collision avoidance.

In Fig. 1 showing the operation of the bus on the example of three terminals; in Fig.3 is a structural diagram of a device for controlling access of a terminal to the data bus of Fig.4 the algorithm of the function of the comparator of Fig.5 is a functional diagram of the device for controlling access of a terminal to the data bus of Fig.6 is a functional diagram of the comparator of Fig. 7 algorithm recovery device for controlling access of a terminal to the data bus.

The device is intended for use as a single unit stand-alone terminal multiplex channel of information exchange with distributed control communication channel (mkio RU). Mkio RU includes a stand-alone terminal (the terminal) and the data bus(1, 2, 3, 4). In this channel, each terminal has offline access to the data bus with collision avoidance due to the special access Protocol, which is implemented by this device.

The access Protocol is based on three functionally dependent timers: timer transmission, the synchronization timer and the timer of the terminal.

Timer transmission terminal starts when you start giving them your own information in the tire and count the interval, called the transmission interval TS during which the terminal HINOI data.

The synchronization timer is triggered interval TC (pause synchronization), which is the same for all terminals combined single bus. This timer is always triggered when there is a bearing on the data bus and the condition that the interval TC is not fulfilled yet.

The timer of the terminal processes the interval TT (pause terminal), is proportional to the number assigned to the terminal. Thus, the interval TT is unique for each terminal. The timer of the terminal is started only after timer synchronization and reset in all cases, the presence of the carrier on the data bus. The maximum interval TT should always be less than the limit for a given tyre interval TC.

The terminal is permitted access to the bus only after processing all of the timers, i.e., must be performed three conditions:

1) finished the countdown own transmission interval TA;

2) the period of time when the bus is no carrier, must be greater than or equal to the interval TC, i.e., over the count interval TC;

3) after the end of the interval TC should pass the time when the bus is no carrier, equal to their own interval TT.

There are two mode data bus: from time to time is.1.

Let when the power is turned on (time) timers transmission TP, TP2, TA3 and synchronization timers TC1, TC, TS respectively first, second and third terminals have worked their intervals, i.e., the conditions PP.1 and 2 (see above).

After that, run timers TT, TT, TT first, second and third terminals. TT first terminal fulfills your first interval (the time T1), i.e., the interval T T TT. At time T1 the first terminal starts transmission. This starts its timer transmission TP, reset timers, synchronization TC1 and terminal T, and timers T and T the other two terminals. At the end of transmission (time T2) and again allowed timers T and T and synchronization timer TC1 of the first terminal (TT cannot start because TC1 not counting the sync interval after the transmission of the first terminal). The first in time T3 will work the timer TT second terminal (as pause synchronization more pause terminal, any terminal of this tire), then the second terminal starts transmission, etc.

At the time T6 finishes last (third) terminal. At this point, all the synchronization timers and the timers are reset terminal and machinae the bot timer TT, however, the transmission of the first terminal to start can't, because you have not yet completed the countdown interval TP. Transmission begins at time T9. At the beginning of the transmission of the first terminal of the discharged spent terminals TT and TT other terminals. Then in turn get access to the bus the second and third terminals, etc.

If you increase the amount of information transmitted in the bus, the bus is overloaded and, if the total length of the message based on technological breaks is greater than the set transmission interval, the bus goes in aperiodic mode (see Fig.2). In this case, the interval between transmissions of the same terminal exceeds the transmission interval TS (the time interval between the moments T1 and T8 in Fig.2).

The structural scheme of the device for controlling access of a terminal to the data bus (Fig.3) consists of a block selector switches 1, block registers 2, two identical blocks of timers 3 and 4, block Comparators 5 mismatch and two elements 6 and 7.

The block selector switches 1 contains three groups of radio buttons, which allow you to set three vosmiseriyny code, each of which corresponds to a specific interval: the interval of transmission of the TA Pau the ditch contains three identical eight-bit register. These registers contains three codes, which are equivalent to the corresponding eight-bit codes installed in the unit selector switches 1. Codes with output registers are received at the inputs of the timer block 4.

Each block of timers 3 and 4 operates independently from each other and contains three schemes (timer) time intervals TA, TC, TT, the magnitude of which is determined in groups of selector switches 1 and register 2. Together blocks of timers 3 and 4 provide a duplicate count of each time interval. They have the appropriate clock inputs 8 and 9, which receives the impulses of the same frequency from two independent generators.

Input device 10 receives the signal a pause, indicating the absence of information transmission on the data bus. This signal is formed in the receiving part of the terminal and enters the blocks timers 3 and 4, resetting timers terminal and the synchronization timers.

During the preliminary eight-digit setup codes supplied for informational inputs 11, 12 and 13 of the system's random-access memory (ROM), recorded in the respective registers of the register unit 2. Recording is performed by applying a signal to the corresponding input of the block timers 3(4), received by corresponding information input unit of the comparator 5.

Block Comparators 5 consists of three separate Comparators mismatch. Each comparator measures the temporary misalignment between the two duplicate signals from a block of timers 3 and 4. If a temporary error is less than the set value, the comparator outputs a signal on the corresponding output unit 5. Otherwise, the signal at the output of block 5 is absent, and produces an error signal on the respective output of the error block 5. This low level signal passing through the element I, is supplied to the output control device.

In Fig. 4 schematically shows an operation algorithm of the comparator mismatch. T1 and T2 compared intervals, and T the set time of the error between the compared intervals. In case (a) is the condition for the validity interval, exhaust relay timers, and in case b) the condition is false interval.

The signal of high level from the output unit 5 are received at the inputs of the element And 6, the output 18 which is formed by the enable signal of the access terminal to the data bus. This signal arrives at the transmitter part of the terminal.

uchtala 19, 20 and 21, a switch 22, three register 23, 24,25, six Comparators 26-31, six counters 32-37, three comparator 38-40 mismatch, four trigger 41-44, nine items And 7, 45-52, four elements OR 53-56, six elements are NOT 57-62, two clock input 8 and 9, the input characteristic pause 10, three information input 11,12,13, three log entries 14, 15 and 16, the inputs initial setup 63 and reset the permissions transmission 64, the output resolution transmission 18 and the output control 17.

The synchronization timer unit timer 3 is built on the meter 32, the comparator 26, the elements AND 45, NOT 57 OR 53, trigger 42; timer transmission - on the counter 33, the comparator 27, the elements AND 47, NOT 58 OR 54; the timer of the terminal on the counter 34, the comparator 28, the elements 48 and NOT 59. The synchronization timer unit timer 4 is built on the counter 35, the comparator 29, the elements AND 49, 60, OR 55, trigger 44; timer gear to the counter 36, the comparator 30, the elements 50, NOT 61 OR 56; the timer of the terminal on the counter 37, the comparator 31, the elements 51 and NOT 62.

The comparator mismatch (Fig. 6) includes two counters 65 and 66, two flip-flop 67 and 68, eight items And 69-76, two elements 77 and 78, two synchronization input 79 and 80, two information inputs 82, 82, exit 83 and the error output 84.

The device operates in the following by the inputs 11, 12, 13. Signals to corresponding inputs of a record 14, 15 and 16 these data are recorded in the registers 23, 24 and 25. Then the signal at the input of the initial installation 63, sets the trigger 41, which leads to a set of triggers 42 and 44 and to the appearance of signals of high level outputs 81 and 82 of the comparator mismatch 38 and 39.

When there are no signals of a high level at the inputs 81 and 82 of the comparator mismatch, the counters 65 and 66 are in the reset state (see Fig. 6). Their inverted outputs are signals of a high level, respectively supporting elements And 71, 69 and 73, 70 in the open position. The times of occurrence of the signal of high level at the inputs 81 and 82 of the comparator mismatch counters 65 and 66 begin counting pulses on their counter inputs with respective inputs synchronization 79 and 80 of the comparator mismatch. The signal of high level from the output element 71 and the output element And 73 are received at the inputs of the element And 74. It opens, and a high signal at its output sets the trigger 67 in one state. The high signal is also present on the output element 75, and thus, at the output of comparator 83 mismatch potara mismatch duration of the high signal on the output of the element And 71(73) is determined by the moment of occurrence of the low-level signal on the inverted output of counter 65(66), i.e., when the latter has counted a certain number of pulses received at its counting input from receipt signal to the input 81(82). After that, the counter 65(66) is blocked by its own output signal received on the input element And 69(70). Thus, the duration of the high signal on the output of the element And 71(73) is determined by the ratio of the account of the counter 65(66) and the period of clock pulses received at the input synchronization 79(80) of the comparator mismatch. The duration of the high signal on the output element 71(73) corresponds to the set interval T in Fig. 4.

Thus, after the signal at the input of the initial installation 63 on the inputs 81 and 82 of the Comparators 38 and 39 simultaneously receive signals of high level. Comparators work, and their outputs 83 receive a signal of high level is input to the input element And 52. These signals are respectively the signs of accurate testing intervals TC and TP (the time THAT in Fig. 1 and 2). Input characteristic pause 10 is a low-level signal, indicating the presence of a pause on the data bus. Counters 32-37 begin counting pulses at the appropriate clock inputs 8 and 9 of the device is, 1 and 2). This comes at a time when the codes on the outputs of the counters 34 and 37 will follow the prescribed code output group selector switches 21 and the register 25. When this trigger Comparators 28 and 31 and the signal of high level from outputs of these Comparators are received respectively by the elements NOT 59, 62 and to the inputs 81 and 82 of the comparator 40. The low level signals from the outputs of the elements are NOT 59 and 62 block, respectively, the elements 48 and 51, which will lead to the shutdown of the counters 34 and 37. When satisfactory conditions (see above) triggers the comparator 40. The result at its output 83 a signal of high level, the And gate 52 is opened and a high signal at its output resets the trigger 41, 42, 44, counters 33 and 36 through the element And 46 (if the circuit breaker is closed 22) and sets the trigger 43. The output of this trigger is generated, the signal transmission solutions are coming on the output device 18. On the 83 outputs of the Comparators 38 and 39 and the output element And 52 are formed in the low level signals. The low-level signal is supplied through the element And 46 to direct reset inputs of the counters 33 and 36 timers transfer that from this moment begins the countdown of the transmission interval. The high signal from the output resolution transmission shall oment T1 in Fig. 1 and 2).

During the transmission period of the information signal at the input of the characteristic pause 10 all terminals connected to the bus is at a high level. The counters 32, 34, 35 and 37 synchronization timers and timers terminal are in reset.

After transmitting information from the transmitting side terminal to the reset input resolution transmission 64 is a high signal, which resets the trigger 43. After the silence on the bus data signal characteristic pause input device 10 enters a state of low level and remains in this state as long as the pause takes place (the period T2-T3 in Fig. 1 and 2). Since the installation of this signal in the low level start working the counters 32 and 35 of both timers synchronization. The counters 34 and 37 of both timers terminal can not work, because the output 83 of the comparator 38 is a low-level signal.

During the interval T2-T3 on a similar algorithm works for the timer of the terminal in the next room terminal, which then starts data transmission on the data bus (the period T3-T4). So it will be up until the last terminal does not transmit their information. To this point in time (T6) triggers 42 and 44 and the counters 32 and 35 half is otali your interval timers sync all terminals, will be set triggers 42 and 44. The signals of the high level outputs of these triggers are received at the inputs 81 and 82 of the comparator 38. He fires, and the high-level signal from its output 83 is supplied to the elements 48 and 51. If on the bus, there is no data transmission, the counters 34 and 37 timers terminal start counting pulses on their counter inputs respectively from the outputs of the elements 48 and 51 (time T7 in Fig. 1 and 2). Upon expiration of the interval TT trigger Comparators 28 and 31 of the first interval. The signals of the high level outputs of these Comparators, respectively:

1) make the stop counters 34 and 37;

2) are fed to the inputs 81 and 82 of the comparator 40, the output of which appears a signal of high level. If by this time the timer transmission counted out their interval TP, the output of comparator 39 also present a high signal. In this case, the output element And 52 will receive a high level signal and the first terminal will allow the transfer of information (time T8 in Fig. 2). If the interval TP not imputed (time T8 in Fig. 1), the enable signal transmission to the output device 18 will be missing. He will only appear at the time T9, when the timer transmission will calculate the interval TP and output comparat

The previously discussed operation of the device, suggesting that the duplicated timers work out the intervals that satisfy the occasion (a) in Fig. 4, when , in which the trigger comparator mismatch. Consider the case b), when . In this case, there is a low level signal at the output of the error comparator 84 mismatch (see Fig. 6). This happens as follows. The high signal received at any of the inputs 81 and 82 of the comparator mismatch, passing through the element OR 77, is supplied to the reset input of trigger 68 (see Fig. 4B). After counting interval T any of the counters 65 and 66 low level signal with their inverted outputs passing through the element And 72, is fed to one input of the OR element 78. To the other input of this element receives the low level signal from the output of the trigger 68. As a result, the output of the element OR 78 will receive the low level signal input to the output of the error comparator 84. If this signal is missing, because the trigger 68 is installed in one state a high signal received at its input set to the output of the comparator 83. This installation will occur before the appearance of the low-level signal at the output of the element And 72 (see Fig. 4A) that does not result in pravlenie access terminal to the data bus and its scope define the strict requirements for reliability. Given the complexity of the access Protocol, a large number of terminals on the same bus (up to 120), the use of mkio RU in onboard systems, the requirement to improve the health of the terminal is an important task. To solve it we need to use the terminal functional blocks capable of self-control and dynamic recovery. These requirements satisfies considered here, the device for controlling access of a terminal to the data bus.

The algorithm recovery device in the terminal shown in Fig. 7. The low level signal from the output of the control device 17 enters the status register terminal, which sets the bits of the control device. The controller of the terminal analyzes this bit and if the system executes the firmware reinit device for controlling access of a terminal to the data bus.

Device for controlling access of a terminal to the data bus, containing six counters, six Comparators, three register, four trigger, three comparator mismatch, eight elements And four elements, OR six elements do NOT switch, three groups of selector Pericles And with the first inputs of the first synchronization, the second and third Comparators mismatch, the input characteristic pause device is connected to the reset inputs of the first, second, third and fourth counters, input the initial installation of the device is connected to the input of the first trigger reset input resolution transmission device is connected to the reset input of the second trigger whose output is the output resolution transmission device, the second clock input of the device connected with the first inputs of the fourth, fifth, and sixth elements And with the second synchronization inputs of the first, second and third Comparators mismatch, the first, second and third information input devices are connected respectively with the information inputs of the first, the second and third registers, the outputs of which are connected respectively to the first inputs of the first, second and third Comparators, the information outputs of the first, second and fifth counters connected with the first inputs of the fourth, fifth and sixth Comparators, respectively, the output of the fourth comparator connected to the first input of the first element OR the input of the first element, the output of which is connected to the second input of the first element And the sixth output of the comparator is connected to the first vhodna And the output of the fifth comparator connected to the first information input of the third comparator mismatch and the entrance to the third element, the output of which is connected to a second input of the third element And the outputs of the first, third and second elements And are connected respectively with the counting inputs of the first, second and fifth counters, the output of the first comparator connected to the first input of the third element OR with the fourth input element And the output of the second comparator connected to the first input of the fourth element OR to the input of the fifth element, the output of which is connected to a second input of the fifth element, And the output of the third comparator is connected to a second information input of the third comparator mismatch and to the input of the sixth element, the output of which is connected to a second input of the sixth element And the outputs of the fourth, fifth, and sixth elements And are connected respectively with the counting inputs of the third, sixth and fourth counters, information outputs of which are connected to second inputs of the first, second and third Comparators, respectively, direct the output of the first flip-flop is connected to the second inputs of the first, second, third and fourth elements OR, the outputs of which are connected to zootecnia, the input set fourth flip-flop and the second information input of the second comparator mismatch, the direct outputs of the third and fourth triggers are connected respectively with the first and second information inputs of the first comparator, the error information output of which is connected to the first input of the seventh element, And third inputs of the third and sixth elements And information outputs of the second and third Comparators mismatch connected with the second and third inputs of the seventh element And whose output is connected to the input of the second trigger, the reset inputs of the first, third, and fourth trigger and to the first input of the eighth element, And the first group of first contacts, the second and third groups of the selector switch and the first switch contact connected to the zero potential bus devices, the second group of contacts of the first, second and third groups of selector switches and a second switch contact connected respectively with the second group of inputs of the fourth, fifth and sixth Comparators and a second input of the eighth element And whose output is connected to the reset inputs of the fifth and sixth counter, and the comparator mismatch with the Oia is connected to the reset input of the first counter, with the first inputs of the first and second elements And the second information input of the comparator mismatch is connected to the reset input of the second counter, the second input of the second element And to the first input of the third element And the output of the second element And is connected to an inverted reset input of the first flip-flop, and to the first input of the fourth element And the first input of the timing comparator mismatch connected to the first input of the fifth element And whose output is connected to the counting input of the first counter, the output of the first counter is connected to the second inputs of the first and fifth elements And, the second synchronization input of the comparator mismatch connected to the first input of the sixth element, And whose output is connected to the counting input of the second counter, the output of which is connected to the second inputs of the third and sixth elements And the outputs of the third and first elements And connected with the first and second inputs of the seventh element And whose output is connected to the input of the first trigger, the output of which is connected to a second input of the fourth element And whose output is the output of the comparator mismatch, characterized in that the comparator input a second trigger, the eighth element And two elements OR the being is connected to the first input of the first element OR the first and second inputs of the second element OR is connected respectively with the first and second information inputs of the comparator mismatch, the inputs set and reset the second flip-flop connected respectively with the output of the comparator mismatch and the output of the second element OR the output of the second trigger is connected to the second input of the first element OR whose output is the output of the error comparator mismatch, and the device contains the ninth item, the first, second and third inputs of which are connected respectively to the inputs of the error of the first, second and third Comparators mismatch, the output of the ninth element And an output control device, the first the second and third inputs of the recording device are connected respectively to the inputs of the first, second and third registers.

 

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