A persistent storage device

 

(57) Abstract:

The invention relates to semiconductor integrated circuits of type base plate containing memory cells, arranged in rows and columns and read-only. These cells are divided into first and second groups containing transistors of the first and second types of conductivity. When this semiconductor memory device includes means for decoding the address management of rows and columns, designed to select in response to a column select signal, an output of the first or second groups. 3 C.p. f-crystals, 2 Il.

The invention relates to a permanent storage device for semiconductor circuits type base plate (matrix of logic elements) containing memory cells, arranged in rows and columns, and a read-only, these memory cells are divided into first and second groups containing transistors of the first and second conductivity types, respectively, and mentioned semiconductor circuit contains selector column is intended to select, in response to a column select signal, an output of the first or second group.

Semiconductor integrated circuit sa Takahashi,

particularly Fig.15. The article describes the schema type of a matrix of logic elements, which is of type base plate. In General, semiconductor integrated circuit type base plate contains a number of columns of the basic cells, which are located one opposite the other, the communication channels are located between the columns on the Central part of the semiconductor circuit. Recently semiconductor circuit type base plates are available with the so-called "logic elements" (also related to ductless matrix of logic elements); for example, see the article "The CMOS Gati Forest: An efficient and Flexible High-Performance Asic Desigh Environment", by M Beunder et al b "1EEE Journal of solide-staticircuits", VOL 23, No. 2, April 1988, pp 387-399,

where the basic cells are present in the Central part of the semiconductor circuit and the communication channels are formed across the base of the cells. Semiconductor integrated circuit-type base plate with many logical elements" integrates large-type cells, because the communication channels occupy little space or do not take up additional space. Mentioned publication Takahashi describes (see especially Fig.15) permanent memory (ROM), implemented mate with n channels and a second group of memory cells with p-channels. The memory cell n-channel or p-channels are selected by the column decoder.

The aim of the present invention is to provide an integrated circuit type of the base plate (gate array) that contains the diagram of the read only memory cells, in which the amount of chip area occupied by the connecting conductors for read only memory, is reduced compared to the known level, and the number of memory cells and the minimum size allowed by the technology of manufacturing integrated circuits have a fixed preset value.

This objective according to the invention is achieved in that the inputs of the first and second groups of memory cells in the same row are interconnected to receive a common signal selection number, provided the device to select one row of memory cells or the first or second group of memory cells. Since the inputs of the first and second groups of memory cells are connected, one transmission line of words sufficient to control the first and second groups of memory cells arranged in the same row. Therefore, in contrast to the scheme disclosed in the above publication Takahashi, which requires a separate transmission line to control the first and second groups of cells padamati. The degree of integration of cells on the surface of the semiconductor, therefore, increases. Due to the presence of these devices and the choice of the number, according to the invention, and the device selection column can be selected one memory cell of the first group and the second group of memory cells.

Image (alternative embodiment) semiconductor integrated circuit according to the invention is characterized by the fact that for each row the device includes an inverter and a switching element for supplying the inverted or non-inverted signals of the selection range, depending on the address signal. Memory, therefore, can be selected in the first or in the second group.

Another image of the semiconductor integrated circuit according to the invention differs in that the inverter and the switching element in series are formed using XOR circuit. Scheme with XOR implies attractive performance of inverter with attached switch in the row.

The following image of the semiconductor integrated circuit according to the invention differs in that the device selection column also receives the address signal during operation. And is Amati.

Another image of the semiconductor integrated circuit containing a controlled device for pre-charging to charge and discharge outputs of the first group and to discharge and charge outputs of the second group respectively according to the invention differs in that the semiconductor circuit includes a managed device selection for connecting the memory cells to a power supply terminal, and a device for pre-charging and the device sample operate in opposite phases during operation. As a device for pre-charging and the device samples are out of phase, any short circuit currents from the first to the second terminal of the power supply through the memory cell, therefore, is prevented during the pre-charge. Consequently, leakage currents, if they ever will be, will be very small, and the current consumption semiconductor integrated circuit according to the invention is low.

In Fig.1 shows a ROM according to the invention; Fig.2 the diagram in the coordinates of the voltage/time of the two signals occurring in the circuit shown in Fig.1.

Fig.1 shows a semiconductor integrated circuit according to the invention. Poluprovodnikov, from 21 to 24 and 31 to 34, each of which is a MOS transistor with a channel of n-type. The second block includes transistors 41 to 44, 51 to 54 and 61 to 64, each of which is a MOS transistor is p-type. The semiconductor circuit further includes a decoder rows 3, the column decoder 4, four of the inverter 11 to 14, four switches 1 through 4, the six transistors of the preliminary charging 19, 29, 39, and 69, each of which is a MOS transistor is n-type, two sampling transistor 100 and 200 related to the MOS transistors of n-type and p-type respectively, and six transistors select the column 10, 20, 30, 40, 50 and 60, each of which is a MOS transistor is n-type. The transmission line of words W1 associated with the gates of transistors 11, 12, 31, 41, 51, 61, which are arranged in the same row. The transmission line of words W2 associated with the gates of transistors 12, 22, 32 and transistors 42, 52, 62. The transmission line of words W3 associated with the gates of transistors 13, 23, 33, 43, 53, 63 and the transmission line of words W4 associated with the gates of transistors 14, 24, 34 and 44, 54,64. Output lines V1, V2, V3 and V4 decoder series 3 contact through the respective switches S1, S2, S3 and S4 to the transmission lines of words W1, W2, W3 and W4 respectively. Output lines V1, V2, V3 and V4 decoder of the rows associated with the corresponding Gushie inverters 11, 12, 13 and 14 (the position 2 of the switches S1 through S4). Switches c S1 through S4 are controlled by an address signal A3. The decoder series 3 receives address signals A4 and A5, column decoder 4 receives the address signals A1, A2 and A3. The sources of the MOS transistors are n-type with 11 to 14, the sources of the MOS transistors are n-type with 21 to 24 and the sources of the transistors are n-type A31 34 are connected with the supply wire which is connected with the second terminal of the Vssthrough the MOS-transistor switching n-type 100. The gate of the transistor switch 100 receives the signal sample fs. The sources of the transistors 41 to 44, the sources of the transistors 51 to 54 and the sources of the transistors 61 through 64 are connected with the supply wire which is connected to the first supply terminal VDDthrough the MOS transistor switch p-type 200. The gate of the transistor switch 200 receives the signal pre-charges fp. Line of bits b1, b2 and b3 are connected through the respective transistors preliminary loading of 19, 29 and 39 with the first supply terminal VDDmentioned transistors pre-charging signal pre-charges fp. Line bits b4, b5 and b6 are connected through the respective transistors preliminary charges 49, 59 and 69 from the second supply terminal Vp. Line of bits b1, b2, b3, b4, b5 and b6 are connected through the respective transistors 10, 20, 30, 50 and 60 with the common data line DL. The gates of transistors 10, 20, 30, 40, 50 and 60 receive the selection signals from the column decoder 4. Depending on the programmed information in memory in block 1 or block 2, the drain of the transistor in the block 1 or block 2 is connected to the associated bit line or not. Stoke, for example, transistors 13 and 14 in Fig.1 is connected to bit line b1, as shown by the cross at the intersection of flow and lines of bits. Stoke, for example, transistors 11 or 12 is not connected to the bit line b1.

The operation of the circuit shown in Fig.1 will be further explained with reference to the diagram of the voltage/time shown in Fig.2.

By way of example will be described first reading information from the memory cells in the block 1 and then read from memory cells in block 2.

Reading transistor cell 22 will be described using an example.

Before reading the memory cell (transistor) in block 1 or block 2 pre-charged line bits 1 through 6, i.e., the bit line is charged using the transistors 19, 29 and 39 and a logical high signal pre-charges fpto a value equal to or approximately itov b4, b5 and b6 are discharged using transistors 49, 59 and 69 and a logical high signal pre-charges fpto a value equal to or approximately equal to the supply voltage Vss.

The decoder rows 3 and the column decoder 4 are devices of a known type. For decoder series 3 this means that for an output line, the output line has a logic high voltage, while the other output lines contain a logical low voltage. The same applies to the column decoder 4, i.e., only one transistor of the transistors 10, 20, 30, 40 and 60 is selected by a logic high signal.

To select MOS transistor cell n-type 22, after pre-charging, therefore, the output line V2 is a logical high and the other output lines V1, V3 and V4 are logic low. Switches S1 through S4 are in position 1 when the cell is selected in block 1, the above-mentioned signals are controlled by an address signal A3. The address signal is also communicated to the column decoder 4, so that the column decoder 4 selects, under control of a logic signal A3, or one of the transistors 10, 20 and 30, or one of the transistors 40, 50 and 60. When the selection transistor 22 in block 1, the column decoder 4 is Ala sampling fsduring a read transistor 22 (after pre-charging), as shown in Fig.2, the source of transistor 22 is connected with the supply terminal Vss. Since the drain of transistor 22 is connected with the bit line b2, marked with a cross in Fig. 1, the bit line b2, which has a positive pre-charged, discharged through the transistor 22 and goes to a logical low level. Since transistor 20 is also selected, the data line DL also goes to a logical low level. However, when the selection transistor in the block 1, the drain of which is associated with its corresponding bit line (e.g., transistor 23), the data line DL takes a logical high value is due to the fact that related to it (pre-charged), the bit line is not discharged.

The future has a place for cell selection MOS transistor is p-type in unit 2. Before selecting transistor cell line bits b4, b5 and b6 completely or almost completely discharged through transistors for pre-charging 49, 59 and 69 and a logical high signal for pre-charging is fpas already described. When there is then a logical low signal pre-charges fpMOS-transistor p-t the following represent the correct address signals A4 and A5 for choice, for example, cells of the MOS p-type transistor 52 output line V2 goes to a logical high level and output lines V1, V3 and V4 are switching to a logic low level. Switches S1 through S4 position 2 under the influence of the address signal A3 selecting transistor cell unit 2. As a result, the signals on the output lines V1 through V4 are inverted and sent to the transmission line of words W1 through W4, respectively. Therefore, the lineage of the words W1, W3 and W4 are the logical units and the transmission line of words W2 is a logical zero, so choose cell MOS transistors are p-type 42, 52 and 62 in the block 2. As the output from the flow cell, the MOS p-type transistor 52 is not connected to the bit line b5 shown in Fig.1 by the absence of a cross at the intersection of flow and the corresponding bit line, the transistor 52 does not conduct current, and the bit line b4 is not charging. On the basis of the address signals A1 to A3 column decoder 4 selects the transistor 50, so that the bit line 45 is connected with the data line DL. Therefore, the level on the data line logic low.

If instead of the transistor cell 52 in the above example were selected transistor cell 53, was charged line bits b5 because of the connection of the drain of the s at the logical high level.

As a preliminary charging and selecting bit lines in the diagram shown in Fig. 1, is out of phase, short circuit currents from the supply terminals VDDpower supply terminal Vssthrough or memory cell MOS-FET n-type in block 1, or a memory cell MOS-transistor p-type in unit 2 is prevented, so that the current consumption circuit according to the invention is low.

The function of one or more inverters 11 to 14 and connected switches S1 or S4 can be implemented, for example, by XOR circuit. The signal on the output line V ( V1, V2, V3, or V4) and the address signal A3 in this case form the input signals, and the signals connected to the lineage of the words W (W1, W2, W3 or W4) form the output signal of the XOR circuit.

Of the known technical solutions, it follows that the image of the ROM according to the invention, shown in Fig.1 is only one of many possible images. Shows the ROM, which is divided into 4 rows and 6 columns, serves only to illustrate the operation of the circuit. The number of rows and columns in the schema according to the invention can be arbitrary. It is obvious that the circuit according to the invention can also be used as the which are arranged in the same row of the diagram.

To achieve this, the corresponding bit line must be connected to separate data lines DL1, DL2, and so on, so that the content of the memory can be read in parallel.

1. A persistent storage device containing a first matrix of first memory elements performed on the transistors of the first conductivity type, each transistor has a control electrode connected to one of the groups of the first numeric tire, and a current channel connected to the corresponding one of the groups of the first bit of the tire, the second matrix of the second memory elements performed on the transistors of the second conductivity type, each transistor has a control electrode connected to one of the second group of numerical tires, and a current channel connected to the corresponding one of the groups of the second bit of the tire, means for decoding the row address control, outputs connected to the first and second groups of numerical tires for selective excitation of first and second memory elements under the address control means for decoding column address control outputs connected to the groups of first and second bit buses to selectively connect the first and second elements is s numeric tire electrically connected to a corresponding one of the second group of numerical tires.

2. The device under item 1, characterized in that it contains means parallel preparada first and second bit buses.

3. The device under item 1, characterized in that the means for decoding row contains the row decoder with a group of inputs of the decoder for receiving bits in the address line and a group of outputs of the decoder for the excitation of one of the numeric tire, a group of inverters, each of which has an inverter input connected to the corresponding output of the decoder, the group reinvestiruja elements, each of which is connected to the corresponding output of the decoder in parallel to the corresponding inverter, a group of switches, each of which provides a connection or a respective inverter or the appropriate einverseremove element corresponding to the first numerical bus running additional address bits.

4. The device under item 1, characterized in that the means for decoding row contains the row decoder with a group of inputs of the decoder for receiving bits in the address line and a group of outputs of the decoder for the excitation of one of the numeric tire, the group of logical XOR, each of which has a first input connected to soundy corresponding to the first numerical bus.

 

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