System for the transmission of discrete information

 

(57) Abstract:

System for the transmission of discrete information relates to communication technology. The system includes a transmitter connected in series with the antenna, the buffer memory, encoder, modulator, amplifier and antenna. The modulator is connected to the generator carrier frequency, and the modulator generator of pseudorandom sequences, the second output of which is connected through a frequency multiplier and a key with a buffer memory. The receiver includes a serial connected the antenna, amplifier, demodulator, coherent detector, solver, the decoder error-correcting code, the receiver information. To the first and second inputs of the demodulator is connected the device to search for and maintain synchronism, the second output of which is connected through a frequency multiplier and the key to the device frame synchronization. In addition, between the two inputs of the coherent detector is enabled restore device carrier frequency. The invention allows to reduce the time of transmission of discrete information, to simplify the system for transmitting digital information to enhance immunity. 1 Il.

The invention relates to communication technology and can be used in systems to which signalov and to combat the effects of intentional interference.

A known system for transmitting binary information signals for U.S. patent N 4229821, NCI 375-53. This system contains a transmitting side of a source of information signals, the clock and carrier frequency, modulating cascade, and at the receiving side input stage circuit of the reference carrier demodulation scheme, a scheme of generation of the reference clock signal, the regeneration scheme, combinational logic circuit. The disadvantages of this system are the relative complexity, a great time joining in synchronism caused by the necessity to synchronize the carrier and clock frequencies.

Closest to the technical essence and the achieved effect is a system of discrete information transmission, is described in J. K. Holmes. Coherent Spread Spectrum Systems. Krieger Publlshing Company. Malabar. Florida. 1990, p. 624.

The known system includes (see Appendix) as part of the transmitter is connected in series source of information, the encoder, the first and second modulators, the amplifier and the antenna, with the first modulator connected to the oscillator carrier frequency, and the second modulator connected to the generator of pseudorandom sequences (SRP). The receiver system includes sequentially connected antenna, amplifier, dem is the second inputs of the demodulator enabled device to search for and maintain synchronism, between the first and second inputs of the coherent detector enabled device recovery and phasing of the carrier, between the first and second inputs of a casting device includes a selector clock frequency, the second output of which through the device frame synchronization is connected to the decoder for error-correcting code, the input is additionally connected to the device frame synchronization. Encoded by the encoder signal performs a first modulation carrier frequency, and then is subjected to modulation of elementary pulses (chips) pseudo-random sequence, is amplified and radiated by the antenna. At the receiving side, the received signal is amplified, is fed to the device and maintaining synchronism between the receiver and the reference signal SRP. Device search and maintain synchronism of the SRP is widely known (see for example, A. I. Alekseev, A., Sheremetiev, G. I. Tuzov, B. I. Glazov, "Theory and application of pseudo-random signals", publishing house "Nauka", M. 1969, Fig. 6.7, 6.8, 6.12, or "Noise-like signals in communication systems" Ed. by Pestryakova Century B. M. Owls. radio, 1973, Fig. 5.5.1, Fig. 5.6.2) and, as a rule, include the discriminator delay generator SRP and controlled the clock. When reaching time you synchronize, the t in the demodulator pseudo-random modulation of the received signal and the recovered narrowband signal is sent to the device recovery and phasing of the carrier and a coherent detector, where is the coherent detection of the received signal using the recovered carrier. Proyektirovanii signal is fed to the selector clock frequency (WH) and solver (RU) for making decisions about the received signals at the points specified clock synchronization with WH. With a casting device of the regenerated signals arrive simultaneously on the device frame synchronization and decoder error-correcting code, with which the information data is received by the information receiver. The disadvantages of the prototype is a great time joining in synchronism, due to the need to consistently implement the first synchronization phase of the SRP, then the clock synchronization. In addition, the accuracy of clock synchronization implemented WH, low, requires the introduction of a device WH at the reception.

Thus, the present invention is the creation of a system for the transmission of discrete data with a higher performance while simplifying device.

The problem is solved as follows.

In a system for transmitting digital data containing the transmitter source is the operators of the carrier frequency and the SRP, connected to the first and second modulators, respectively, and the receiver is connected in series with the antenna, amplifier, demodulator, coherent detector, solver, the decoder error-correcting code and an information receiver and, in addition, the device search and maintain synchronism included between the first and second inputs of the demodulator, the carrier recovery block that is included between the first and second inputs of the coherent detector, the device frame synchronization, the first input connected to the first input of decoder error-correcting code, and output to the second input of the decoder error-correcting code, additionally introduced into the second transmitter output from the generator of the SRP in the form of a decoder of the beginning of the SRP, which appear pulses with a repetition period of the SRP, the buffer memory, the frequency multiplier and the key, and a buffer memory connected between source of information and coder, and its second input through the key and the frequency multiplier associated with the second generator output of the SRP. In the receiver inputs of the second output from the generator SRP device search and maintain synchronism in the form of a decoder of the beginning of the SRP, which appear pulses with a repetition period of the SRP, the multiplier is often the lines of synchronism and the first input key, the second input is connected with the second output of the generator SRP device search and maintain synchronism, and the key is associated with the second input of the casting device and the second input of the frame synchronization. As will be shown below, the introduction of the system of the second outputs of the generators of the SRP, frequency multipliers and keys will allow you to increase performance by eliminating the time occurrence in synchronism to clock frequency. In addition, because of the system displayed the selector clock frequency, which is harder than the second outputs of the generators of the SRP, the multipliers and the keys, simplified system design. An additional effect is to increase the noise immunity of the system, as in the proposed system, the type of transmitted information does not affect the immunity of clock synchronization.

The invention is illustrated in the drawing, which shows the proposed system for the transmission of discrete information. System for transmitting digital data includes a transmitter connected in series source 1, the buffer memory 2, the encoder 3, the first modulator 4, the second modulator 5, the amplifier 6, an antenna 7. The modulator 5 is connected to the generator 8 SRP, and to the modulator 4 poulsom the beginning of the SRP, connected through the frequency multiplier 10 and the key 11 with the second input buffer memory 2 and the second input key 11. The receiver of the proposed system contains consistently connected the antenna 12, an amplifier 13, a demodulator 14, a coherent detector 15, solver 16, decoder error-correcting code 17, a receiver 18. Between the first input and the second input of the demodulator 14 is enabled devices to search for and maintain synchronism 19, the second generator output SRP which, issuing periodic sequence of pulses beginning of the SRP, through the frequency multiplier 20 and the key 21 is connected with the second input of the frame synchronization 22, the first input connected to the first input of decoder error-correcting code, and output to the second input of the decoder error-correcting code. The recovery block carrier frequency 23 connected between the first and second inputs of the coherent detector 15.

The operation of the device is as follows.

On the transmitter information from the information source 1 is written into the buffer memory 2 with its clock speed of its instabilities or force with a nominal clock frequency when the possibility of conflicting junction (see e.g. the source information 1. The copying of information from the buffer memory 2 to the encoder 3 is performed by the clock pulses of frequency f = 1/, where the nominal length of the information bits (without instabilities) coming from the second pulse generator output SRP 8 to the input of the buffer memory through the frequency multiplier 10 and the key 11 or, in the particular case, directly through the key 11. The repetition period of the SRP is chosen equal to TSRP= R where R is a positive integer (R1). The multiplication factor of the multiplier is equal to R. Thanks pulses at the beginning and end of the period of the SRP supplied from generator SRP 8 to the inputs of the multiplier 10 and the key 11, always coincide with the fronts of the information bits. So at the reception, there is no need in a special CELL, as its function is performed by the device search and maintain synchronism SRP 19-added output from the generator SRP of this device and the frequency multiplier 20 key 21. If R=1, the duration of the SRP exactly coincides with the length of the information bits and the need for frequency multipliers 11 and 20 no. In this case, the generator 8 of the SRP is connected through the key 11 with the buffer memory 2 directly, and the device search and maintain synchronism 19 through the key 21 is directly connected to the device cycle iperiod pulse repetition exactly equal to the length of information bits. In this case, the generator 8 of the SRP is connected to the buffer memory through the frequency multiplier 10 and the key 11, and the device search and maintain synchronism 19 is connected to the device frame synchronization 22 through the frequency multiplier 20 and the key 21. Next, the encoded signal is modulated first carrier frequency to the modulator 4, and then the elementary pulses (chips) SRP chip frequency fh=nf(1/R), n atomicity of the SRP, in the modulator 5, and after amplification in the amplifier 6 is radiated by the antenna 7. In the receiver the signal from the antenna 12 after amplification in the amplifier 13 is supplied to the demodulator 14 and the device search and maintain synchronism 19, where searches and phasing SRP accurate to the duration of the elementary pulse (chip) SRP that, as a rule, is less than 1% of the duration of the clock interval information when sacnoth SRP n127. This accuracy is much higher than the accuracy of the selection of the clock frequency in the prototype. Due to the lack of the receiver selector clock frequency information signal time of entry into synchronism at a clock frequency equal to zero, i.e., the first proyektirovanii information bits at a crucial device 16 already has a clock synchronization. This means that the clock synchronization implemented wheretogo detection in coherent detector 15, the signal at the crucial device 16, where it is integrated from the beginning to the end of the bit and through the reset voltage of the integrator is determined by the type of bit of information. Further highlighted in the decoder 17 information collected by the information receiver 18.

The invention can be implemented on existing hardware components on standard technologies.

The use of the invention would allow for the transmission of discrete data with high speed and noise immunity, however, the system for transferring information easier compared to the prototype.

System for the transmission of discrete information containing on the transmission side information source and connected in series encoder, the first, the second modulator, the amplifier and the antenna, and the generator carrier frequency, is connected to the second input of the first modulator, and the pseudo-random sequence generator connected to the second input of the second modulator at the receiving side containing connected in series with the antenna, the amplifier, the demodulator, coherent detector, the deciding unit, a decoder error-correcting code and the receiver of information, the search block and maintain synchronism included between the first and second inputs of the demodulator, block no is Itachi, included between the first and second inputs of decoder error correcting code, wherein on the transmission side entered sequentially connected to the frequency multiplier, the key and the block buffer memory, a second input connected to the output of the information source, and the output is connected to the encoder input, the input of the frequency multiplier and the second input key is connected to the second pulse output of a pseudorandom sequence generator, at the receiving side the entered frequency multiplier and the key, and the second pulse output unit of the search and maintenance of synchronism is connected to the input of the multiplier with a second input key, the output of which is connected to the inputs of the decision making unit and the unit frame synchronization.

 

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