The method of recording data when testing the memory device and the test device memory

 

(57) Abstract:

The invention has means to record data, checks the data, and the control circuit. The method of recording data when testing the memory device includes the steps of generating a voltage differential between the pair of bit lines B/L and direct storage of data to the capacitor of the memory cell. Direct recording on bit lines may be possible according to this invention. In addition, each memory cell can be fully tested in one cycle, and the scan time can be significantly reduced. 2 S. 2 C.p. f-crystals, 1 Il.

The invention relates to a memory device, such as random access memory (DRAM), and more specifically to a method, which can reduce the test time of the memory device with high density and high degree of integration, and to the scheme which can test the memory device.

The memory device integrated in the production processes of semiconductor devices requires the use of various precision operations, accordingly, to increase the degree of integration in the production of memory devices. During these processes, you should avoid getting dust or dirt. But with increasing density of the elements of the Oia memory device. Even if checking the memory device is conducted internally, the scan time is lengthened in proportion to the density of integration.

That is, when the conventional control devices memory test goes a bit (x4, x8, x16) using test signals. Spent this time increases with the density of integration of x bits.

Accordingly, the higher the degree of integration, the greater the scan time, since the recording and reading of data are carried out by x-bitney unit through line I / o and data are compared with each other to find the error.

The purpose of this invention is to provide a method of recording in random access memory (RAM) (DRAM), which can verify the normality or the defect data, and to reduce the scan time by recording and comparing data directly on the pair of bit lines without the use of lines I / o when reading and writing data.

Another aim of the invention is to propose a scheme for testing RAM, performed according to the method.

To achieve videoshablony purposes, the invention consists in the method of recording data when testing the memory device. The method comprises the steps of generla direct write data to the pair of bit lines without the use of lines I / o and direct store those data in the capacitor of the memory cell, the selected line of words.

The invention further consists in the method of recording data when testing the memory device. The method includes the steps of directly generating a voltage differential between the pair of bit lines by selecting at least one MOS transistor of the control circuit of a pair of lines with a level of supply voltage (Vccor ground level (GND) through an amplifier reading and storing data to the capacitor of the memory cell selected by the word line.

The invention still further consists in the circuit for testing, including a lot of read amplifiers connected to the pair of bit lines, multiple memory cells connected to bit lines and word line, many of the MOS transistors included in a conductive state by the column selection in response to a specified set of memory cells to connect the I / o to a pair of bit lines, respectively, containing recording media for writing data, while the pair of bit lines report the level of Vccand the ground level (GND) when using MOS transistors are directly connected to the pair of bit lines, means of verification data, connected to the output of the amplifier scity

According to this invention may directly write on a bit of wire. In addition, each memory cell can be fully tested in one cycle, and the testing time can be greatly reduced, as the data is written in each memory cell connected with the selected line of words, and errors are checked for each bit line.

The invention is illustrated in the drawing, which shows a diagram of the execution of this invention.

A detailed description of the preferred designs.

The invention will now be described in more detail in the accompanying diagram. As shown in the drawing, the read amplifier 2 is located between the pair of bit lines B/L and to detect the voltage difference on the bit lines. The memory cell 5 is connected between a bit line B/L and word line B/L. the memory Cell has a transistor of type n-MOS M11and the capacitor 1. Also to bit line B/L is connected transistor p-MOS M1and n-MOS M2to keep it level Vccand the ground level (GND), respectively.

Similarly, the p-MOS transistor M 3 for tier Vccand n-MOS transistor M 4 to ground level (GND) is connected to the unit (diagram) control 1 through nodes A-G sootvetstvyy behind the read amplifier 2. The gates of transistors M5 and M6 are also connected to the control circuit 1 through the nodes E and G, respectively (scheme nodes E and G are connected not gates, and other electrodes of the transistors M5 and M6.

Transistor type n-MOS M7 connected to the RESET line (reset, reset) is connected to a common node H of the transistor type n-MOSFET M5 and M6, and the line indicating the defect TQ is connected through the n-MOS transistor M8 to form the validation scheme. After this validation schemes transistors type n-MOSFETs M9 and M10 to be included on the conductivity signal of the column COL, connected with lines I/o 1/0 so that the bit lines and lines 1/0 are connected to each other. Line DIN determines the status signals, which are issued for each "node" A-G as input of the control circuit 1, when data is written and read.

Operations that meet the technical requirements of the invention are the same as regular online memory device (DRAM), and at this time, the MOS transistors M1 to M4 locked.

When the normal RAM (DRAM) of the MOS transistors M9 and M10 are included on the conductivity signal selection column COL to select lines I/o 1/0, then line 1/0 connect to a pair of bit lines In/L and the read amplifier 2. The amplifier of the read MOS transistor M11. Then for a read operation, the MOS transistor 11 is transferred to the conducting state by the word line B/L and the charge stored in the capacitor C1 is discharged to the bit line B/L. the read Amplifier 2 detects and amplifies the signal state of the bit line to produce a status signal on the line I / o 1/0. This operation is the same as work RAM (DRAM). In contrast, the invention does not use the line I / o 1/0 for a quick check of RAM, so that the transistors M9 and M10 connecting line I / o 1/0 locked.

To check RAM means to write data into RAM and to compare two sets of data after reading the data recorded. Check RAM can be divided into two methods of the present invention, that is, one uses the read amplifier 2 during read operations, while the other does not use the read amplifier 2.

First will be described the method without using the read amplifier 2. During this operation, the data is directly set on the bit line B/L to save the data in the capacitor C1 of the cell RAM in the recording process. After the desired line of words B/L is selected, the control circuit 1 holds the output node And at a low level, the p-MOS transistor M1 opens and energizes ETOR M11, the selected line of words B/L, is included on the conductivity to charge the capacitor C1. Here, although the drawing shows only one MOS transistor M11 and one capacitor C1, a large number of MOS transistors and capacitors for memory can be connected in parallel to the line of words. The voltage corresponding to the data applied to charge the RAM cell, the selected line of words B/L. At this time, since the data on the bit line B/L is fixed by the control circuit 1 and is loaded on the nodes E and G during reading quick check, the read amplifier 2 does not work in the way you write.

Now let us describe the method of using the read amplifier 2.

When the control circuit generates status signals of high level and low level at the node D and a, respectively, to enable the conducting state, the MOS transistors M1 and M4, these transistors are disabled and there is a voltage difference between a pair of bit lines D/L and then the read amplifier 2 detects and amplifies the voltage difference and data charges in the capacitor C1 through the binding of a bit line to the level of Vccor the ground level (GND).

On the other hand, the comparative operating procedure for CPA the record, is:

First, the control circuit 1 outputs a signal of a high state on nodes a and C and a status signal of low level to the nodes b and D to lock the MOS transistors M1, M2, M3 and M4. Then, if the data stored in RAM are "1" and the MOS transistor M11 is enabled on the conductivity of a line of words B/L, the charge stored in the capacitor C1 is discharged to the bit line B/L. the read Amplifier 2 detects this voltage, so that the bit line B/L becomes high level, while the bit line becomes low level. While this level is not set, both nodes E and F have a low level. After that, the control circuit 1 generates status signals of low and high level at nodes E and F, respectively, so that the data is checked in block data validation (schema validation) 3 (in the case of "1" data). That is, the low level signal on the bit line is supplied to the gate of the MOS transistor M5, while the signal of the high level bit line B/L is supplied to the gate of the MOS transistor M6, then the MOS transistor M5 is locked, and the MOS transistor M6 is turned on conductivity, so that the low level is transmitted to the node H, and the MOS transistor M8 is continuously locked.

So the line display defect TQ, prior and specifies the memory cell during the examination, is normal. If there is an error when reading the data stored in the cell, a high signal arrives at a node H to open the MOS transistor M8, so that the line indicating the defect TQ goes to the lower level and indicates the presence of a defect. Thus, when one of the many memory cells with a defect, or each cell with a defect common node H receives a high level, as described above, and indicates the presence of a defect in the RAM passes the test.

The MOS transistor M7 connected to the reset terminal RESET, returns the node H to the ground potential for the next scanning operation. Namely, during a write operation and a read control circuit 1 pre-defines the data (1 or 0) is stored in the memory cell as the outputs of the nodes A-F and outputs a signal check at nodes E and G schema test 3 to test norms or defect in RAM.

As mentioned above, the present invention checks whether the data is normal or not in the validation scheme 3, by means of direct write and read data on the bit lines without the use of lines I / o 1/0. The write operation of data into each of the memory cells connected with the selected line of words that may occur during the display cycle, significantly reducing this time to test the RAM.

The invention is in no way limited to the above described example implementation. Various modifications of the described implementation, as well as other designs of the invention will be obvious to experts in this field after viewing the description of the invention. Therefore, we believe that the attached claims will cover any such modifications or execution, which fall within the true scope of the invention.

1. Device for testing the memory containing the amplifier of the read memory cell, the control unit, the unit write data, and an information input device connected to the input of the control unit, first to fourth outputs of which are connected to the first, second, third and fourth inputs of the status indicator block write data, the first output of which is connected to the information input of the memory cell, the first input of the read amplifier is an information input-output unit record data and is connected to the first bit line of the device, the power input and the reference potential unit record data is connected to the power input and the reference potential of the device, respectively, the control input of the memory cell of the key data, the first and second information input of which is connected to the first and second outputs of the amplifier are read, respectively, the reset input of the device connected to the input reset block data check, the control input of which is connected to the input of the display defect of the device, the outputs of block data validation connected to information inputs of the block address column, the control input of which is connected to the input of the column selection device, the output of the block address column is connected to the line I / o devices, fifth and sixth outputs of the control unit connected with the first and second inputs respectively of the status indicator block data validation, the second bit line of the device through the block of write data is connected to the second input of the amplifier is read.

2. The device under item 1, characterized in that the write block data contains four MOSFET, and two of them are p MOS transistors, the sources of which are connected to the bus voltage of the power supply and the drains of the first and second p-MOS transistors are connected to first and second bit lines of the device, respectively, which are connected to the sources of the first and second n - MOS transistors, the drains of which are connected to the bus zero potential is an economic unit, the second and the fourth inputs status indicator which is connected to the gates of the first and second n-MOSFETs.

3. The device under item 1, characterized in that the test data contains two n-MOS transistor, and the gates of which are connected with the first and second information input unit, respectively, the first and second control inputs of the block are connected with the origins of the first and second n - MOS transistors, the drains of which are combined and connected to the drain of the third and gate of the fourth n MOS transistor, the drain of which is connected to the zero potential bus unit and the drain of the third n MOS transistor, the gate of which is connected to the input reset block, the source of the fourth n - MOS transistor is connected to the control input of the block.

4. The method of recording data when testing a memory device, namely, that generate an electrical signal proportional to the difference between voltages of the pair of bit lines by selecting at least one MOS transistor from the set of the first group of MOSFETs over which control using control signals that form using the control unit, the input of which receives signals of the input data, write data somesite memory exercise, using the read amplifier, wherein each bit line is served or the potential of the supply voltage or the ground potential and perform a direct write of data to the memory cell, followed by reading data from a memory cell, the control unit locks the input data, under the action of control signals compare the read data recorded in the control unit using at least one MOS transistor of the second group, using the MOS transistor by comparing the results form a judgment about the presence or absence of errors.

 

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