The storage device store type

 

(57) Abstract:

The invention relates to the field of computer engineering and can be used as a buffer storage device in the system of collecting and processing information. To expand functionality and improve performance in the device entered the power management mode that contains the managed demultiplexer and managed multiplexers, one for each memory cell, as well as the bus control mode of operation, United among themselves and with other functional units and blocks new connections. 1 C. p. F.-ly, 2 Il.

The invention relates to the field of computer engineering and can be used as a buffer storage device in gathering systems and information processing, computer and systems for various purposes for the coordination of transmission of information between devices.

Known storage device /1/ for the orderly storage, recording and issuing information on unaddressed principle in several modes: write a "top-down" and "bottom-up" in the first empty cell; reading in the "Shop", "bobsled", "Inverted shop", "Inverted bobsleigh".< the and additional memory elements, seven elements "And" four element "OR" two delay elements, and the eight elements "And" one element "OR" that groups designed to control reading and order entry information.

The disadvantage of this device is the large complexity of the drive, resulting in useful information, the memory capacity can be implemented in a very limited (a few dozen words) even when using advanced integrated technologies create vis memory. Consequently, this memory has a limited scope and is expensive.

Known storage device store the type of /2/ that we have chosen as a prototype. The prototype contains n-bit memory cells (JAP) storage store the type and the number of JAPANESE sites sampling (surveillance), the outputs are connected to the inputs read permissions (write) corresponding JAP. Each memory element YAP contains the first and second valves, the first and second inverters, the inverters feedback, interconnected and memory elements adjacent YAP relevant links. Each node sampling (addition) contains two inverter, inverters reverse tie is the synchronization of the drive and of the sampling sites is provided by the sequence of clock signals, and the shift information from one JAPANESE drive to another is carried out in the first phase, and loading (reading) the data on the second.

The device prototype has the following disadvantages: limited functionality, because it implements only one type of mode FIFO (first-come, first-served basis), and low performance due to the fact that is equivalent to the recording time information in the drive requires a minimum of two gifts: one to shift the previously recorded information, the other actually on the record. In addition, when the shift information, significant transients and interference in the discharge and the address drive circuits associated with the promotion when writing (reading) the previously recorded information in many JAP. This, in turn, results in additional to material consumed by the drive power and therefore heat IPOs, which is implemented by the device.

The aim of the invention is to expand the functionality of the device through the implementation of two modes (FIF first - come, first-served basis and LIFO first come last served), as well as improving performance by eliminating the need to promote in h is giving signals to the write-enable (read) at the inputs YAP drive store type, organized by unaddressed.

Diagram of the device shown in Fig. 1. The structure of the device includes: a drive unit 1, containing the memory cell 2, the enable inputs write and read them, as well as inputs and outputs data and reset inputs connected to the corresponding same inputs and outputs of the accumulator, block 3 sample recording unit 4 sample reading, containing for each memory cell of the memory is identical nodes 5 sampling unit 6 for controlling the mode of operation of the drive that contains the managed demultiplexer with one of two directions, and for each node 5 unit 4 controlled multiplexer with 8 two in one direction, the bus 9 data. When the output resolution sampling when recording unit 3 is connected to the same corresponding inputs of the block 6 and block drive 1, the inputs and outputs data which is connected to the bus 9 data. Output resolution sampling when reading unit 4 is connected with the corresponding same input storage unit 1, the input "Reset" of which is connected to the same inputs of unit 3 sampling during the recording unit 4 sample reading block 6 control mode and connect to the bus Reset of the device. Input mode selection LIFO/FIFO (L/F) units 3, 4 and 6 t between and connected to the bus synchronization F2 devices bus control signal Write which is connected to the same input unit 3 of the sample in the record, and the bus control signal "Read" is connected with the same input unit 4 sample reading.

Outputs 10 feedback unit 4 (the number of nodes of the sample 5 of this unit) are connected to respective inputs 11 training mode LIFO respective nodes 5 unit 3 sampling when recording, the outputs 12 feedback (the number of nodes of the sample 5 of this unit) are connected with the inputs of the 13 training mode LIFO respective nodes 5 unit 4 inputs 14 setting the operation mode for each node 5 is connected with the corresponding same outputs 15 of the unit 6 for controlling the mode of operation of the device, while the first and second output signals of the controlled discharge unit 6 are connected respectively with the first and second same input unit 4. Each node 5 sample has an output resolution sampling a read (write), output feedback, the input control word read (record), entry mode selection L/F, the synchronization input F2, the input set to one, the feedback input, the input to the preparation of LIFO mode, the input set to zero, the input mode setting. For unit 3, the input set to zero is offline to the input Reset block 3.

The preparation mode of the current (starting with the first in Fig. 1) node 5 of the block 3 and the feedback input of the subsequent node 5 of this block for each pair of nodes are interconnected and connected to the corresponding input 11 feedback for the current node 5 of the block 3. The feedback input of the first node 5 unit 3 (first from the top in Fig. 1) and the preparation mode, the last node 5 of this block (fifth from the top in Fig. 1) are interconnected and connected to the latter (Fig. 1 fifth) to the input 11 of the feedback block 3. Output feedback for each node 5 of the block 3 is connected with the same corresponding output unit 3. The input control word "Record" all nodes 5 unit 3 are interconnected and connected to the same input unit 3. Inputs mode select all nodes 5 block 3 also interconnected and connected to the same input unit 3, the synchronization input of which is connected to the same inputs of all units 5 this block. When this input mode setting of each of the current node 5 block 3 (except the first from the top in Fig. 1) is connected to the output resolution sampling of the previous node 5 of the block, and the input mode setting the first node 5 of the block 3 is connected to the output resolution Vyborg is, 1) block 4 and the preparation mode of the subsequent node 5 for each pair of nodes of this block are interconnected and connected to the input 13 training mode for subsequent node 5 of the block 4. At the entrance of the training mode of the first node 5 and the feedback input to the last node 5 unit 4 is connected and is connected to the input 13 of the block 4 to the first node 5 of this unit. The inputs installed in the unit all nodes 5 sampling unit 4 (except the first and last nodes on the top) is connected and is connected to the input of the signal "Reset" of the unit 4, the first input control signal reset which is connected with the input set to the last unit of node 5 and with the input set to zero the first node 5 of the block 4, the second signal input of the controlled discharge of which is connected with the input set to zero the last node 5 unit 4 and to the input of the installation unit of the first node 5 of the block 4.

Outputs signals read permissions on each node 5 unit 4 are connected with the corresponding same output unit 4 outputs the feedback of which is connected to the same outputs of all nodes 5 of this unit. The inputs of the control signal "Read" each node 5 unit 4 is connected and is connected to the same input unit 4, and I connected to the synchronization input unit 4, inputs 14 mode settings which are connected to the same respective inputs of the nodes 5 of this unit. The outputs of read permissions (write) block 4 connected to respective same input unit 6, the input mode selection which is connected with the control input of the demultiplexer 7, and with the control inputs of all of the multiplexers 8, and the information input of the demultiplexer 7 is connected to the input of the reset signal of the block 6, and its first and second outputs connected respectively to the first and second controllable outputs a reset unit 6, the outputs 15 of the profile settings, which are connected to the respective outputs of the multiplexers 8, the first inputs of the first (top in Fig. 1) and the second input of the penultimate multiplexers 8 are interconnected and connected to the last (on account from the top in Fig. 1) the entry permit reading unit 6, the second input of the first and the first input of the third multiplexer 8 are tied together and connected to the second enable input of the reading unit 6, the first entry permit reading of which is connected to the first input of the second and the second input of the last multiplexer 8 of the block 6, the third entry permit reading of which is connected with the second input of the second and first input of the penultimate (fourth in Fig. 1) multi is the home of the last (fifth in Fig. 1) of the multiplexer 8.

Each node of the sample 5, the diagram of which is shown in Fig. 2, contains: RS-trigger 16, the first 17 and second 18 and third 19 schematic "And" the first 20 and second 21 scheme "OR". Zero trigger output 16 connected to the first input of the first circuit And 17, the second input of which is connected in the input of the control signal "Read" ("Account"), and the output of the first circuit And 17 connected to the first input of the second circuit And 18, the first input of the third circuit "And"19 and the output enable signal sampling site 5. Input "mode Selection" node 5 is connected to a second input of the second circuit And 28, the output of which is connected to the output of the feedback node 5. The output of the first circuit "OR"20 connected to the S-input of the trigger 16, R

the inlet of which is connected to the output of the second circuit "OR"21, the first input of which is connected to the input node 5 training mode, the second input to the input node 5 install the trigger 16 to zero, the third circuit input OR 21 is connected to the input node 5 mode settings.

The first input of the first circuit "OR"20 connected to the input node 5 installation unit, the second input to an output of the third circuit, And 19, the second input of which is connected to the synchronization input of node 5, and the third input of the first circuit OR 20 is connected to the feedback input node 5.

T what about the difficulties since the memory cell 2 of the block 1 may be implemented as a simple register circuits with the enable inputs of a read / write input and output data, and each node 5 can be implemented on the basis of the RS trigger and simple logic "AND", "OR", as shown in Fig. 2.

The operation of the device is as follows. In the device there are two modes: FIFO (first-come, first-out) and LIFO (first come, last served). However, instead of promoting the previously recorded information in the drive applied to the continuation of the signals permits sampling at reading and writing when the fixed information in the drive. The fetch block 3 when recording and fetch block 4 when reading move the pointer boundaries the upper and lower (top and bottom) parts of the stack. While monitoring the degree of filling capacity of the disk drive and including an overflow can be implemented in various known circuits or software methods, for example, using counters and Comparators, as done in /1/.

The LIFO mode, the write operation. The initial state in the drive 1 is missing information (directly after turning on the power source). On the bus mode selection display signal mode settings LIFO the inputs of all units 5 this block, sets the RS - trigger the first from the top in Fig. 1 node 5 in the state of "zero", and RS triggers all the other nodes 5 unit 3 in a state of "unit". Moreover, the elements of memory of all the memory cells 2 drive 1 also signal "Reset" is set to "zero". At the same time the signal "reset" is set to "unit" RS triggers all nodes 5 (except the first and last node) block 4 sample reading. The first site 5 sampling unit 4 is installed in the state unit managed by the reset signal, which is passed to the block 4 from the second output of the demultiplexer 7 block 6. This signal can also be controlled reset sets the last (fifth from the top in Fig. 1) node 5 unit 4 in a state of "zero".

The presence of logical units" on the control inputs of the multiplexers 8 block 6 configure these multiplexers for transmission of signals from the second input of each multiplexer 8 to the corresponding outputs 15 mode settings of this unit.

After the action of the reset signal on the bus "Record" in the moment of action phases F1 set control signal "Write", represented as a logical "unit". This signal via the input unit 3 is fed in parallel to the corresponding input is 1. The enable signal sampling when recording will take place at the output only the first from the top in Fig. 1 node 5, since the first and second inputs of the first circuit And 17 of this node (Fig. 2) there are two logical units: output inverted shoulder of the trigger 16, the reset signal has been previously set to the zero state, and the input control word entry of this node. Because triggers other nodes 5 of block 3 were established by the reset signal in one state, the signal on the other output resolution sampling when recording unit 3 is not produced. Similarly, block 4 does not produce the signal resolution of the sample for the reading, as the control signal "Read", presented in the form of logical units on the respective input nodes 5 block 4, no.

The enable signal sampling when recording with the release of the first (top in Fig. 1) node 5 is supplied via the output unit 3 and the corresponding input block 1 input recording resolution of the corresponding memory cell 2, thereby realizing an entry in the cell data on the data bus 9. This same signal is supplied to the first input of the second circuit And 18 (Fig. 2), to a second input of which there is a single signal mode selection, appropriate to the block 3 (Fig. 1, figs. 2) is fed to the same input 13 unit 4, and through him to the input of the training mode of the first top node 5 of the block 4 by setting the trigger 16 of this node in the zero state. Thus, in block 4 of the sample for reading recorded information in the first cell of the memory 1 is carried out record data. When the input 13 of the unit 4 is also fed to the input of feedback last node 5 of the block 4 and sets it in one state. At the same time the enable signal sampling when recording comes from the connection (Fig. 1) input mode settings the subsequent (second from the top in Fig. 1) node 5 of block 3, setting it to zero state and thereby preparing the recording mode to the second top cell memory 2 memory 1. Simultaneously the same signal resolution sampling when recording from the output of the first circuit And 17 (Fig. 2) is fed to the input of the third circuit And 19 of the node 5. Based upon a timing signal F2, which is a synchronization input node 5 is supplied to the second input of the third circuit, And 19, the output of the third circuit, And 19 (Fig. 2) you may receive a signal through the first scheme OR 20 is supplied to the S input of the trigger 16, setting it in one state.

Thus, in the result of the unit 3 (except the second from the top in Fig. 1) installed in one state, when the trigger 16 of the second node 5 of the block 3 is in the zero state, and thus the logical scheme of this site prepared to generate a signal resolution sampling when recording and feedback signal at the input of this node signal "Write".

To enroll in the following time steps phase F1 of the control signal Write simultaneously to corresponding inputs of all units 5 unit 3, the enable signal sampling when recording and the feedback signal will appear only at the respective outputs of the second (on account from the top in Fig. 1) node 5 of the block 3, as the trigger 16 that node 5 is in the zero state (Fig. 1, figs. 2). When the enable signal sample when writing, acting via the corresponding input block 1 input recording resolution of the second top cell memory 2 unit 1 implements the entry in the cell data on the bus 9 data, and at the same time, when the input mode setting subsequent account (the third in Fig. 1) node 5, sets the trigger 16 of this node in the zero state, thus preparing the perception of this node the following command "Record". The feedback signal from the output of the second (account Sorgue 4, sets the trigger 16 of this node in the zero state. At the same time, acting on the feedback input of the previous (first from the top in Fig. 1) unit 4, this signal sets the first node in block 4 in one state.

Similarly, as in the first cycle recording, the trigger 16 of the second node 6 unit 3 at the time of the signal phase F2 is set to one state. Thus, at the end of the second loop recording (the second word) all triggers 16 nodes 5 block 3 (except the third from the top in Fig. 1) will be installed in one state, with all triggers of 16 nodes 5 block 4, except the second from the top in Fig. 1, will be established in one state.

A similar process implement when writing in all subsequent memory drive 1. When data is written in the last memory cell of the drive permission signal sampling when recording with the same output of the last node 5 unit 3 is fed to the input mode setting the first node 5 of the block 3 by setting the trigger 16 of this node in the zero state.

Similarly, write data in the memory cell 2 located at an arbitrary location of the drive 1, which corresponds to the zero state trigger sootvetstvuyshee the LIFO mode. This multiplexers 8 unit 6 configured to transfer signals received at its second input. On the bus Read" expose the control signal "Read" corresponding to a logical "one". This signal is applied in parallel to corresponding inputs of all units 5 unit 4 sample reading. However, the enable signal sample reading will be generated at the output of the node 5 of the block 4, the trigger 16 which is in the zero state (Fig. 2), i.e. corresponding to that node 5 memory 2, the data bus 9 data which were recorded last. Assume that the write data block is implemented in the second from the top in Fig. 1 memory cell 2. A corresponding cell site 5 unit 4 sampling when recording also will be the second from the top in Fig. 1, and the trigger 16 is in the zero state. With zero shoulder of the trigger 16 to the first input of the first circuit And 17 receives the signal of logical units (Fig. 2). If the second input of this circuit And 17 of the control signal read also in the form of logical units on the output of the circuit And 17 receive a permission signal sample when reading, which goes through the same output node to the input of the corresponding memory cell 2, implementing CTG. 2). As to the second input of the second circuit "And"18 the signal is present the logical unit corresponding to the operation mode LIFO, the output of this circuit "And"18 produces a feedback signal, which, acting on the same input of the corresponding node 5 unit 3, sets the trigger 16 of the node 5 in the zero state, thereby providing the possibility of recording data in the selected second memory cell. The same enable signal sampling when recording is supplied to the second input of the first and the first input of the third multiplexer 8 of the block 6. As each multiplexer 8 in LIFO mode is configured for transmission at its output signals from the second of its input, the enable signal sample when reading from the output of the selected second node 5 of the block 4 is supplied through the first top in Fig. 1 multiplexer 8 input mode settings of the first top node 5 of the block 4 by setting the trigger 16 of this node in the zero state. Thus the first overhand knot 5 block 4 in Fig. 1 prepared for the next cycle of reading information from the first memory cell.

It should be noted that the operation of the unit 5 unit 4 is similar to the work site 5 of block 3, so the installation of the trigger 16 of this node in one state produce similar videopornocasalin, for example, first in first from the top in Fig. 1 memory cell, and then the second, then when reading in this mode, the output data from the drive is automatically first from the second memory cell, and then from the first.

The FIFO mode. The write operation. The initial state in the drive 1 is missing information, for example, is considered a point of time directly after turning on the power source. On the bus mode selection display signal mode settings FIFO, which is represented by a logical zero. In contrast to the LIFO mode, the signal of the controlled discharge of the same name appears on the first output unit 6 (Fig. 1), which, acting on the input set to zero the first from the top in Fig. 1 site 5 unit 4 sets the trigger 16 of this node in the zero state. Simultaneously, the same signal is applied to the input set to the last unit (the fifth from the top in Fig. 1) node 5 of the block 4. Other nodes 5 unit 4 unit 3 and the memory 2 memory 1 are set by the reset signal coming from the bus Reset is exactly the same as in the above-described mode of operation LIFO.

Thus, the initial state of all units 5 units 3 & drive 1 when implementing the entries in the FIFO mode does not differ from the original SOS is on (top of Fig. 1) node 5 of the block 3 is set to zero and triggers other nodes 5 of this block is in one state.

At the same time the signal "Reset" is set to "unit" triggers all 16 nodes 5 block 4 (except for the first one at the top and the latest in Fig. 1). Trigger the first node 5 unit 4 is set in the zero state signal on the input set to zero, coming from the first output of the controlled discharge unit 6. This signal is controlled reset is set in the one state, the trigger 16 to the last node 5 of the block 4. After the action of the reset signal on the bus "Record" in the moment of action phases F1 set the recording signal, represented as logical units. This signal via the input unit 3 is supplied in parallel to respective inputs of all units 5 unit 3. At the same time on the data bus 9 put the code words, which must be recorded in the memory 1. The enable signal sampling when recording will appear in the output only the first from the top in Fig. 1 node 5, since the first and second inputs of the first circuit And 17 only this node (Fig. 2) there are two logical units with output inverted shoulder of the trigger 16 and the input control word entry of this node. The permission signal to wyboru in Fig. 1) memory cell, thereby realizing an entry in the memory cell data on the data bus 9.

However, unlike LIFO mode, when implementing the FIFO mode, the feedback signal on the respective output node 5 of the block 3 is not produced (Fig. 1) as the second input of the second circuit And 18 (Fig. 2) there is a signal of logical zero, which presents the control signal select FIFO mode. As a result, when the implementation of the entries in the FIFO mode (unlike mode LIFO) no impacts on the block 4 block 3 does not occur, and all triggers 16 nodes 5 unit 4 at the time the records remain in the same condition in which they were installed when the impact signal "Reset".

Otherwise, the process of recording information in all memory cells (as in first) drive 1 in the FIFO mode is identical to the process of recording information in the memory when implementing LIFO mode.

When this memory cell is filled from top to bottom, as shown in Fig. 1, when the empty drive 1, or in any available memory, also moving from top to bottom.

The FIFO mode. The read operation. On the bus selection mode set signal of the logic zero corresponding to the job operation mode FIFO. When this multiple rawsome signal read the corresponding logical unit. This signal is applied in parallel on the same input nodes 5 unit 4 sample reading. However, the enable signal sample reading will be generated on the output, but that node 5 of the block 4, the trigger 16 which is in the zero state, i.e. at the output of the first from the top in Fig. 1 node 5 of the block 4. It is advisable to note that the information in the first memory cell block 2 drive 1 was first recorded from the available sequence data.

The signal of the logic unit output zero shoulder of the trigger 16 of the first top node 5 unit 4 is supplied to the first input of the first circuit And 17, the second input of which the signal is present the logical unit representing the command "Read". As a result, the output of the first circuit And 17 produces a signal of logical units, which are simultaneously supplied to the first input of the third circuit, And 19, the first input of the second circuit "And"18 and to the output resolution sampling at the entry node 5.

Due to the fact that at the second input of the second circuit "And"18 there is a signal of logical zero, which presents the control signal select FIFO mode, the output schema "And"18 the feedback signal is absent (Fig. 2). Thus, when implementing a read mode is so

The enable signal sample when reading from the corresponding output of the first unit 4 via the output unit 4 and the input unit 1 is supplied to the enable input is read first from top to memory cell 2, thereby realizing the process of reading information from this cell to the data bus 9.

Duration of the signal read permissions and, therefore, the read operation is specified by the point of action of the clock signal F2, which, coming to the second input of the third circuit "And"19, permits the formation of the output of this circuit "And"19 setting signal trigger 16 is selected first from the top of node 5 in one state (Fig. 2).

As each multiplexer 8 unit 6 is configured by the signal mode selector on the transmission on its output signal to its first input, the enable signal sample when reading from the output of the selected first node 5 block 4 (Fig. 1) passing through the second top multiplexer 8 of the block 6 to the input mode settings of the second top node 5, sets the trigger 16 of the second node 5 in the zero state. Thus the second overhand knot 5 block 4 in Fig. 1 prepared for the next cycle of reading information from the second memory 2 memory 1. Next, the reading process is repeated until the last ball is they were written to the drive, and not in reverse, as when implementing LIFO mode.

Thus, the proposed device is compared with the prototype richer, because in addition to the implementation of the drive operation in FIFO (first-come, first-served basis) also provides the drive mode LIFO (first come last served).

The presence of fixed information in the drive allows you to use it repeatedly, which is also significantly expands the functionality of the device.

The proposed device is also higher compared to the prototype performance, instead of the promotion of the information in the memory by the aforementioned modes implemented promotion signal sample memory cell when the read signal sample cell when writing at fixed information in the drive. This eliminates the occurrence of harmful interference and transients in the discharge circuit of the storage device 1 and thereby reduces the cycle time read and write information.

1. The storage device store type, containing a block of memory consisting of n memory cells, the fetch block when writing containing n nodes fetch and fetch block prnu with the same inputs of the accumulator, the input recording resolution of which is connected to the same outputs of the nodes of the sampling unit sampling when recording, the inputs and outputs of data of the memory cells of the accumulator is connected to the data bus device, the input recording device connected to the outputs of the write-enable all nodes sampling unit sampling when recording, the input reading devices are connected to the inputs read permissions on all nodes fetch fetch block when reading the reset input of the device connected to the reset inputs of the blocks of the sample when writing and when reading, the synchronization inputs are connected to the inputs of all units of the sample and connected to the synchronization input device, characterized in that the device further comprises a control unit, which is composed of a demultiplexer and a group of n multiplexers, the input mode selection device connected to the same inputs of all units of the sample to the control inputs of multiplexers and demultiplexer, the output of the i-th, where i 1, 2, n, a multiplexer group is connected to the input mode settings of the i-th node sampling unit sampling the read output of the read permission for the i-th memory cell, the input recording resolution of which is connected to the output of the i-th node sampling unit sampling when recording, the reset input of the fetch block and block sampling when recording, the input set to "1" which is connected to the input of the logic zero of the device, and inputs the installation in the "0" from the second to n-th nodes of the sampling unit sampling when recording, the input to the preparation mode of the first node sampling unit sampling when recording is connected to the output of the feedback of the n-th node sampling unit sample reading and the feedback input node sampling unit sampling records, the preparation mode of the j-th node sampling unit sampling when recording, where j 2, 3, n, connected to the output feedback (j 1)on site sampling unit sampling for reading and the feedback input (j 1)-th node sampling when recording, the output feedback of the j-th node sampling when recording is connected to the feedback input of the j-th node of the sample for the reading and preparation of mode (j 1)-th node sampling or reading the output of the first node sampling when recording is connected to the feedback input of the first node of the sample for the reading and preparation of the n-th node sampling or reading the input set to "1" of the first node sampling unit sampling when reading connected to the input set to "0" of the n-th node sampling unit sample reading and the first output of the demultiplexer, the second output of which is connected to the input set to "0" of the first node sampling unit sampling when reading and to the input set to "1" of the n-th knot the Institute is connected to the information input of the demultiplexer, the reset inputs of all of the memory cells and the input reset, input setup to "0" from the second to the (n-1)-th node sampling unit sampling when reading connected to the input of the logic zero of the device, the output of the l-th node sampling unit sampling when reading connected to the first input (l + 1)-th and the second input (l 1)-th (where l 2, 3, n-1) multiplexers, the output of the first node sampling unit sampling when reading connected to the first input of the second and the second input of the n-th multiplexers, the output of the n-th node sampling unit sampling when reading connected to the first input of the first and the second input of the (n-1) th multiplexers.

2. The device under item 1, characterized in that each node sample contains RS-trigger, the three elements and two elements OR, in this case zero output RS-flip-flop connected to the first input of the first element And a second input connected to the enable input of a read or write node sampling, the output of the first element And connected to the first input of the second element And the first input of the third element And with the output resolution sampling site sampling, the input mode selector connected to the second input of the second element And whose output is connected to the output of the feedback node sampling the output of the first element OR connected to the S input of the RS-trigger, R-entrance which A second element OR is connected to the input mode setting unit work sample, the input set to "1" which is connected to the first input of the first element OR the second input connected to the output of the third element And a second input connected to the synchronization input node of the sample, the feedback input of which is connected to the third input of the first element OR.

 

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EFFECT: broader functional capabilities.

7 cl, 148 dwg

FIELD: electric engineering.

SUBSTANCE: device has frequency filter, voltage amplitude limiter and two comparators, each of which includes differential cascade, two power sources, emitter repeater and voltage divider.

EFFECT: simplified construction, higher precision, higher reliability.

2 dwg

FIELD: data carriers.

SUBSTANCE: device for determining logical state of selected memory cells in memory device with passive matrix addressing is made with possible connection to ferroelectric memory device or forming its portion and contains reading amplifying contours, synchronous amplifier, combined source of shift voltage and signal, active control line driver, multiplexer, a set of routers. Other variant of aforementioned device is additionally equipped with second set of routers. Method describes operation of aforementioned devices.

EFFECT: higher efficiency, broader functional capabilities.

3 cl, 12 dwg

FIELD: editing of records.

SUBSTANCE: device is used for separation of data file with main and control data on first file and second file. Device has operation means for determining a point of division on first and second files; editing means for editing first control data, to render ineffective first portion of block of recorded data of fixed length with main data; and means for generating second control data, to render ineffective second portion of block of recorded data of fixed length with main data, and for adding second control data to second data file.

EFFECT: higher efficiency.

3 cl, 46 dwg

FIELD: technology for manufacturing plastic cards with chip (cards with inbuilt micro-circuit).

SUBSTANCE: method includes performing cycles of operations, consisting of loading command by external device into buffer of chip-card, execution of command by chip-card and return of message about result of command execution by chip card to external device. Prior to operation of loading by external device, block of commands is formed, containing administrative command, in which as data several commands fed onto card are used, aforementioned commands block is executed and message about result of execution of command block is returned to external device. Number of commands in block is supposed to be maximal possible to decreased exchange cycles and it determined by length of commands, size of command buffer, maximally allowed length of data in used transfer protocol.

EFFECT: when used in plastic cards with chip on basis of microprocessor, for example, in SIM-cards, leads to increased speed (decreased consumed time) of card initialization.

6 cl, 2 dwg

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