A method of manufacturing semiconductor devices
(57) Abstract:Usage: in microelectronics, in particular in the manufacture of semiconductor devices during the preparation of crystals for Assembly into the housing. The essence of the invention: on the collector side of the plate with the generated structures of semiconductor devices consistently put a layer of aluminum and Germany. The plate is divided into crystals and carry out the brazing crystals on crystallochemical. After applying a layer Germany put an extra layer of aluminum with a thickness in the range 0.05 to 0.15 the thickness of Germany, and conducting heat treatment in a gaseous environment with the content of the oxidizing components of oxygen and/or water vapor for more than 3 vol.% at 424 - 510oC. The invention relates to microelectronics, in particular the production of semiconductor devices, and can be used in the preparation of crystals for Assembly into the case.The known method of mounting the crystals in the metal casing on which the gasket of the eutectic alloy, such as gold-germanium, is placed between the crystal and heated to the temperature of the eutectic alloy body 
The disadvantage of this method is the low electrical parametrically to the base of the case.Known the closest to the technical nature of the invention is a method of manufacturing semiconductor devices, comprising the sequential deposition on the collector side plates formed with structures of semiconductor devices of layers of aluminum and Germany, the separation of the plates at the crystals, the brazing crystals on crystallochemical covered with aluminium 
The disadvantages of this method are irreproducibility and low electrophysical parameters of semiconductor devices caused by incompleteness (by area) of contact of the crystal to the case base as a result of partial oxidation of Germany, and his cracking and peeling in some areas.Reduction of the area of connection of crystal with crystallochemical leads to increased thermal resistance (Rtn-k), reducing power dissipation.The challenge which seeks the invention is the improvement of electrical characteristics of semiconductor devices and increase the reproducibility of the process by increasing the area of the wettability of the contacting surfaces, reduce the likelihood of oxidation of the soldering p is bretania is in the method of manufacturing semiconductor devices, comprising the sequential application on the collector side of the plate with the generated structures of semiconductor devices of layers of aluminum and Germany, the separation of the plates at the crystals, the brazing crystals on crystallochemical, according to the invention after application of a layer of Germany put an extra layer of aluminum with a thickness in the range of 0.05 to 0.15 the thickness of Germany, followed by a heat treatment in a gaseous environment with the content of the oxidizing components of oxygen and/or water vapor of not more than about 3. in the temperature range 424 510oC.In the process of trimoorti plates in the temperature range 424 510oC on the boundary of the first lying to the silicon layer of aluminum and germanium is mutual dissolution of aluminum and Germany. Formed at the boundary of layers of aluminum and germanium transition layer provides sufficient adhesion layer Germany with the underlying layer of aluminum, which ensures the integrity of the collector cover for any accompanying cutting and breaking plates mechanical stresses.Carrying out heat treatment of the plates in any gas environments with moderate, not more than 3% steriani role of an additional layer of aluminum. The layer of aluminum germanium protects from oxidation during the heat treatment of the plates, and when the brazing crystals, which in the presence of an additional layer of aluminum is permitted to apply directly to the air, which greatly simplifies the process of soldering, providing at the same time 100% full contact crystal and Kristallografiya.Heat treatment of the wafer with formed collector coated Al Ge - Al in gas environments with increasing content (>3%) oxidizing agents, for example air, can lead to oxidation of the collector cover and non-repeatable process soldering crystals.The range of thicknesses additional protective layer of aluminum is selected based on the need to fulfill the complete dissolution of the aluminum layer and Germany. Violation of this provision if the thicknesses of 0.15 the thickness of the layer Germany saves after heat treatment or pure aluminum surface or layer, enriched with aluminum, which negatively affects the quality of soldering.Reduction of the thickness of the additional layer of aluminum is less than 0.05 the thickness of Germany leads to the formation on the surface of the collector panaceia thermal treatment regimes collector coating is selected depending on thermal stability of the metallization of a semiconductor device and other possible reactions of the materials in the structure. The minimum heat treatment temperature 424oC is the temperature of the eutectic alloy aluminum germanium. Exceeding 510oC leads to a deliberate increase leakage currents of p-n junctions on most types of silicon devices due to degradation of the structures.Tests of the proposed method on the experimental batches of transistors, small-and medium-capacity type CT 3102, CT 3107, CT 816, CT 817, CT 604, CT 602 and IP type CU NC, IN, IN showed that by introducing an additional layer of metal increased yield structures and improved characteristics such transistor structures, asCanas30 50% 10 - 20% of the reproducibility of the process of soldering crystals up to 100%
The proposed method is implemented in the manufacture of semiconductor devices according to the following route.Example 1.On silicon wafers create a transistor structure methods of photolithography, ion doping and diffusion.Form aluminum metallization transistor structures.After viginia metallization when 5100,5oC for 10 min conducting the control of the electrical parameters of the transistor structures.Reduce the thickness of the Plaza is l Ge Al magnetron sputtering method on the installation type "ORATORIO-5" (NI-7-006) spray messenia, made of aluminum and Germany.Mode of application:
preliminary vacuum of 5 x 10-7mm RT.article.the temperature of the substrate 25020oC,
the current aluminium target 102 AND,
current germanium target of 1.5-2A
the pressure of argon 52 x 10-3mm RT.article.The thickness of the first layer of aluminum, in contact with silicon, 0.2 to 0.3 μm, the second layer Germany 1.5 to 2 μm, the top layer of aluminum of 0.1 to 0.2 μm.In the furnace LMS 125/5 conduct heat treated plates with 5000,5oC for 5 min in a stream of nitrogen gas with a flow rate of 22060 l/h at atmospheric pressure. The volume fraction of oxygen in nitrogen 1% water vapor 0,1%
The plates are cut and separated into the crystals.Method of contact-reactive brazing crystals you solder to the base, covered with aluminum. Temperature soldering 460 480oC, time of process 1 3 C. Soldering is carried out on the air.Example 2. Different thicknesses of the three-layer collector metallization:
the thickness of the first aluminum layer is 0.5 μm,
the thickness of the layer Germany 0.1 ám,
the thickness of the upper layer of aluminium of 0.005 μm.Heat treatment time of 1 min at 4300,5oC. The method of manufacturing according to Rovaniemi structures of semiconductor devices of layers of aluminum and germanium, the separation of the plates at the crystals, the brazing crystals on crystallochemical, characterized in that after applying a layer Germany put an extra layer of aluminum with a thickness in the range of 0.05 to 0.15 the thickness of Germany, followed by a heat treatment in a gaseous environment with the content of the oxidizing components of oxygen and (or) water vapor of not more than about 3. in the temperature range 424 510oC.
FIELD: micro- and nanoelectronics, micro- and nanomechanics where insulated conductors are used.
SUBSTANCE: proposed method for filling pockets in solid body with conducting material includes coating of solid-body surface, bottom, and side walls of mentioned pockets with first layer that functions as barrier material preventing diffusion of mentioned conducting material in solid body; application of second layer onto first one that functions as wetting layer for conducting material; application of third layer by way of physical or chemical deposition onto third one from gas phase that has in its composition mentioned conducting material; coating of third layer with fourth one that also incorporates conducting material; melting of conducting material by heating and profile leveling; material melting by heating is conducted after applying third layer and fourth layer is applied by any method of physical deposition from gas phase, chemical deposition from gas phase, chemical deposition from solution, electrochemical deposition, or chemical-mechanical deposition.
EFFECT: facilitated procedure, enlarged functional capabilities.
12 cl, 17 dwg
SUBSTANCE: invention is attributed to microelectronics and can be used in production of semiconductor devices and integral circuits. Essence of invention: in the method of attaching silicon chip to chip holder, chip seating surface is successively sputtered with two titan-germanium metals, and chip to chip holder soldering is carried out at temperature of 280-300°C.
EFFECT: improvement of chip with chip-holder contact reliability and stability of attachment process.
SUBSTANCE: method involves notching in bulk of a silicon wafer and silicone removing from the wafer back to uncover notch bottoms. Notching enables silicone pattern formation to represent hollow cell walls that is followed with wall-through oxidation to form a dielectric SiO2 conduit system. Silicon removing from the back of the wafer can be conducted by the deep plasma etch process.
EFFECT: high strength of the insulating element which can be used for manufacturing various MEMS devices in bulk of a standard silicon wafer.
2 cl, 13 dwg
SUBSTANCE: in manufacturing method of multi-level copper metallisation of VLSIC, which involves application operations of metal and dielectric layers, photolithography and selective etching of those layers, chemical mechanical polishing of dielectric layers, to plate of silicium, which is coated with dielectric material with vertical conductors of underlying structure, which protrude on its surface, there applied is multi-layered conducting film consisting of adhesive barrier, etched and auxiliary layers; grooves are formed in auxiliary layer before etched layers by electrochemical method; copper horizontal conductors are grown inside grooves in open sections of etched layer till grooves are fully filled; the second auxiliary layer is applied to surface of plate, and in that layer holes are made to the surface of horizontal copper conductors; vertical copper conductors are grown by electrochemical method in open sections of horizontal conductors till holes for vertical conductors are fully filled; then, auxiliary layers are removed; conducting layers between horizontal copper conductors are removed; dielectric layers are applied to surface of the plate by smoothing and filling methods, and then dielectric material layers are removed above vertical conductors by means of chemical and mechanical polishing method.
EFFECT: improving quality of copper conductors.
16 cl, 11 dwg, 1 tbl
FIELD: instrument making.
SUBSTANCE: invention relates to semiconductor devices production process, in particular to technology of making contacts with lowered resistance. In method of semiconductor device making contacts are formed on basis of platinum. For this film of platinum with thickness of 35-45 nm is applied by electron-beam evaporation on silicon substrate, heated prior to 350 °C, at rate of deposition of 5 nm/min. Then heat treated in three stages: 1 step is carried out at temperature of 200 °C for 15 minutes, 2 step is carried out at temperature of 300 °C for 10 minutes and 3 stage is at 550 °C for 15 min in forming gas, with mixture of gases N2:H2=9:1.
EFFECT: proposed method of semiconductor device making provides reduced contact resistance, high technological effectiveness, improved parameters of devices, high quality and yield.
1 cl, 1 tbl
SUBSTANCE: invention relates to the field of semiconductor production technology, namely to a technology of low-resistance silicide layers formation. The method of semiconductor devices manufacture includes formation of an amorphous layer by silicon ion implantation on the silicon plate with the energy of 50 keV and dose⋅ of 5⋅1015 cm-2, at the substrate temperature of 25°C. Prior to the palladium layer application, the substrate is sequentially etched in nitric, sulfuric and hydrofluoric acid, then washed with deionized water. The palladium layer is applied at a temperature of 25-100°C, with a thickness of 0.1 microns at a rate of 1.5 nm/sec. After application of the palladium layer, heat-treated under vacuum is conducted at a pressure of (2-8)⋅ 105 mm Hg, temperature of 250°C for 20-30 minutes. As a result, palladium silicide Pd2Si is formed.
EFFECT: invention reduces drag, improves process efficiency, improves parameters, improves quality and increases yield percentage.
SUBSTANCE: method of increasing the threshold barrier voltage of a transistor based on gallium nitride (GaN), which includes creating gate p-GaN mesa on the surface of the silicon wafer with epitaxial heterostructure of GaN/AlGaN/GaN type, inter-instrument mesa-isolation, forming ohmic contacts to the areas of the transistor drain and source, forming a two-layer resistive mask by lithographic methods, cleaning of the surface of the semiconductor, deposition of thin films of gate metallization, removing of the plate from the vacuum chamber of the evaporator, removal of the resistive mask, prior to the evaporation of thin films of gate metallization the plate is subjected to treatment in an atmosphere of atomic hydrogen for t=10-60 seconds at a temperature of t=20-150°C and flow density of hydrogen atoms on the surface of the plate, equal to 1013-1016 at. cm-2 c-1.
EFFECT: increase in the threshold barrier voltage of the GaN transistor when applying barrier metal films to the p-GaN gate area with a high electronic work function.
5 cl, 3 dwg