# Matrix setprocessor

(57) Abstract:

The invention relates to computing and is designed to build on the basis of specialized computers. The aim of the invention is the expansion of the class of tasks. This objective is achieved in that the matrix setprocessor includes m registers, m decoders mark, 2m-1 adders-vychitala, m-1 EXCLUSIVE OR circuits, three shifter, m+3 multiplexer (m - dimensionality of the processed matrix). 4 Il. The invention relates to computing and is designed to build on the basis of specialized computers.Known specialized devices that perform triangulation matrix (patent RF N 1800463), solution of systems of linear algebraic equations (RF patent N 1832301), solution of systems of linear algebraic equations with a triangular matrix (patent RF N 1803921), as well as devices for the rotation vector algorithm for Valdera (ed. mon. USSR N 445042).The main disadvantages of these devices are narrow functional composition of operations performed when significant hardware costs, as well as the need to compute the m-dimensional vector to use consistently is eusto for module definition three-dimensional vector (ed. mon. USSR N 1205139) that implements the iterative algorithm for three-dimensional movement vector using the sequence of n transformations reflection to its coincidence with the x-axis.One of the major drawbacks of this device is a great time determination module m-dimensional vector, which is of order m/2 cycles for n iterations. In addition, with this device it is impossible for the solution of systems of linear algebraic equations with a triangular matrix (perform a "reverse" for solving systems of linear algebraic equations) and to carry out the conversion matrix according to the method of Gauss or Gauss-Jordan. Meanwhile, the above operations are the mathematical content of a significant part of practical problems.The aim of the invention is a class extension is solved by the device of tasks by introducing the functional structure of the device of operations for solving systems of linear algebraic equations with a triangular matrix and transformation matrix according to the method of Gauss and Gauss-Jordan, and a calculation module m-dimensional vector for one cycle of operation of the device.This goal is achieved by the fact that the device contains three register is connected to the reference input of the binary code the number of iteration the output of the first register is connected to the information input of the first shifter, added m-3 registers, m-3 decoders mark, 2m-7 adders-vychitala, m-1 XOR circuit, m+3 multiplexer, where m is the dimensionality of the processed matrix block multiplication unit changes the sign of the number, and information inputs of all the registers are the input operands setprocessor, the synchronization inputs of all the registers is connected to the synchronization input of setprocessor, the control input of block multiplication is connected to the reference input of the binary code the number of iteration of setprocessor, the output of the first shifter through the block to change the sign, a control input connected to the output of the first decoder badge, connected to the first input of the chain of adders-vychitala, in which the sign of the first term (reducing) the j-th element (j 1,2,m-1) is connected to the output of the (j-1)-th element, and the input of the second summand (wichitaeagle) output (j+1)-th register, the output of the last element of the chain is connected to the information input unit of multiplication, the output of which is connected to the information input of the second shifter, the input of the second summand (wichitaeagle) the first output of the adder-vicites connected to the output of the second DM is the l-th register, the output of the l-th output of the adder-myCitadel, except the first, is connected to the l-th output setprocessor, the input l-th decoder of the mark is the l-th input of the analysis of the sign of the operand setprocessor, the output of the first decoder of the sign is connected to the control input of the first output adder-myCitadel, the output of the first register through the third shifter connected to the first information input of the m-th multiplexer, the second information input connected to the output of block multiplication, and output with inputs of the second term (wichitaeagle) each output of the adder-myCitadel, except for the first and second, the output of the first output adder-vicites connected with the second information input of the (m+3)-th multiplexer, the first information input connected to the output of the first register, and the output from the first output setprocessor, the output of the j-th decoder sign (j 2,3,m) is connected to the second input of the (j-1) th XOR circuit, a second input connected to the output of the first decoder badge, output (j-1) th XOR circuit connected to the first information input of the (j-1)-th multiplexer, the second information input connected to the output of the j-th decoder token, the output of the j-th multiplexer (j=1,2,m-1) connected to upravlajushemu first and second, the output of the second multiplexer is connected to the second information input of (m+2)-th multiplexer, the first information input connected to the output of the first multiplexer, and the output with the control input of the second output adder-myCitadel, the first information input of the (m+1)-th multiplexer connected to the output of the m-th multiplexer, the second information input with the input binary weight of the treated discharge setprocessor, and the output to the input of the second term (wichitaeagle) of the second output adder-vicites control inputs of all of the multiplexers connected to the reference input in binary mode setprocessor.The unit changes the sign of the number is known technical solution and, in particular, may be made in the form of adder-myCitadel, to the input of the first term (reducing) which is constantly supplied value of zero, the sign of the second term (wichitaeagle) is an information input unit changes the sign of the number, the control input of the adder-vicites managing unit changes the sign of the number, and the output of the adder-vicites output block.Block multiplication is known technical solution and is designed on the can, in particular, be in the form of a device consisting of a permanent storage device for storing constants and multipliers, and the address input of the storage device is a control input of the multiplication, the output of the storage device is connected to the input of the first factor, the input of the second factor of which is an information input unit of multiplication, and the output of the output unit of the multiplication.In Fig. 1 presents a diagram of the matrix setprocessor, where 1_{1}.1

_{m}registers operands, 2

_{1}.2

_{m}- decoders mark 3

_{1}.3

_{2m-1}adders-myCitadel, 4

_{1}, 4

_{2}, 4

_{3}shifters, 5-input binary code the number of iteration 6

_{1}. 6

_{m-1}XOR circuit, 7

_{1}.7

_{m+3}multiplexers, 8 block multiplication, 9 unit changes the sign of the number, 10

_{1}.10

_{m}the input operands, 11 synchronization input, 12

_{1}. 12

_{m}the outputs of setprocessor, 13

_{1}.13

_{m}the inputs of the analysis of the sign of the operand, 14 the reference input binary weight of the treated discharge, 15 the reference input in binary mode setprocessor.In Fig. 2 shows the scheme for conversion of vector pipelining, where U

_{1}. U

_{n}X

^{(j)}vector processed by the device U

_{j}Z - bus the signs of the operands for n iterations, Z

^{(j)}bus signs of the operands to the j-th iteration.In Fig. 3 presents a framework for triangulation of the matrix A(mxm), the columns of which are filed on the device U

_{1}.U

_{m}, each of which is the device shown in Fig. 2.In Fig. 4 shows a scheme for solving systems of linear algebraic equations with a triangular matrix, where U

_{1}.U

_{3}devices, each of which is the device shown in Fig. 2, a

_{ij}- the elements of the matrix system to the processing elements of the system matrix after processing, b

_{i}the elements of column free members before and after processing, respectively.Setprocessor includes m registers 1

_{1}.1

_{m}, 2m-1 adders-vychitala 3

_{1}.3

_{2m-1}, m decoders mark 2

_{1}.2

_{m}, m-1 XOR circuit 6

_{1}.6

_{m-1}m+3 multiplexer 7

_{1}.7

_{m+3}three shifter 4

_{1}, 4

_{2}, 4

_{3}unit changes the sign of the number 9, block multiplication 8 on one of the n constants, m inputs operands 10

_{1}.10

_{m}m inputs of the analysis of the sign of the operand 13

_{1}.13

_{m}that outputs 12

_{1}.12

_{m}the reference input binary NGOs discharge 14, moreover, the inputs of registers 1

_{1}.1

_{m}input operands 10

_{1}.10

_{m}and outputs connected to the inputs of the first term (reducing) the output of adders-vychitala 3

_{m}. 3

_{2m-1}accordingly, the inputs of the decoders mark 2

_{1}.2

_{m}are respectively the inputs of the analysis of the sign of the operand 13

_{1}.13

_{m}the outputs of decoders mark 2

_{2}.2

_{m}connected to the second inputs of EXCLUSIVE OR circuits 6

_{1}.6

_{m-1}accordingly, the first inputs of these circuits are connected to the output of the decoder, mark 2

_{1}and outputs are connected with the first information inputs of the multiplexers 7

_{1}.7

_{m-1}accordingly, the second information inputs of these multiplexers are connected to the outputs of decoders mark 2

_{2}.2

_{m}accordingly, the reference input binary code the number of iteration 5 is connected to the control inputs of shifters 4

_{1}, 4

_{2}, 4

_{3}and block multiplication 8, the output of register 1

_{1}connected through the shifter 4

_{1}and unit changes the sign of the number 9 to the input of the first term (reducing) of the adder-vicites 3

_{1}the sign of the second term (wichitaeagle) which is connected to the output of the register 2

_{2}the control input with the output of the multiplexer 7<3

_{1}.3

_{m-1}chained together, the j-th element of which the sign of the first term (reducing) connected to the output of the (j-1)-th element, the input of the second summand (wichitaeagle) to the output (j+1)-th register, managing input to output multiplexer 7

_{j}and the entrance to the entrance of the first term (reducing) (j+1)-th element, the output of the adder-wichitas 3

_{m-1}connected with the information input unit 8 multiplication, the output of which through the shifter 4

_{2}connected to the input of the second summand (wichitaeagle) adder-vicites 3

_{m}and directly to the first information input of the multiplexer 7

_{m}the output of the adder-calculator 7

_{m}connected to the second information input of the multiplexer 7

_{m+3}the first information input connected to the output of the first register, and the output from the first output setprocessor 12

_{1}the second information input of the multiplexer 7

_{m}connected through the shifter 4

_{3}with output register 1

_{1}and the output is connected to the first information input of the multiplexer 7

_{m+1}and to the inputs of the second term (wichitaeagle) adders-vychitala 3

_{m+2}.3

_{2m-1}the second information input of the multiplexer 7

_{m+1}connected to the reference input of the active ingredient is of the motor 3

_{m+1}control inputs of the adders-vychitala 3

_{m+2}.3

_{2m-1}connected to the outputs of the multiplexers 7

_{2}.7

_{m-1}respectively, and the control input of the adder-vicites 3

_{m+1}connected to the output of the multiplexer 7

_{m+2}the first information input connected to the output of the multiplexer 7

_{1}and the second with the output of the multiplexer 7

_{2}control inputs of all of the multiplexers connected to the reference input in binary mode setprocessor 15, the outputs of adders-vychitala 3

_{m+1}.3

_{2m-1}are the outputs of setprocessor 10

_{2}.10

_{m}accordingly, the output of the decoder, mark 2

_{1}connected with the control unit changes the sign of the number 9 and the controlling input of the adder-vicites 3

_{m}the input synchronization registers 1

_{1}.1

_{m}connected to the synchronization input of setprocessor 11.Setprocessor can operate in one of three modes.The work of setprocessor in modes 1 and 2 can be described by the following expression:

< / BR>

where i is the iteration number.The values of a and C

_{j}defines the operating mode of setprocessor.In mode 1

< / BR>

In this mode, the algorithm (1) describes one of the n PR who is with the first of the m coordinate axes, the first element of the vector is equal to the module of the vector, and the remaining coordinates of the vector will be zero.In mode 2

< / BR>

In this mode, the algorithm (1) describes one of the n transformation vector according to the method of Gaussian or Gauss-Jordan), in which the original source vector X

_{0}(x

^{(}

_{1}

^{0)}x

^{(}

_{2}

^{0)}, ..., x

^{(}

_{m}

^{0)}converted to a vector Y(x

^{(}

_{1}

^{0)}, 0, ..., 0).

Mode 3 is auxiliary and is designed to perform a division operation on the same device, which is necessary for solving systems of linear algebraic equations with a triangular matrix.The work of setprocessor in mode 3 can be described by the following expression:

< / BR>

where

< / BR>

In this mode, the source vector X

_{0}(x

^{(}

_{1}

^{0)}, 0, x

^{(}

_{3}

^{0)}) is converted to a vector Y(x

^{(}

_{1}

^{0)}x

^{(}

_{3}

^{0)}/x

^{(}

_{1}

^{0)}, 0). The remaining coordinates of the input and output vector in this mode are not used and can be arbitrary.Consider the work of setprocessor on the i-th iteration. The operands of the components of the vector X

_{i}recorded in the registers 1

_{1}.1

_{m}at the entrance the entrance 11 setprocessor. The inputs 13

_{1}.13

_{m}served operands, the signs of which decoders mark 2

_{1}.2

_{m}and the XOR circuit 6

_{1}.6

_{m-1}produce control signals adders-vycitalem according to the ratios(2), (3), (5).The multiplexers 7

_{1}.7

_{m-1}and 7

_{m+2}serve for switching the generated control signals by the adders-vycitalem in accordance with the mode, binary code which is specified at the input 15. Shifters 4

_{1}and 4

_{2}serve to shift the number by i bits, the output unit changes the sign of the number 9 will be the value of -2

^{-i}x

_{1}C

_{1}to which the adder-myCitadel 3

_{1}added (deducted) the value of x

_{2}c

_{2}. Thus, at the output of the adder-vicites 3

_{m-1}it will mean -2

^{-i}x

_{1}c

_{1}+x

_{2}c

_{2}+ + x

_{m}c

_{m}that is fed to the input of block multiplication 8. Block multiplication is to multiply the input number depending on the number of inertia to one of the n constants -2(m-1+2

^{-i})

^{-1}. The output of block multiplication to obtain the value a, through which the shifter 4

_{2}forming the value a2

^{-i}, is supplied to the adder-myCitadel 3

_{m}. Thus obtained of the engine 4

_{3}. The multiplexer 7

_{m}selects one of these values depending on the mode. From the output of the multiplexer 7

_{m}the value a is supplied to the inputs of the second term (wichitaeagle) adders-vychitala 7

_{m+2}.7

_{2m-1}directly on a corresponding input of the adder-vicites 3

_{m+1}through the multiplexer 7

_{m+1}on the second information input of which is fed the value of d from the reference input binary weight of the treated discharge 14. The multiplexer 7

_{m+1}in modes 1 and 2 connects to the input of the second term (wichitaeagle) adder-vicites 3

_{m+1}the value of a, and in mode 3 value d according to (4). In modes 1 and 2 adders-vicites 3

_{m}.3

_{2m-1}line-by-line implement equation (1), and in mode 3 adders-myCitadel 3

_{m}.3

_{m+2}line-by-line implement equation (4). The values of Y

_{2}. Y

_{m}obtained at the outputs of adders-solvers 3

_{m+1}.3

_{2m-1}respectively, are fed directly to the outputs of setprocessor, and a value of Y

_{1}output of setprocessor through the multiplexer 7

_{m+3}that connects the corresponding output with the output of the adder-vicites 3

_{m}in mode 1 and output register 1

_{1}in modes 2 and 3. All multiplex the-th iteration ends. The next iteration can be performed sequentially in the same device, if you connect the outputs 12

_{j}with inputs 10

_{j}(j=1,2,m), or in pipelined mode with n devices, as shown in Fig.2. The values applied to the inputs 13

_{1}.13

_{m}the j-th device (j=1,2,n) depend on the mode of the device, but also on whether the device column of the matrix, which is zero off-diagonal elements in the current step (main column), or the device is processed by one of the other columns of the matrix (the dependent column) to preserve the linearity of the conversion.In modes 1 and 2 during the processing of the main column inputs 13

_{1}.13

_{m}the j-th devices are connected to the inputs 10

_{1}10

_{m}this device respectively, while processing a dependent column with inputs 10

_{1}.10

_{m}device for machining the main column. In mode 3 inputs 13

_{1}and 13

_{3}the j-th devices are connected respectively to the inputs 10

_{1}and 10

_{3}that device. The signal applied to the inputs 13

_{1}.13

_{m}the j-th device form a bus Z

^{(j)}and a common bus Z, shown in Fig.2.In Fig. 3 shows the circuit connection for the cast of the matrix A ({a

_{ij}}) dimensions (mxm) to the upper triangular form by means of orthogonal transformations reflections (mode 1) or by decomposition of a matrix into triangular multipliers according to the method of Gauss (mode 2). The device U

_{1}handles the main column, and the device U

_{2}.U

_{m}dependent columns of the matrix. Inputs Z each device is connected as described above to form the tire Z in Fig.3. In the transformation of all the elements of the first column of the matrix, in addition , will be zero, and the element will be equal to the module of the vector (mode 1) or (a

_{11}(in mode 2). After exclusions (zero) podiagonalnee elements of the first column, the same procedure is carried out with a matrix of order (m-1) to exclude podiagonalnee elements of the second column.After (m-1)-th similar step, the resulting matrix is an upper triangular matrix after these manipulations in mode 1 with rows of matrix - dwuhvalentnoe.If in mode 2 at each step does not reduce the dimensionality of the space, and to use the released modules for exceptions and addiionally elements, the resulting matrix will be a diagonal initial method (Gauss-Jordan).For triangulation matrix in raisiny column in the selected mode, for processing of column free members similar to the columns of the matrix.In Fig. 4 presents a scheme to perform "reverse" (the solution of a triangular or diagonal matrix when solving systems of linear algebraic equations. Device U

_{1}U

_{2}U

_{3}represent the device shown in Fig.2. Device U

_{1}works in mode 3, when the input X is a vector (a

_{mm}, O, b

_{m}), where a

_{mm}element of the system matrix, b

_{m}element column free members, the output Y of the device is obtained vector, the first element of which is the value of the element of the vector solution x

_{m}=b

_{m}/a

_{mm}. In the case of a diagonal matrix to obtain a vector solution it is enough to make m such operations. In the case of a triangular matrix after receiving x

_{m}you need to go to the matrix of dimension (m-1), transforming the vector of free members. To do this, use the device U

_{2}processing the dependent column-vector (x

_{m}b

_{1}b

_{m-1}), and the device U

_{3}processing the main column vector (1, a

_{1m}, a

_{m-1m}). As a result, the conclusions of the device U

_{2}the result is a vector Y (x

_{m}b

_{1}-a

_{1m}x

_{m< is by solving m linear systems of algebraic equations with the same matrix and m different columns free members, and for finding the determinant of a matrix and solving some other problems of linear algebra.The effectiveness of the invention consists in the extension class solved by the device of tasks, and it does so at the expense of a small increase in the cost of equipment. Matrix setprocessor containing three cases, three decoder badge, six adders-vychitala, three shifter, and the control inputs of shifters connected to the reference input of the binary code the number of iteration of setprocessor, the output of the first register is connected to the information input of the first shifter, characterized in that it introduced m-3 registers, m-3 decoders mark, 2m-7 adders-vychitala, m-1 exclusive or circuits, m+3 multiplexers, where m is the dimensionality of the processed matrix block multiplication unit changes the sign of the number, moreover, the information inputs of all the registers are the input operands setprocessor, the synchronization inputs of all the registers is connected to the synchronization input of setprocessor, the control input of block multiplication is connected to the reference input of the binary code the number of iteration of setprocessor, the output of the first shifter through the block changes the sign of the number, the control input of which is connected to virsago term (reducing) the j-th element (j=1,2,m-1) is connected to the output of the (j-1)-th element, and the sign of the second term (wichitaeagle) output (j+1)-th register, the output of the last element of the chain is connected to the information input unit of multiplication, the output of which is connected to the information input of the second shifter, the input of the second summand (wichitaeagle) of the first output adder-vicites connected to the output of the second shifter, the input of the first term (reducing) the i-th output of the adder-vicites (j 1, 2, m) is connected to the output of the first register, the output of the i-th output of adder myCitadel, except the first, connected to the i-th output setprocessor, the input of the i-th decoder of the mark is the i-th input of the analysis of the sign of the operand setprocessor, the output of the first decoder of the sign is connected to the control input of the first output adder-myCitadel, the output of the first register through the third shifter connected to the first information input of the m-th multiplexer, the second information input connected to the output of block multiplication, and output with inputs of the second term (wichitaeagle) each output of the adder-myCitadel, except the first and the second output of the first output adder-vicites connected with the second information input of the (m + 3)th multiplexer, the first information input of which is connected to the aircraft by the second input (j 1) th XOR circuit, the second input of which is connected to the output of the first decoder badge, output (j 1) th XOR circuit connected to the first information input of the (j 1)-th multiplexer, the second information input connected to the output of the j-th decoder token, the output of the j-th multiplexer (j 1,2,m 1) is connected to the control input of the j-th adder-vicites in the chain and to the control input of the (j + 1)-th output of the adder-myCitadel, except for the first and second, the output of the second multiplexer is connected to the second information input of (m + 2)-th multiplexer, the first information input connected to the output of the first multiplexer, and the output with the control input of the second output adder-myCitadel, the first information input of the (m + 1)-th multiplexer connected to the output of the m-th multiplexer, the second information input with the input binary weight of the treated discharge setprocessor, and the output to the input of the second term (wichitaeagle) of the second output adder-vicites control inputs of all of the multiplexers connected to the reference input binary mode setprocessor. }

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7 cl, 10 dwg, 1 tbl

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6 cl, 7 dwg

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28 cl, 18 dwg

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