The memory element

 

(57) Abstract:

Usage: in computing, to build a reprogramming storage devices. The inventive memory element includes a semiconductor base in the form of a single crystal layer or the polycrystalline film layer, coupled bipolar transistors with metallization separated by insulating layers, conclusions, write, read, erase and terminals of the power source. A pair of bipolar structures placed on the face side of the semiconductor substrate, and along its length are consistently insulating layer, and a layer of ferromagnetic material containing two pole tip. Bipolar transistors in the pairs are connected in series, the lower emitters of the bipolar transistors of the pairs is connected to the housing, the collector of the upper transistor pairs connected to the power source and the base of the upper transistors of each pair by means of resistors connected to the bases of the lower transistors of adjacent pairs. 2 Il.

The invention relates to computing, and in particular to a storage device, and can be used to build a reprogramming storage devices.

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The memory element comprises a semiconductor base (substrate) 1, the bipolar transistors 2 and 3, the left pair of ohmic contacts to the emitter 4, the base 5 and the collector 6 of transistor 2 and the emitter 7 base 8, the collector 9 of the transistor 3, the bipolar transistors 10 and 11, the right pair of ohmic contacts to the emitter 12, the base 13, the collector 14 of transistor 10 and the emitter 15, a base 16, the collector 17 of transistor 11. Ohmic contacts 6 and 14 to the collectors of the transistors 2 and 10 are both ohmic contacts to the semiconductor substrate 1.

In accordance with Fig. 2, the emitters of the transistors 2 and 10 by means of metallization in the form of a metallic film layers 18, separated by layers of dielectric 19, directly connected with each other and with the casing, the collector 6 of transistor 2 is connected directly with the emitter 7 of the transistor 3 and the emitter 15 of transistor 11 is connected to the collector 14 of transistor 10. Between the collectors of the transistors 2 and 10 inclusive of the semiconductor base 1, which represents the diagonal of the bridge, consisting of the bipolar transistors 2, 3, 1, 11. The upper base of the bipolar transistor 3 left pair is connected through resistor 20 to the base of the lower transistor 10 right pair and the base of the upper bipolares pair. The length of the substrate, on the contour is the insulating layer 22, on which is formed a layer of ferromagnetic material 23 containing two pole piece 24 and 25, and perpendicular to the pole tips of the sides of the semiconductor substrate 1 are electrodes reader 26, one of which is connected with the General conclusion 27.

The memory element also contains the output record 28, the output of the erase 29 and the output of power supply 30. If the level recorded in the memory element information signal (bit) the following is valid for the particular type of logic is used amplifying element 31, which provides increased levels of recorded data to the desired values. This element represents the DC amplifier field-effect transistor realized by integrated technology.

Left and right pairs in contact with a semiconductor base 1 bipolar transistors 2, 3 and 10, 11, metallization and interlayer insulation is implemented by a standard hybrid and solid-state technology with the standard topology, the film thickness, with standard sizes of active and passive elements. The insulating layer 22 is formed along the entire length of the semiconductor substrate 1 and has then coprostasia areas of metallization. Their optimum thickness of 1-5 μm. The layer of ferromagnetic material 23 made of a hard magnetic material, for example of the type of alni or ferrite with a rectangular hysteresis loop (Nickel-zinc ferrites brand of 1.5 W, 1.3 W, 2 W), and pole pieces 24, 25 of magnetic material such as permalloy, soft-magnetic manganese-zinc ferrites 1500 nm, and the thickness, as shown by the results of an experiment is 5-20 μm. Pole pieces 24, 25 are separated from the layer of ferromagnetic material (magnetic core) 23 the insulation layer, and the contact is in the middle part to getting the most out of the magnetic induction in the middle part of the semiconductor substrate 1. The optimal ratio of the lengths of the cap and the pole piece, as shown by the results of an experiment is(1:2)-(1:10). The sizes of the semiconductor substrate 1 depending on the type of material of the semiconductor substrate 1, the mobility and diffusion length of the carriers, the conductivity of the resulting information recording magnetic field. As shown by the results of the experiment, the ratio length-width of the semiconductor substrate 1 is from 3:1 to 1:1, and the thickness of the substrate 1 made of monocrystalline floor is tx2">

As the material of the substrate 1 using the electronic semiconductor with high mobility of carriers and small resistance is germanium or silicon with av=0,5210-2Ω m, 0.3 m2/(B c), antimony India 4,o m2/(B c), indium arsenide with 1.5 m2/(B c).

The memory element operates as follows. When applying a recording signal to the recording 28 is opened transistors 3 and 10 and through the semiconductor base 1 carrying current I0B1Icwhere Iccurrent recording signal, and B1the average gain current of the transistors 2 and 10. Flowing through the substrate current I0creates a layer of ferromagnetic material 23 of the magnetic field, the induction of which

,

whereomagnetic constant and the relative magnetic permeability of the ferromagnetic material 23,

r0the radius drawn from the middle of the base 1 to the ferromagnetic layer 23.

After the departure of the recording signal in the hard magnetic layer of ferromagnetic material 23 will be recorded information representing the residual induction B of the specified layer 23. Through the pole pieces 24 and 25 of magnetic ferromagnetic material induction B acts on the semiconductor base is about to conclusions 27 and 30 of the supply voltage.

To read the recorded information from the memory element should be applied to its electrodes 27, 30 supply voltage, and the input of the write pulse. In the flow through the semiconductor base 1 of the current pulse and actions perpendicular to the current magnetic field on the electrodes reader 26, a signal will appear read (EDS Hall) in accordance with addiction

,

where d is the thickness of the semiconductor substrate.

Amplifying element 31 provides the desired amplification of the recording signal ("0", "1") up to the specified level.

To erase the information for later transfer to the output of the erase signal erase (for example sinusoidal modulation exponent), which removes the recorded information. In this case, will be included in the work of the transistors 2 and 11, and through the semiconductor base 1 the current flows in the opposite current account direction. To record new information on the input record 28 should apply the desired tone.

Recorded information the proposed memory element stores after removing the supply voltage, that is, this element acts as an EPROM. In the same way, the proposed memory element will function and what was germanium size 2 x 1 mm and a thickness of 200 μm, which methods of photolithography, diffusion, epitaxy and sputtering were formed two triode pairs amplifying element, the layer of ferromagnetic material (magnetic core with pole pieces and the interlayer insulation. The specified value logic signals (1 3,8 B; "0" 0,2 (B) at the output of the amplifying element is formed by the recording signal voltage pulse 3,5-4,5 Century

A memory element containing a ferromagnetic drive transistor, conclusions, write, read, erase and output power, characterized in that the element is designed as a monolithic hybrid-film structure, the base being made of a semiconductor material, with the end sides of the base layers placed a pair of bipolar transistors, and along its length on both sides are consistently located insulation layer and the hard magnetic layer of ferromagnetic material containing two pole piece of magnetic ferromagnetic material, while the emitters are in contact with the semiconductor base, the internal transistor is connected to the housing, base far from the semiconductor base of the transistors of each pair through the resistive layers are connected to the bases of the internal transistor p is

 

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FIELD: semiconductor memory devices.

SUBSTANCE: device has a lot of memory elements, each of which contains input and output areas, isolating film, channel area, shutter electrode, area for storing electric charges, device also contains large number of periphery circuits, containing reading amplifier, register for storing recorded data of memory elements, register, which preserves the flag, indicating end of record during its check, and circuit, which after recording operation compares value, read from memory cell, to value, fixed by flag at the end of record, and overwrites value indicated by the flag.

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SUBSTANCE: device for determining logical state of selected memory cells in memory device with passive matrix addressing is made with possible connection to ferroelectric memory device or forming its portion and contains reading amplifying contours, synchronous amplifier, combined source of shift voltage and signal, active control line driver, multiplexer, a set of routers. Other variant of aforementioned device is additionally equipped with second set of routers. Method describes operation of aforementioned devices.

EFFECT: higher efficiency, broader functional capabilities.

3 cl, 12 dwg

FIELD: digital data processing.

SUBSTANCE: device in form of semiconductor memory device has control block with control elements and memory cells, each of which is made with possible connection to system of buses for connection to central processor and has an in-built microprocessor, including registers, made with possible storage of signs of start of data flow name and its end, information about state and mode of in-built microprocessor. Method describes process of data processing in aforementioned recording device.

EFFECT: higher speed of operation.

6 cl, 7 dwg

FIELD: physics; computer technology.

SUBSTANCE: invention refers to the method and device for the implicit preliminary charging of dynamic operative memory. The memory device contains at least one bank consisting of memory cells, organised into a set of lines of memory cells; and the logic control facility connected with at least one bank, and reacting to reception by the memory device to a command of activation of a single line for opening a particular line in such a manner that if there are no open lines when the command has been given, then at least in one bank it opens, and if in the bank another line is open, then the other line closes and the particular line opens. The device of management of memory contains the first site of storage in which is stored data relative to the lines in bank of memory cells in the memory device and a logical control tools transformed, committed to the memory cells. The methods describe the work of the specified devices.

EFFECT: expanding the functional capabilities of the device for preliminary charging of dynamic operating memory.

22 cl, 6 dwg

FIELD: physics; computer technology.

SUBSTANCE: invention refers to the method and device for the implicit preliminary charging of dynamic operative memory. The memory device contains at least one bank consisting of memory cells, organised into a set of lines of memory cells; and the logic control facility connected with at least one bank, and reacting to reception by the memory device to a command of activation of a single line for opening a particular line in such a manner that if there are no open lines when the command has been given, then at least in one bank it opens, and if in the bank another line is open, then the other line closes and the particular line opens. The device of management of memory contains the first site of storage in which is stored data relative to the lines in bank of memory cells in the memory device and a logical control tools transformed, committed to the memory cells. The methods describe the work of the specified devices.

EFFECT: expanding the functional capabilities of the device for preliminary charging of dynamic operating memory.

22 cl, 6 dwg

FIELD: physics, computer facilities.

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EFFECT: obtaining of possibility of predicting of of a storage device speed.

14 cl, 24 dwg

FIELD: information technologies.

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EFFECT: saving of critical data even in case of malfunction in game machine.

15 cl, 12 dwg

FIELD: information technologies.

SUBSTANCE: device comprises two CMDS inverters, two recording transistors of n-type, two transistors for reading of n-type and reading transistor of p-type. Output of the first CMDS inverter is connected to input of the second CMDS inverter, to gate of the first reading transistor of n-type and via the first recording transistor is connected to direct data bus. Output of the second CMDS inverter is connected to input of the first CMDS inverter, to gate of reading transistor of n-type and via the second recording transistor of n-type is connected to complementary data bus. Gates of recording transistors of n-type are connected to address recording bus. The first and second reading transistors of n-type are connected serially between shift bus and reading bus. Reading transistor of p-type is connected parallel to the first reading transistor of n-type, and gate of the second reading transistor of n-type is connected to address reading bus.

EFFECT: improved efficiency of device.

1 dwg

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to micro- and nanotechnology and can be used in designing dynamic memory, two-dimensional control matrices for liquid-crystal displays, high-speed and high-precision scanners, two-dimensional sensors, delay lines etc. The device uses a chain series-connected active functionally integrated cells which can control technologically compatible electric devices. Each cell of the chain is a simple electric circuit consisting of a MOS transistor, resistors and a capacitor. The time used is the delay time for switching off the MOS transistor relative the end of the output signal.

EFFECT: invention speeds up operation of the functional device, simplifies its manufacturing technology, reduces its size and improves its integration.

16 dwg

FIELD: information technologies.

SUBSTANCE: pseudo-dual-port memory contains the first port, the second port and array of memory cells with six transistors. The first call to memory is initiated by means of anterior front of the first synchronising signal (ACLK) received along the first port. The second call to memory is initiated in response to anterior front of the second synchronising signal (BCLK) received along the second port. If anterior front of the second synchronising signal occurs in the first period of time, than the second call to memory is initiated immediately after completion of the first call to memory by pseudo-dual-port method. If anterior front of the second synchronising signal occurs later in the second period of time, than the second call to memory is delayed till the time after the second anterior front of the first synchronising signal. Duration of the first and second calls to memory does not depend on beats of synchronising signals.

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37 cl, 16 dwg

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