Device for computing eigenvalues of (n n)- matrix

 

(57) Abstract:

1. Device for computing eigenvalues of (n x n) - matrix containing the computational module of the first type, l computational modules of the second type (1 < 2n) and the unit of analysis, and the i-th entry of the group of information inputs and the i-th input of the first group of control inputs of the device are connected respectively to the first information input and the first control input of the i-th computing unit of the second type, the first information input, the first and second control inputs connected respectively to the first information input, the first and second control inputs of the computing unit of the first type, the first information output processing module of the first type connected to the second information input of the first computing module of the second type, the first information output of the i-th computing unit of the second type connected to the second information input of the (i + 1)-th computing unit of the second type, the third information input of the i-th computing unit of the second type connected to the second information output (i + 1)-th computing unit of the second type, the second information output of the first computing normativnyi the output of which is connected to the first information input unit of analysis, the second information input of which is connected to the reference input precision computing device, engraved which is connected to the state clock inputs of all the computing modules and unit of analysis, the i-th output group output unit of analysis is connected to the i-th output group output device, the information output of which is connected to the output of the sign of the end of the computing device, wherein the i-th entry of the second group of control inputs of the device connected to the second control input of the i-th computing unit of the second type, the third control input device connected to the third control input computing module of the first type, the first and second control outputs of the computing module of the first type are connected respectively to the third and fourth control inputs of the first computing module of the second type, the first and second control outputs of the i-th computing unit of the second type are connected respectively to the third and fourth control inputs (i + 1)-th computing unit of the second type, and a computational module of the first type configured to implement the following functions:

< / BR>
wherejandjvalues respectively, the first and second przyczyny respectively on the first and second control outputs of the processing module to (j+1)-th clock cycle;

< / BR>
where ajand Cjvalues respectively, the first and second information inputs of the computing unit to the j-th clock cycle;

Dj+1and Cj+1values respectively, the first and second information outputs of the processing module to (j+1)-th clock cycle;

jvalues on the third control input computing module to the j-th step,

< / BR>
and the computational module of the second type is configured to implement the following functions:

< / BR>
wherejandjvalues respectively on the third and fourth control inputs of the computing unit to the j-th step,

Aj+andj+values respectively on the first and second control outputs of the processing module to (j+)-th clock cycle;

< / BR>
where Cj- the value for the second information input of the computing module in the j-th clock cycle;

Cj+- the value of the first information output processing module to (j+)-th clock cycle;

< / BR>
where ajand bjvalues respectively, the first and second information inputs of the computing unit to the j-th clock cycle;

Fj+n-1values on the second information output vycislitelnoj is managing the inputs of the computing unit to the j-th step,

j1j10values respectively on the outputs from the first to the tenth control unit computer module to the j-th step.

2. The device under item 1, characterized in that the unit of analysis contains 2n registers, n vychitala, n schema comparison, the divider module account (n+n), the divider module account n2the trigger, the three elements and the element OR, in the unit of analysis of the first information input unit of analysis is connected to the information input of the first register, the output of the i-th register is connected to the information input of the (i + 1)-th register to the i-th output group output unit of analysis and the first input of the i-th myCitadel, the second input is connected to the output (i + n) th register, the output of the i-th vicites connected to the first input of the i-th of the comparison circuit, second input schemas comparison and United are second information input unit of analysis, the output of the i-th of the comparison circuit is connected to the i-th input of the first element And whose output is connected to the output of the sign of the end of the calculation unit of analysis, engraved which is connected to the first inputs of the second and third elements And the counting inputs of the dividers modules account (n+n) and (n2), the output of the divider module account (n2connected to information is the first condition of the divider with the account module (n+n), the output of which the output of the second element And connected respectively to first and second inputs of the OR element, the output of which is connected to the second input of the third element And whose output is connected to the state clock inputs of all the registers.

 

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