The selector pseudo-random sequence of pulses

 

(57) Abstract:

The invention relates to digital computing and can be used in information-measuring systems, devices, analysis of the temporal structure of the pulse, the devices forecasting and periodic pseudoperiodicity sequences and other Selector pseudo-random sequence of pulses comprises a generator of clock pulses 1, n frequency dividers 2 - 1, ..., 2 - n, the control bus 3, n - inputs set the initial state 4 - 1, ..., 4 - n, n-pulse counters 5 - 1, . .., 5 - n, n RS-flip-flops 6 - 1, ..., 6 - n, the input prohibition 7, (n + 1)-th pulse counter 8, To - block delay 9 - 1,..., 9 - K, the information input 10, the output is 11. The delay block contains n storage devices 12 - 1, . . . , 12 - n, the first element AND NOT 13, three D-flip-flop 14, 15, 16, the second element AND - NOT 17, the And gate 18, the fourth D-flip-flop 19. 1 C. p, f-crystals, 3 ill.

The invention relates to digital computing and can be used in information-measuring systems, devices, analysis of the temporal structure of the pulse, the devices forecasting and periodic pseudoperiodicity sequences, etc.

Known select the Oia periodic sequence of pulses and comprising a generator of clock pulses, the pulse counter, the delay elements, the threshold device. These selectors do not provide the selection SRP pulse, as it does not provide a delay of the input signal simultaneously on several independent time intervals and require special threshold devices for making decisions about the presence of the useful signal.

The closest in technical essence to the invention is selected as a prototype tunable selector pulse sequences [3] contains a generator of clock pulses, the control bus, two counters, the first of which is the divider pulses, connected to control inputs to the control bus, and the output of the overflow to the input of the zero of the second pulse counter, in addition, the first trigger, the third pulse counter, the counting input of which is connected to the counting inputs of the first two counters and generator output clock pulses, the output of the overflow account of the first pulse counter is connected to the counting input of the first flip-flop, two storage devices inputs the read (write) which is connected to the direct and inverse output of the first flip-flop, respectively, informational inputs are connected with the input set initial state of the third pulse counter connected to the output of the overflow of the first counter pulse, the control input of the low order of the second and third pulse counters connected with the input of the read (write) the first and second storage devices, respectively, the Assembly element, the first and second inputs which are connected to the outputs of the storage devices, respectively, the element of coincidence, the first and second inputs which are connected to the input selector and the output element of the Assembly, respectively, two one-shot, the second trigger, the S-input connected to the output element matches after the first one-shot, R-entrance to the entrance of the selector through the second one-shot, and the output from the first input unit of the ban, a second input connected to the output of the first pulse counter.

Block the ban includes serially connected pulse counter, a trigger input recording resolution of which is connected to the input of the installation of the meter pulses in the initial state and the second input unit of the ban, the trigger element matches the first input of which is connected to the counting input of the counter and the first input unit of the ban, and one trigger output. The output element of coincidence is output.

This tunable selector has the following disadvantages: (a) does not provide you the mode sequential write (read), does delay element bulky.

These shortcomings do not allow you to use the selector prototype, and apply without changing the delay element to highlight the SRP pulses, the main feature of which is the presence of a pulse on one of n possible time positions measured relative to the next received pulse of this sequence. Moreover, the number of these positions, as well as the possible time interval between two adjacent pulses in each case are known, and the position of the pulse at one of the positions is random. These types of signals are used in modern radar stations.

The technical problem of the invention consists in the selection of the SRP pulses by delaying the input stream signals simultaneously on the n-time slots resulting from the use of n delay elements while simplifying their circuitry, logic multiplying the delayed signals with the input for selecting the SRP pulse, and increase the noise immunity of the selector SRP in large flow noise and interference signals due to the introduction of additional blocks of delays for re (mnogokrat>/P>The task is solved in that in the known device, comprising a generator of clock pulses, the first pulse counter, the first frequency divider, a control bus, connected with control inputs of the frequency divider, the output of the overflow of which is connected to the input of the zero pulse meter, according to the invention, introduced (n 1) frequency divider control inputs which are connected respectively through the ranks with the relevant conclusions of the specified control bus inputs set the initial state of the n-frequency divider with corresponding inputs set the initial state of the selector, n RS-triggers S-inputs are connected together and to the input of the ban delay selector and R inputs are connected with the inputs set the initial state of the respective frequency dividers, (n 1) pulse counters, the counting inputs of which are connected with the counting inputs of the n-frequency divider and a counter input of the first pulse counter, and the inputs zero with o (n 1)-th frequency divider, respectively, (n + 1)-th pulse counter, a counting input connected to the output of the generator of clock pulses, the output of the last category with a counter input of the first counter pulse is output bits of the respective pulse counters, n-inputs allow the selection of delay blocks connected to each other, respectively, and output the corresponding RS flip-flop (n + 1)-th input of the first delay unit connected to the information input of the selector, (n + 1)-th input of each subsequent unit delay with the second output of the previous delay block, (n + 2)-th inputs of all units of delay are connected with the output of the overflow account (n + 1)-th counter of pulses (n + 3)and the input of all units connected with each other and with the release of senior level (n + 1)-th counter of pulses (n + 4) th inputs - between themselves and with the first output of the first delay unit, the second output of the last delay block is the output of the selector.

In the selector, the delay block contains n storage devices, the address inputs are connected to respective conclusions n-bus inputs respectively, the inputs allow the selection of storage devices to the corresponding inputs allow the selection unit, inputs the read (write) - between and (n + 2) th input of the delay block, the first element AND NOT, three D-flip-flop, the inputs zero which are connected with the D input of the first D-flip-flop and the output of the first element AND NOT, the synchronization input of the first D-flip-flop is connected to the (n + 1)-th entry of amenta AND NOT with (n + 3)-th entry unit, the second input element AND is NOT connected to the output of the third D-flip-flop, D-input of the second D-flip-flop connected to the output of the first and the third input with the output of the second D-flip-flop inverted output of the first D-flip-flop connected to connected between a data input storage devices, the second element AND NOT the element And the fourth D-flip-flop, a synchronization input connected to the output element And the input set to zero with its D-input and the output of the first element AND NOT the first input element And (n + 4)-m input unit, the second input element And is connected to the output of the second element AND NOT, each of the n inputs is connected to the output of the corresponding storage device, the output of the first D-flip-flop is the first output unit, and the output of the fourth the second output unit.

In Fig. 1 shows a structural circuit diagram of the selector SRP pulses and structural electrical diagram of the delay unit, and Fig. 2, 3 - time diagrams of the selector and the operation of the delay block.

The device Fig. 1 includes a pulse generator 1, n-frequency divider 2

1, 2 n, the control inputs of which are connected to the control bus 3, and the inputs set the initial state of the inputs set the initial is sootvetstvujushij frequency dividers, and counter inputs are connected with the counting inputs of the frequency dividers, n RS-triggers, 6 1, 6 n, S-inputs of which are connected together and to the input of the ban selector SRP 7, and R-inputs of each of them with the inputs of the selector 4 1, 4 n, respectively, (n + 1)-th pulse counter 8, a counting input connected to the output of clock 1, and the output of the last category with a counter input of the first frequency divider, series-connected delay blocks 9 1, 9, n-bus inputs which R1, W-n are connected, respectively, with the respective bit outputs of the pulse counter 5 1, 5 n, n-enable inputs of the choice are connected, respectively, to the outputs of the RS-flip-flops 6 1, 6 n, respectively, (n + 1)-th input of the first delay unit 9 1 is connected with the information input selector 10, (n + 1)-th input of each subsequent unit delay with the second output of the preceding delay unit 9 2 9 1, 9 9 (1), (n + 2)-th inputs of delay blocks connected with each other and with the release of overflow account (n + 1)-th pulse counter 8, (n + 3) and the input delay blocks 9 1, 9 are interconnected and senior level (n + 1)-th pulse counter 8, (n + 4) th inputs among themselves and with the first output of the first delay unit 9 1, and in RIT n storage devices 12 1, 12 n address inputs are connected to the terminals of R1 tyres, noise reduction, respectively, a selection input with n inputs allow the selection unit, respectively, and inputs the read (write) between themselves and with the input of the (n + 2) block, the first element AND NOT 13, three D-flip-flop 14, 15, 16, inputs zero which are connected with the D-input of the first flip-flop 14 and the output of the first element AND NOT 13, the synchronization input of the first D-flip-flop 14 is connected to the (n + 1)-th input unit and the input synchronization triggers 15, 16 are connected with the first input element AND NOT 13 and (n + 3)-th input block, the output of the third D-flip-flop 16 is connected to the second input of the first element AND IS NOT, the output of the first flip-flop 14 is connected to the D-input of the second trigger 15 and the second output of the D-input of the third trigger 16, the inverted output of the first D-flip-flop 14 is connected to is connected between a data input storage devices 12 1, 12 n, the second element, AND NOT 17, the And gate 18, and the fourth D-flip-flop 19, the input D of which is connected with its input set to zero and the output of the first element AND NOT the input synchronization with the output element And 18, the first input connected to (n + 4) th input unit and one output of the second element AND NOT 17, each of the n inputs is connected to the output of the corresponding thetrigger 17 second output unit.

As frequency dividers can be used commercially available chip VI or cascaded registers IR and counters IE or IE, as a storage device RU, RU and other element AND LI, as an element AND NOT LA or chip LI and LN included according to the recommendations [4] as a D-flip-flop TM.

The selector SRP pulses is as follows.

To the input of the selector 9 receives the signal flow (Fig. 2 (a), which along with the useful signal (SRP pulse) contains noise: periodic sequence of pulses, the periods of repetition which Tpnot coincide with the values of the possible time interval SRP tuand a random noise. This flow signal is delayed by the delay elements 12 - 1, 12 n at intervals of time tu1, tunwhat pre-feed pulse selection from input selector 10 RS-triggers are set to "1". Thus the outputs of the storage devices are in a state of high impedance (the chip is not selected).

Then, on the control bus 3 exhibited a code that corresponds to the value of the i-th time interval tuand bus KJV is set to RS-trigger 6 i in state "0", and the storage device 12 (i translated it into working condition. This procedure enable mass storage devices 12 may be necessary in cases when the number of possible time intervals of breeding SRP less than the number available in the unit delay elements n to exclude the influence of unused storage devices information on the resulting voltage from the outputs of the delay blocks. Read address write to memory devices formed by the counters 5 1, 5 n in arriving at their counting input pulses (Fig. 2B), the repetition Cycle address read (write)" is determined by the division ratio of the respective frequency divider 2 1, 2 n. Coming to the information input of the delay elements 12 1, 12 n information (Fig. 2A) is delayed by the interval tu1, tulin the first delay unit (Fig. 2B, 2C, 2D), (where l 3 the amount specified in the SRP time intervals) and the result of the logical multiplication with nederzhanyem signal (Fig. 2A) on the second output of the delay block is formed resulting signal (Fig. 2E). (Detailed operation of the delay block is discussed below (Fig. 3).

From the second output of the first delay block, the resulting signal, prohodit the resulting voltage (Fig. 2K). Thus, passing through the first delay block interference (Fig. 2E) are eliminated after repeated delays (Fig. 2K).

Usually to eliminate disturbances are 2-3-fold signal delay.

The delay unit operates as follows. Entering the input information is stored by each delay element in the cycle time tu. The duration of the reading process stored in the storage device information and records to newly received information is determined by the capacity of the (n + 1)-th pulse counter 8 and the pulse frequency of the clock generator 1 (Fig. 3A). Change of address of the storage device is at a positive differential voltage at the input of counter 5 1, 5 n (Fig. 3b). The reproduction of information is carried out through the time delay tgtuin logical units with output overflow pulse counter 8, and the recording negative differential voltage (Fig. 3b).

The use of short pulse recording allows you to reduce the presence of noise on the outputs of the storage devices due to their transition at the time of entry into the state of the logical unit.

Entering block information is mo, to resolve skip the useful signal at the output multiplied element And 18, due to the discrete nature of the signal delay and instability intervals of the pulse repetition SRP.

The pulse extender is assembled on the elements 13 to 16. In the initial state, the voltage at the outputs of the triggers 14 16 0 (Fig. 3D, 3E, g), respectively, and the voltage at the output of the first element AND NOT (Fig. S) - logical unit. When the input pulse at the positive differential voltage trigger 14 passes into the state of the logical unit, then two subsequent positive differential voltage at the inputs of synchronization triggers, 15, 16 (Fig. 3b), the voltage of the logic unit on their outputs in series (Fig. 3E, g). As a result, the output of the first element AND NOT 13 is formed voltage logical "0", which puts the elements 14, 15, 16 in the initial state. With the inverted output of the first trigger 14 (Fig. 3i) the signal is sent to the information inputs of the storage devices for recording, reading signal is delayed tgat cycle tu. For recording and reading are two adjacent cells of memory devices. Received signals have a level is Suppl function of the logical multiplication of the extended input signal (Fig. 3D) and delayed (Fig. 3K). To eliminate interference ("rents"), occurring at the output of the element, And by switching the storage device in the write mode, and when changing addresses and for expansion of output pulses at the input of the next delay unit, to the duration, ensuring their entry in two adjacent cells of storage devices, the selected pulses (Fig. 3) extend the duration of the D-trigger 19.

When the trigger 19 is transferred into the state "1" the first positive voltage (Fig. 3l) and returns to the "0" signal (Fig. S). The output signal of the block is represented (Fig. 3M).

Thus, the objective is formulated on the allocation of the SRP pulses and increase the noise immunity of the selector in large flow noise and interference signals is solved using the proposed device.

1. The selector pseudo-random sequence of pulses comprising a generator of clock pulses, the first pulse counter, the first frequency divider, a control bus connected to the control inputs of the frequency divider, the output of the overflow which is connected to the input of the zero pulse meter, characterized in that it introduced n 1 frequency dividers, pack the Anna bus control inputs set the initial state of the n-frequency divider to the corresponding inputs of the set state of the selector, n RS-flip-flops, S-inputs are interconnected with the inputs ban delay selector and R inputs are connected with the inputs set the initial state of the respective frequency dividers (n - 1) pulse counters, the counting inputs of which are connected with the counting inputs of the n-frequency divider and a counter input of the first pulse counter, and the inputs zero with o (n 1)-th frequency divider, respectively, (n + 1)th pulse counter, a counting input connected to the output of the generator of clock pulses, the output of the last category with a counter input of the first pulse counter, and K blocks, delays, n-bus inputs which are connected, respectively, each of the tire connected to the output bits of the respective pulse counters, n-inputs allow the selection of delay blocks connected respectively with the output of the corresponding RS flip-flop (n + 1)-th input of the first delay unit connected to the information input of the selector, (n + 1)the third input of each subsequent unit delay with the second output of the previous delay block, (n + 2)-th inputs of all units of the delay of the trading among themselves and with the release of senior level (n + 1)-th pulse counter, (n + 4) th inputs - between themselves and with the first output of the first delay unit, the second output of the last delay block is the output of the selector.

2. The selector on p. 1, wherein the delay block includes n storage devices, the address inputs are connected to respective conclusions n-bus inputs respectively, the inputs allow the selection of storage devices to the corresponding inputs allow the selection unit, the inputs of the read/write between a and C (n+2) th input of the delay block, the first element AND NOT, three D-flip-flop, the inputs zero which are connected with the D input of the first D-flip-flop and the output of the first element AND-NOT the synchronization input of the first D-flip-flop is connected to the (n+1)-th input unit and the synchronization inputs of the second and third D-flip-flops interconnected to the first input of the first element AND NOT with (n+3) th input unit, the second input element AND is connected to the output of the third D-flip-flop, the D input of the second D-flip-flop connected to the output of the first and the D-input of the third with the output of the second D-flip-flop, inverted output of the first D-flip-flop connected to connected between a data input storage devices, the second element AND-NOT element And the fourth D-flip-flop, the input synchronize, the first input element And (n+4) th input unit, the second input element And is connected to the output of the second element AND each of the n inputs is connected to the output of the corresponding storage device, the output of the first D-flip-flop is the first output unit, and the output of the fourth the second output unit.

 

Same patents:

The invention relates to computer technology and can be used in digital systems for control channel synchronization system elements

Paraphase inverter // 2030107
The invention relates to a pulse technique

The invention relates to computer technology and can be used in digital automatic systems, in particular for control of tape drives

The invention relates to a pulse technique and can be used in digital computing and engineering to restore the distorted pulses, solves the problem of correcting the distortion of signals of type "split" pulse

The invention relates to techniques for processing digital data, in particular to a device for error detection, and may find application in digital transmission systems

The invention relates to the field of control-measuring equipment and can be used for tolerance frequency control in systems automation and control

FIELD: digital pulse engineering.

SUBSTANCE: proposed device designed for shaping pulses of desired length for each of three events during power turn-on in response to off-operation button signal incorporating provision for chatter elimination in case of skip or stop of changes in input pulses on detection enabling has first and second monostable restart multivibrators 1, 4, off-operation button 2, flip-flop 3, shaper 5 of signal responding to button-provided power turn-on which is built around capacitor 12, resistors 13, 14, diode 15 and two NAND gates 6,7, as well as AND gate 8, controllable pulse generator 9, logical 1 input, pulse signal input 10, and control input 11. Controllable pulse generator 9 is built around AND gate 16, NAND gate 17, resistors 18, 19, and capacitor 20. Device can shape input pulse during power turn-on period and function as hardware watch timer implemented in the course of forward and backward automatic interaction with system microcontroller.

EFFECT: enlarged functional capabilities of device.

1 cl, 1 dwg

FIELD: digital pulse engineering.

SUBSTANCE: proposed device that can be used for shaping output pulses of desired length for each of three events (power turn-on, detection of input-signal pulse skipping or hanging [stop of changing] when detection is enabled in response to signal from closing button, including chatter suppression) provides for shaping output pulse during power turn-on and can function as hardware watch timer enabling generation of output pulse in case of skipping or hanging of input signal pulse. Device has first and second resistors 1, 2, closing button 4, capacitor 5, logical follower 6, inverted pulse signal output, common bus, and power supply bus. In addition, device has third resistor 3, NAND gate 7, first and second AND gates 8, 9, power turn-on and push-button signal integrator 10, pulse detector 11, pulse signal input 12, and control input 13.

EFFECT: enlarged functional capabilities.

1 cl, 1 dwg

FIELD: digital pulse engineering.

SUBSTANCE: proposed device designed for shaping output pulses of desired length for each of three events, that is, signal front across first control input, signal zero level from closing button incorporating provision for chatter suppression, and detection of pulse skipping across signal pulse input has seven resistors 1 - 7, two capacitors 11, 18, button 10, first and second control inputs 12, 13, pulse input 14, AND gate 17, NOT gate 8, two NAND gates 9 - 16, NOT gate with open collector output 15, and pulse signal envelope detector 19. This pulse shaper can be used, for instance, as system reset pulse shaper of numeric control device.

EFFECT: enlarged functional capabilities.

1 cl, 1 dwg

Impulse selector // 2309532

FIELD: impulse engineering, possible use in impulse analyzing devices to select impulses with given parameters of duration, amplitude and period.

SUBSTANCE: device contains differentiating element, zero level limiter, inverter, three delay blocks, key, adder, multi-level amplitude selector, commutator, trigger, saw-shaped voltage generator, AND element, subtracting device.

EFFECT: expanded functional capabilities of device due to selection of both periodic impulses with given duration and amplitude parameters, and impulses appearing in random time moments.

2 dwg

FIELD: impulse engineering, possible use in devices for analyzing impulses to select impulses with given parameters of duration, amplitude and period.

SUBSTANCE: device contains input impulse generator, three delay blocks, key, adder, multilevel amplitude selector, commutator, trigger, saw-shaped voltage generator, AND element, subtracting device.

EFFECT: expanded functional capabilities due to selection of both periodic impulses with given parameters and impulses which appear in random time moments.

2 dwg

FIELD: radio engineering, possible use for finding a stack of mutually coherent impulses.

SUBSTANCE: device contains input block, connected to first input of adder. Second input of adder is connected to output of reverse communication amplifier. New feature is the introduction of compensating amplifier and band filter. Input of amplifier is connected to output of delay line, and output of amplifier is connected to input of band filter. Delay line consists of input, intermediate and output of inter-digital transformers on sound-conductive substrate. Duration of interaction of train of waves in output inter-digital transformer is selected to be several times or several dozen times greater than delay of signal between input and intermediate inter-digital transformers, output inter-digital transformer is made in form of continuous mono-periodical structure, matched with carrying frequency of received radio-impulses, and connected to input of compensating amplifier. Pass band in band filter is selected to be commensurable with reverse value of duration of radio-impulse signal generated in output inter-digital transformer.

EFFECT: increased detection capability of accumulator without worsening of its stability.

2 dwg

FIELD: radio engineering and impulse engineering, possible use for selection and measurement of parameters of regular and random impulse series.

SUBSTANCE: impulse series selector contains input impulse generator (1), at first and second outputs of which impulses of constant duration are generated, proportional to amplitude of input impulses, corresponding to rise-up and descending parts of input impulses respectively, delay blocks (2,4,5,7), AND elements (3,12), adder (6), multi-level amplitude selector (8), commutator (9), triggers (10,13), keys (11,14,15), and computing device (16). At first output of selector one periodical series of impulses is received with preservation of its amplitude. At second output of selector, all impulses are received with given amplitude and duration both from periodical series and those that appear in random time moments. At third output of selector all remaining impulses which may be used for further analysis are singled out. At fourth output of selector, impulses with given amplitude and duration, which appear in random time moments, are singled out.

EFFECT: expanded functional capabilities when analyzing and processing impulse series due to usage of informative impulse parameters.

2 dwg

FIELD: computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in digital automatic systems. The technical outcome allows for quantitative measurement of the degree of short term mismatch between pulses. The device contains pulse formers (1-4), AND elements (5-7), OR elements (8 and 9), delay elements (10-12), RS flip-flops (13 and 14), standard frequency generator (15), pulse counter (16), memory register (17), input (18) for the first controlled pulse train and input (19) for the second controlled pulse train. The newly introduced AND element (7), delay elements (10-12), RS flip-flop (13 and 14), generator (15), pulse counter (16) and register (17) allow for achieving the said technical outcome.

EFFECT: increased functionalities of the control device.

2 dwg

Up!