The extender rectangular pulses

 

(57) Abstract:

Usage: to increase the incoming input pulses by a given amount of expansion. The inventive dilator comprises a generator of clock pulses 1, summarizing the counter 3, the switch parallel codes 10, the comparison element parallel codes 25, reversible counter 35, the input terminal 44, the element OR NOT 40, the output terminal 53. 3 Il.

The invention relates to the field of pulse technique. The device, made in accordance with the proposed technical solution can be used to increase (expand) the duration of the received input pulses by a given amount of expansion, and the amount of expansion can be set as greater and lesser duration of the input pulse using control codes.

Extending the duration of the rectangular pulses is one of the important and common operations performed on the signals in the pulse devices. Extenders rectangular pulses is known. One of the famous options for building extender rectangular pulses is the device described in the article: L. D. Alexander, K. A. Kondratiev, V. I. SUS.2. This device will be seen as a device similar in relation to the proposed. The device is similar consists of the input of the switching transistors T1integrating RC circuit formed of the collector resistor R2cascade transistor T1and the capacitor C1and the input stage transistor T2, the base of which is connected to the collector of the transistor T1and one lead of the capacitor C1. The emitter of the output transistor T2connected to the cathode of the Zener diode (D2and one output ballast resistor (R5), the other output of which is connected to the bus power supply.

Device-similar works as follows.

In the absence of an input pulse, i.e., when the logic level zero at the input of the expander, the transistor T1locked. The transistor T2included due to the action of direct (flowing) the base current flowing through resistor R2and the base of the transistor from the power source. Capacitor C1charged to a voltage equal to the sum of the voltage on stabilization D2(the magnitude of this voltage is equal to Varticleand voltage cutoff input characteristics of the transistor TT2is equal to the sum of the voltage Varticleand the voltage between the collector and the emitter of the transistor included T2that is equal to VCAN. This amount VCAN+Varticlecorresponds to the bottom level of the output signal. The input pulse durationIunlocks the transistor T1. On timeIthe transistor T1is enabled. When turning on the transistor T1the voltage on the base of T2decreases, and the transistor T2will be locked voltage Varticlestill current at its emitter. DuringIthe capacitor C1quickly discharged through the collector circuit is turned on transistor T1. The voltage at the collector of transistor T2after locking the door becomes equal to +E, where E is the voltage of the power source. Voltage +E corresponds to the top level of the output voltage.

After the end of the pulse input transistor T1again locked, however, the transistor T2some time will be locked and its collector is maintained upper level of the output voltage. This is due to the presence of a discharged capacitor C1base circuit T2. The voltage on the capacitor C1leap will change the UB>2
from the power source +E. When the voltage on the capacitor C1and , consequently, on the base of the transistor T2will increase to the value of Varticle+lABtransistor T2is turned on and the voltage at its collector drops to a lower output level. The high voltage level on the output device (i.e., at the collector of transistor T2) will exist during the timeI+pwhere the value ofpis determined by the charging time of the capacitor C1to a voltage Varticle+lAB. The lifetime of the upper logic level of the output voltage corresponds to the duration of the output pulseo. The duration of the output pulse is extended in comparison with the duration of the input the value ofp. The device is similar, therefore, performs the function of the expander pulse duration.

The disadvantages of the device are similar:

high bottom level of the output signal. It is determined by the stabilization voltage Varticlethe Zener diode D2. High bottom level of the output signal makes a pair of such expander with other pulse cascades, such as integral elements to the adjustment value of the expansion duration p(the device is the first analogue of any of the circuits external control extension value does not contain).

With the widespread introduction of digital technology in the device formation and processing pulsed signals have been developed extenders pulses on digital items. One of the known devices used to extend the time interval and executed on the digital elements of the system is given in the book: Y. N. Erofeev. Impulse devices. M High school, 1989, S. 475, Fig.9.17, S. 479. This device will be seen as a device of the prototype in relation to the proposed. The device prototype is a reversible counter having a separate subtractive input and inverted output retransfer, as well as inputs account information in bits.

The device prototype works as follows. The inputs of the write discharge is fed code number indicating the amount of expansion (delay). The input pulse acting on the input recording resolution in bits of the reversible counter, causes the record for the specified code in the bits of the counter. After recording starts, the information read-out clock pulses supplied to the subtractive input reversevoltage transfer pulse is produced, defines the value of the derived delay (extensions). Latency (extensions) depending on the code.

The device prototype has a number of disadvantages:

the spread here is not related to the duration of the received input pulse. The input pulse of any duration after exposure to the enable input records will lead to the same, up to a period of clock pulses, the value of the expansion (delay);

the expansion pulse is displayed in the device prototype pulse, and not in potential form in the form of delay short pulse relative to the beginning count. Advanced signal in the form of a rectangular pulse in the device prototype is not produced.

The problem which is solved with the help of the proposed technical solution is to increase the input pulse priori unknown length, lying in a given range of values of duration, ensuring proportionality between the length of the received input pulse and the amount of expansion and providing the possibility of adjusting the value of this proportionality.

It is assumed that the received input prompredpriyaty, she lies in the range fromRef.min.toRef.max.. The output rectangular pulse must be synchronous input and practically (with accuracy to small delays in the switching elements) to coincide with the front. The duration of the output pulse must be set too. The value ofois determined by the equalityo=I+pwherepthe extension value. The value of the extension should be in proportion to the duration of the received pulse:p= KpIwhere TOpthe coefficient of proportionality. The value of Kpshould be regulated using the control codes that affect the device. At constant codes must be equal TOp=const. This feed control codes should provide the ability to change TO apand receive asp>1, and Kp<1 depending on the installed control codes. Aso=I+p= (1+Kp)I= KIwhere K=1+Kpthen the proposed device must ensure proportionality betweenoandIwith K>1.

The essence of the proposed technical solution is the following. The delay control n the Isla m, called "source of measurement". Setting different n and m and changing their ratio, we obtain the values of coefficient of proportionality Kpas less than one and greater than one. In the device extension, reversible counter, clock and digital elements forming the frequency divider managed by the division factor. During the duration of the input pulseIthe frequency of the clock pulses is divided by m times, and the period of the pulses obtained in the process of frequency division, is set mTowhere Tothe repetition period of the clock pulses. With these pulses, the isolating intervalIturns out the timing information of the received input pulse ("dimension" durationI). In the interval between the input pulses, the frequency of the clock pulses is divided n times, and the repetition period of the pulses resulting from the division is equal to nTo. These pulses will be charged to the timing informationIobtained in the reversible counter in the interval I. When all bits of the counter will be reset to zero (i.e., information available in the reversible counter will be described to zero), the signal retransfer, which was written duringIin the reversible counter, the value ofpwill always proportionalIand the coefficient of proportionality Kpwill depend on the ratio between the rate of entry and the rate of recording of information, i.e. on the values of m and n.

The essential features of the proposed device are:

the presence of reversible counter, clock, sum counter, switch, parallel codes, comparison element parallel codes and logical element OR NOT,

the connection of the outputs of the bits of the output code switch parallel codes with the input bits of the second number of element comparisons parallel codes, bitwise communications outputs sum counter inputs digits of the first number of element comparisons parallel codes, the connection of one input of logic element OR NOT the input terminal of the device and to the input of the direction switching accounts reversible counter and link the other input of the logical element OR NOT with inverse output transfer reversible counter.

In common with the prototype of the symptoms are:

the presence of a reversible counter,

the availability and use of specified reversible counter invert you the proposed devices from the prototype are:

introduction sum counter, switch, parallel codes, comparison element parallel codes and logical element OR NOT,

the relationship of the output clock with dynamic synchronization input summing counter, input asynchronous reset totalizer counter with the output of the comparison element parallel codes and the synchronization input of reversible counter, one input of the logical element OR NOT with the input terminal and to the input of the direction switching accounts reversible counter, link the other input of the logical element OR NOT with an inverted yield retransfer reversible counter, the relationship of input bits of the first number of switch parallel bitwise codes with terminals control code expansion, the relationship of input bits of the second number of parallel switch codes bitwise with the terminals of the control input measurement, the connection of the outputs of the bits of the output code switch parallel codes bitwise with the inputs of the second comparator parallel codes, the connection of the outputs of the bits of the bitwise sum counter inputs digits of the first number of the comparator parallel codes.

Main technical EF is eTelestia input rectangular pulse, a priori unknown, and the value of the expansion, and the coefficient of proportionality between the measured extension and duration of the received pulse can be set large and smaller units.

Additional technical effect of using the proposed technical solution is:

a) control the value of the expansion (saving can be set using control codes the values of the coefficient of proportionality when changes in the pulse duration I)

b) in ensuring the proportionality of the length of the output rectangular pulse and the length of the input,

C) to increase the manufacturability of the device through the use of a single digital devices, methods of manufacturing and installation,

d) increase the temperature stability and the degree of repeatability of the device settings through the use of unified stabilization period of the clock pulses and use of other elements of the digital type, without additional timing and control circuits.

To achieve the technical effect of the rate of receipt of pulses that fills interest is aversives counter after the end of the input pulse, regulate by means of a feed control codes (code dimension code and extension), and the duration of the output pulse is received amount sequentially existing intervals - interval Iand intervalp< / BR>
You can set the following causal link between the emerging processes in the proposed device when generating the output pulse: code dimension affects the ratio of frequency division of the clock pulses at the intervalIwhat if you change this code will change the rate of receipt of pulses, the isolating intervalI; extension code affects the ratio of frequency division of the clock after the input of the pulse at the expansion stage, because what if you change this code will change the tempo describe the information recorded in the reversible counter in the intervalI; with constant control codes to a constant factor of proportionality between the extension and duration of the pulses. If the number m is reflected by the code dimension is less than the number n, as reflected in code expansion, the coefficient of proportionality Kpless than one. Otherwise, KpB. the IC output pulse synchronous input and having a front, almost coinciding with the front of the input signal. If you come to the input pulse, the signal on the input terminal is set to a logical unit, and the signal at the output of the element OR NOT, which is the output of the proposed device, a value of logical zero. Since the proposed device has an inverted output (the duration of the output pulse corresponds to a logical zero at output terminal), the emergence of a logic zero at the output terminal corresponds to the front output.

Further presentation of material applications will be made using the following illustrations:

Fig. 1 functional diagram of the proposed extender pulses, Fig.2 - graphs of voltage changes in the characteristic points of the proposed device, Fig. 3 schematic diagram of the device used in its implementation.

The proposed device consists of:

clock pulses 1, with output 2,

sum counter 3 with dynamic synchronization input 4, input asynchronous reset 5, the output of the first discharge 6, the output of the second category 7, the output of the third order 8, the output of the fourth (poslednego the th digit of the first number 12, the entrance to the third digit of the first number 13, the input of the fourth (last) digit of the first number 14, an inverse input resolution transmission code the first number 15, input the first digit of the second number 16, the input of the second digit of the second number 17, the entrance to the third digit of the second number 18, the input of the fourth (last) digit of the second number 19, entry permit transmission of the code of the second number 20, the output of the first discharge of the output code 21, the output of the second discharge output code 22, the output of the third digit output code 23 and the fourth (last) digit of the output code 24,

comparison element parallel codes 25 having input the first digit of the first number 26, the input of the second digit of the first number 27, the entrance to the third digit of the first number 28, the input of the fourth (last) digit of the first number 29, input the first digit of the second number 30, the input of the second digit of the second number 31, the entry of the third digit of the second number 32, the input of the fourth (last) digit of the second number 33 and outlet 34,

reversible counter 35 with dynamic synchronization input 36, the input direction switching accounts 37, the input asynchronous reset 38 and the inverted output of the transfer 39,

logical element OR NOT 40, having one input 41, the other input 42 and inverse you the code of the extension 46, the third terminals of the control code of the extension 47, the fourth terminal control code extensions 48,

the first terminals of the control code measure 49, the second terminals of the control code measure 50, the third terminals of the control dimension code 51, the fourth terminal of the control dimension code 52,

output terminal 53.

Output 2 clock 1 in the proposed device is connected with dynamic synchronization input 4 sum counter 3, the input asynchronous reset 5 which is connected to the output 34 of the comparison element parallel codes 25 and dynamic synchronization input 36 reversible counter 35. The output 6 of the first rank sum counter 3 is connected to the input 26 of the first digit of the first number of element comparisons parallel codes 25. The output 7 of the second discharge sum counter 3 is connected to the input 27 of the second digit of the first number of element comparisons parallel codes 25. The output 8 of the third rank sum counter 3 is connected to the input 28 of the third digit of the first number of element comparisons parallel codes 25. The output of the fourth (last) digit 9 sum counter 3 is connected to the input 29 of the fourth (last) digit of the first number of element comparisons p terminal 45 of the control code of the extension. The input 12 of the second digit of the first number of parallel switch 10 codes connected with the second terminal 46 of the control code of the extension. The input 13 of the third digit of the first number of parallel switch 10 codes connected with the third terminal 47 of the control code of the extension. The entrance 14 of the fourth (last) digit of the first number of parallel switch 10 codes connected with the fourth terminal 48 of the control code of the extension. Inverted enable input of the transmission code, the first number of switch 15 parallel codes 10 is connected to the enable input of the transmission code, the second number 20 of the switch 10 with the input of the direction switching accounts 37 reversible counter 35, with one entrance 41 of the logical element OR NOT, 40 and to the input terminal 44. The input 16 of the first digit of the second number of parallel switch 10 codes connected with the first terminal 49 of the control code measurements. The entrance 17 of the second digit of the second number of parallel switch 10 codes connected with the second terminal 50 of the control code measurements. The input 18 of the third digit of the second number of parallel switch 10 codes connected with the third terminal 51 of the control code measurements. The entrance 19 of the fourth (last) digit of the second number of parallel switch 10 codes connected with Chinuch codes 10 is connected to the input 30 of the first digit of the second number of devices comparison of parallel codes 25. The output 22 of the second discharge output code switch parallel codes 10 is connected to the input 31 of the second digit of the second number of element comparisons parallel codes 25. The output 23 of the third digit output code switch parallel codes 10 is connected to the input 32 of the third digit of the second number of element comparisons parallel codes 25. The output 24 of the fourth (last) digit of the output code switch parallel codes 10 is connected to the input 33 of the fourth (last) digit of the second number of element comparisons parallel codes 25. Input asynchronous reset 38 reversible counter 35 is connected to the inverse output 43 of the logical element OR NOT 40 and output terminal 53. Inverted output of the transfer 39 reversible counter 35 is connected to another input of the logic element 42 OR 40.

The proposed device operates as follows. Output 2 clock 1 is a sequence of clock pulses with a period of To. She goes on dynamic synchronization input 4 sum counter 3. The level of the input signal at input terminal 44 is equal to a logical zero. This level is transmitted to the inverted enable input of transmission of the first number of switch 15 PA permit transmission of the first number 15 this logic level zero is permissive. For the first 45 and second 46, third 47 and 48 fourth terminal control code extension filed code of the number n, which determines the division ratio of the clock frequency (and equivalently, increasing the period of the incoming pulses) at the stage of expansion. The same code will be installed at the entrance of the first digit of the first number 11, the input of the second digit of the first number 12, the entrance to the third digit of the first number 13 and the input of the fourth digit of the first number of switch 14 parallel codes 10. Thus, the first number for this switch is the number n. The first terminal 49, the second terminal 50, the third terminal 51 and the fourth terminal 52 dimension code submitted code number m, which determines the division ratio of the frequency of clock pulses at the stage of filling the length of the input pulse, i.e., on the measurement stage of this a priori unknown duration. The same parallel control code set at the input of the first digit of the second number 16, the input of the second digit of the second number 17, the entrance to the third digit of the second number 19 and the input of the fourth digit of the second number 19 switch parallel codes 10. Thus, for a given switch, the second number is the number m.

A logic level zero input signal, as selected codes 10, provide resolution transmission values of the digits in the number n at the output of the first discharge of the output code 21, the output of the second discharge output code 22, the output of the third digit output code 23 and the output of the fourth class of the output code 24 switch parallel codes 10. Thus, when a logic zero on the input terminal 44, the output number for the switch 10 and the input number of inputs 30-33 digits of the second number of element comparisons parallel code 25 will be the number of n. In comparison, parallel codes 25 compares the code of the number n and the current code outputs of digits 6-9 sum counter 3. The value of the number recorded at the output of summing counter 3, incremented upon receipt of clock pulses of clock 1 on its dynamic input 4. When codes digits, with a summing counter 3, are compared with the codes of the digits of n, the set of inputs 30-33 digits of the second number of devices comparison of parallel codes 25, the specified device is triggered and its output 34 produces a positive difference. This difference, when the input asynchronous reset 5 sum counter 3 causes it to reset. After the reset of the counter retroactive comparison of parallel codes 25 again vanishes. The duration of the output pulse at the output 34 of the comparator parallel codes is determined, essentially, by the time zero sum counter 3. Begins a new cycle of this counter, which ends with the achievement recorded therein to the values of n and providing a comparison of the first and second numbers in the device comparison of parallel codes 25. Thus, summarizing the counter and the comparator parallel codes form a controlled frequency divider, in which the division ratio is determined by the value of the number n. The output pulse from the output 34 of the comparator codes 25 produced at the time of comparing the codes of the first and second numbers current at its input, is also on dynamic synchronization input 36 reversible counter 35. The frequency of the impulses acting on dynamic synchronization input 36 is, essentially, a clock frequency for this reversible counter. However, the reversible counter these pulses are not counted for the following reason: its input asynchronous reset 34 is connected to the inverse output 43 of the logical element OR NOT 40, on one and the other inputs of this element is a logic level zero, and the output 43 of logic is 8 reversible counter 35, holds the reversible counter in the state of logical zeros on the output bits. At the output terminal 53 is also a signal of logical units. In this state, the device can be as long as you like before the arrival of the input signal.

The input is a rectangular pulse of positive polarity with durationIis supplied to the input terminal 44. On timeIthe signal at the input 20 of resolution transmission code, the second number switch code 10 assumes the value of logical units, and outputs 21-24 bits of the output code of the switch will already passed the number m. The division ratio of the frequency of the controlled divider formed by summing the counter 3 and the comparator parallel codes 25, will change and the output 34 of the comparator parallel code 25 will be produced by short pulses with a period T1=mTo. These pulses will arrive on dynamic synchronization input 36 reversible counter 35.

In addition, the input pulse durationIwill come to the entrance direction switching accounts 37 reversible counter 35 and will switch the counter mode summation. Further, the input pulse is received on one input 41 layover logical zero. If: a) forming a front output (negative) momentum b) voltages will be removed from input asynchronous reset 38 reversible counter 35 and the counter gets the opportunity to work in the mode of counting pulses on dynamic synchronization input 36, namely in the summation mode.

Reversible counter 35 at the timeIcounts the number N of pulses with a period T1=mTocompleting the specified durationI..

After the end of the input pulse, the voltage at input terminal 44 will be set to logical zero. When switching the logic level of the signal at input terminal 44 (logical zero) will be the next switch in the proposed device: through the switch parallel codes 10, as in the initial state, will again be transmitted to the number n, and the repetition period of short pulses at the output 34 of the comparator parallel codes again takes the value T2=nTo,

b) reversible counter 35 at the input 37 of the direction switching accounts will switch from mode summation in the subtraction mode.

Because digit reversible counter has recorded the number, the signal on inverse the s input pulse, supported logical zero.

Reversible counter begins to work in the subtraction mode, and recorded therein the number gradually decreases due to the action of the input pulses with a period of T2= nToon dynamic synchronization input 36. When the number, before, duringIrecorded in the reversible counter 35 will be charged to zero, at its inverted output of the transfer 39 produces a signal of logical zero. Both inputs are logical element OR NOT 40 will be logic zero signal, and the output 43 of the logical element OR NOT 40, and hence to the output terminal of the signal will be set to logical units. The formation of the output pulse has ended.

The duration of the output pulse is determined by the ratioo=I+p, i.e., the output pulse is extended by the amount of expansionp. If the number of pulses with a period of T1=mTofilling the input pulse durationIwas equal to N, the number of pulses with a period of T2=nTo, written off information in the reversible counter 35, also (up to units) is equal to N. Thenp= Nn, where or . Denote by Kpthe coefficient of proportionality betweenpp=2), and smaller units (for example, Kp=0,5). For this you need to install the corresponding values of the integers m and n.

If the number n terminal 45-48 (terminals code expansion) is greater than the number m terminals 49-52 (terminals dimension code), thenp>1. If the number n terminal 45-48 (terminals code extension) is less than the number m terminals 49-52 (terminals dimension code), thenp<1. When m=n the extensionpapproximately equal durationI.

It is essential that the proportionality between pandIIis provided with a priori unknown value ofIin a certain range of values of this duration, which is greater, the greater the bit depth of the digital elements included in the proposed device.

The use of two control codes (code expansion, which is the number n, and the dimension code, which specifies the number (m) allows you to set different values TOp.

The proposed device has been tested experimentally. When the experiment was applied clock integrated circuit 564 LE; summarizing the counter was organized on the basis of the integral counter IE, IE, as a comparison element parallel codes chip IP, as the switch parallel codes chip IS, for the organization of the inverse log-resolution transmission code the first number of the input 9 of this integrated circuit was connected to the inverter output, the input of which was used as the inverse of the enable input of transmission gate OR was NOT performed on the integrated circuit LE.

The period of clock pulses Towhen indicated on Fig.3 the component values timing chain clock was 6 ISS. The range of durations of the input pulses was set within the following limits:Ref.min= 25 µs,,Ref.max= 45 ISS.. Asking code dimension corresponding to the number m=7, and the extension code corresponding to the number n=14, when the experiment has been estimated (up to a period of the frequency measurement) increasing the pulse duration with the following parameters: Kp=2, K=3. These valuespand maintained automatically for all values ofIlying in the rangeRef.min+Ref.max..

The experiment thus confirmed, how is the device on the digital elements, and reached the tel rectangular pulses, containing a reversible pulse counter and clock generator pulses, characterized in that it introduced an element of comparison of parallel codes summarizing the pulse counter, the switch parallel codes and the item OR NOT, the output of which is connected with the output terminal and to the input asynchronous reset reversible pulse counter, the first input to the input terminal, the input direction switching accounts reversible pulse counter, an inverted enable input of the transmission code of the first number of parallel switch codes and entry permit transmission of the code of the second number of the switch parallel codes, the second input with an inverted yield retransfer reversible pulse counter, dynamic synchronization input connected to the output of the comparison element parallel codes and input asynchronous reset totalizer count pulse, the dynamic synchronization input of which is connected to the generator output clock pulses, the outputs of the bits with bitwise inputs digits of the first number of element comparisons parallel codes, the input bits of the second number of which is connected with bitwise output bits of the output code switch parallel codes, inputs rozradowani, the input bits of the second number of parallel switch codes bitwise with terminals for signalling bits of the control code measurements.

 

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