Digital correlator

 

(57) Abstract:

The invention relates to the field of radar and is intended to implement the operations of convolution of two signals. The purpose of the invention is to improve performance. The correlator includes an integrator, a synchronizer, an address counter, a group of delay lines, groups of switches, demultiplexes, the multiplier products, adder, two frequency divider and channel count. 7 Il.

The invention relates to the field of radar and intended for the operation of convolution of two signals received and reference. The specified operation is the basis for the correlation method technique, which is widely used in radar systems for measuring coordinates of the target.

The known device for calculating the correlation integral and convolution of functions containing the digital delay line, a multiplier and an integrator, the input connected to the output of the multiplier.

One such device is a cyclic digital correlator described in U.S. patent N 3717756 from 20.02.73, MKI 5 G 06 F 15/34, NCI 235-181. The specified device contains two cyclic memory, multiplier and memory. From the analyzed input signal selects Diskr the resolutions of the input signal are calculated in the formation of the compositions of the samples and the summation of these works with the corresponding correlation coefficients, which were recorded earlier in another memory. This way, the latest data when sampling discrete information from the input signal.

Another similar device is monolithic scheme is a discrete convolution described in U.S. patent N 4489393 from 18.12.84, MKI 5 G 06 F 7/38, NCI 364-728. This circuit contains N memory circuits for storing the N corresponding values of the first function, N multipliers having one input connected to the corresponding memory circuit, and a second input, connected to each other, to obtain N consecutive values of the second function, and generating output signals indicating the achievement of the respective values of the first function and the successive values of the second function, N shift registers, N adders having first inputs connected to the outputs of the respective multipliers, the outputs of the respective shift registers, and a second input for receiving the accumulated data from the adjacent shift registers. Adders and shift registers are combined in a circuit in which each adder combines the result of the multiplier with the accumulated amount received from the next adder in the chain, and the last adder produces posredovanje functions.

Known devices have low speed, because the accumulation of reference correlation integral is carried out consistently.

The closest about the technical nature and the greatest match characteristics selected as a prototype, is a digital correlator described in U.S. patent N 4025772 from 24.05.77 MKI 5 G 01 S 9/02, NCI 235-166 shown in Fig.8 and containing the first digital delay line, the first input of which receives the received signal, the second digital delay line, the first input of which receives the reference signal, the multiplier, the inputs of which are connected to the outputs of the first and second delay lines, the integrator, the input connected to the output of the multiplier, the synchronizer, the address counter, an input connected to the first input of the synchronizer, second and third outputs of the synchronizer connected, respectively, with the second inputs of the first and second digital delay lines, the first and second outputs of the address counter is connected, respectively to the address inputs of the first and second digital delay lines, and the output signal is taken from the output of the integrator.

The disadvantage of the prototype is low performance, defined according to the following who s already contained in the digital delay line. In addition, it is necessary to divide in time steps of data accumulation and processing. In that case, if the input signal is supplied continuously, it will lead to loss of information.

The purpose of the invention improve the performance of the digital correlator.

This goal is achieved by the fact that in the digital correlator containing an integrator, a synchronizer, an address counter, an input connected to the output of the synchronizer, inputs of the first, second group of digital delay lines, which represents a set of digital delay lines, the group of multiplier products, the third group of digital delay lines, the fourth group of digital delay lines, the first demultiplexer, the input of which is filed with the received signal, and outputs connected to first inputs of digital delay lines of the first and third groups, the second demultiplexer, the input of which is filed with the reference signal, and its outputs connected to first inputs of digital delay lines of the second and fourth groups, the first group of switches, the first inputs of which are connected to the outputs of the digital delay lines of the first group, the second inputs to the outputs of the digital delay lines of the third group, and outputs the first input of the multiplier products, the second groody to the outputs of the digital delay lines of the fourth group, and outputs with the second inputs of the multiplier products, adder, m-inputs of which are connected to the outputs of multiplier products, and the output to the input of the integrator, the first frequency divider, the input of which is connected to the first output of the synchronizer, channel count, the input connected to the output of the first frequency divider, and the output - control inputs of the first and second demultiplexes the second frequency divider, the input connected to the output of the first frequency divider, and the output - control inputs of the switches of the first and second groups, the second output of the synchronizer is connected with the second inputs of the digital delay lines of the first and third groups, and the third output of the synchronizer is connected with the second inputs of the digital delay lines of the second and fourth groups, the first output address counter connected to the address inputs of the delay lines of the first and third groups, and the second address input of digital delay lines of the second and fourth groups, the output of the integrator is the output device.

Comparative analysis of the prototype shows that the proposed device has new blocks: first, second, third and fourth group of digital delay lines, the group of multiplier products, the first and second de is. is that the proposed solution meets the criterion of "novelty".

When comparing the claimed device with other technical solutions are not found solutions with similar features. Known devices use the accumulation of works of samples received and reference signals sequentially in time, which limits the performance of the digital correlator. In addition, there is no possibility to perform simultaneous processing and accumulation of signal in the digital delay lines. The introduction of additional groups of digital delay lines and multiplier products allows parallel, i.e., simultaneous processing of some set of samples of the input signal. The proposed device allows to reduce the analysis time required for evaluation of the correlation function.

This allows to conclude that the technical solutions according to the criterion of "significant differences".

In Fig. 1 shows a structural diagram of the device of Fig.2,3,4,5,6,7 implementation of its individual units.

The digital correlator of Fig.1 contains a first group of digital delay lines 11. 1mthe second group of digital lines zaderzhala is connected to the first output of the synchronizer 5, the third group of digital delay lines 71, 7m, the fourth group of digital delay lines 81,8mthe first demultiplexer 9, the input of which is filed with the received signal, and outputs connected to first inputs of digital delay lines of the first and third groups 11,1m, 71,7mthe second demultiplexer 10, the input of which is filed with the reference signal, and outputs connected to first inputs of digital delay lines of the second and fourth groups 21,2m, 81,8mthe first group of switches 111,11mthe first inputs of which are connected to the outputs of the digital delay lines of the first group 11,1msecond inputs with the output of digital delay lines of the third group 71,7mand outputs the first input of the multiplier products 31,3mthe second group of switches 121, 12mthe first inputs of which are connected to the outputs of the digital delay lines of the second group 21,2msecond inputs to the outputs of the digital delay lines of the fourth group 81,8mand outputs with the second inputs of the multiplier products 31,3mthe adder 13, m-inputs of which are connected to the outputs of multiplier products 31,3mand the output to the input of the integrator 4, kotorogo connected to the output of the first frequency divider 14, and the output from the control inputs of the 1st, 2nd demultiplexes 9 and 10, the second frequency divider 16, the input connected to the output of the first frequency divider 14, and the output from the control inputs of the switches of the first and second groups 111,11m, 121,12mthe second output of the synchronizer 5 is connected with the second inputs of the digital delay lines of the first and third groups 11,1m, 71,7mand the third output synchronizer 5 is connected with the second inputs of the digital delay lines of the second and fourth groups 21,2m, 81, 8mthe first output of the address counter 6 is connected to the address inputs of the digital delay lines of the first and third groups 11,1m, 71,7mand second address inputs digital delay lines of the second and fourth groups 21,2m, 81,8mthe output of integrator 4 is an output device.

The proposed device operates as follows.

The received input signal is fed to the input of the first demultiplexer 9-Si. The reference signal is input to the second demultiplexer 10-Ui. In odd periods of signal accumulation of data is performed in the digital delay lines of the first and third groups 11,1mthe eat period signal from the digital delay lines of the second and fourth groups 21,2m, 81,8m. This organization of work of the device with the buffer of the previous period allows continuous signal processing. In even periods of signal reading and processing of data is carried out with digital delay lines of the first and third groups 11,1mand 71,7mand the accumulation of digital delay lines of the second and fourth groups 21,2mand 81,8m. The corresponding switching of the digital outputs of the delay lines is carried out with two groups of switches 111,11mand 121,12m. The signals from the outputs of the switches are received, respectively, on first and second inputs of the m multiplier products 31,3m. The adder 13 averages the results of the works and the resulting counts are accumulated in the integrator 4.

The selection of a particular digital delay line when writing new information by using demultiplexes 9 and 10, managed code, generated by the special channel counter 15.

The address of a particular memory cell device comprising a digital delay line is formed by using the address counter 6. Synchronizer 5 provides synchronous operation of all digital device is tel frequency 16 (1:m) generates a switching signal switches 111,11mand 121,12mduring the transition to the next period of the signal.

Let the number of samples per period of the signal is N, the number of multiplier products equal to m. In this case, the number of cells storage device, each digital delay line will be n=N/m.

Thus, these lines in m times shorter than a digital delay line in the prototype.

The distribution of samples of the input signal Si digital delay lines is carried out using a demultiplexer 9 as follows

S1 Sm+1.S(n-1)m+1 __ line 11(71)

S2 Sm+2.S(n-1)m+2 --L line 12(72)

< / BR>
Sm S2m.SN --L line 1m(7m).

Similarly, distributed timing reference signal Ui, i 1,N

U1, Um+1.U(n-1)m+1 --L line 21(81)

U2 Um+2.U(n-1)m+2 --L line 22(82)

< / BR>
Um U2m.UN --L line 2 m (8m).

The newly introduced, compared with the prototype, digital devices: demultiplexes 9,10, counter, switches, frequency dividers, the adder are standard digital devices and examples of their implementation are widely presented in the literature (see for example (3) C. 556-596, Fig. 8.18-8.46).

Consider the possible options for implementation of certain (non-standard) units of the proposed mouth of tiplexer intended for distribution counts of the input (reference) signal over m channels. The General structure of the demultiplexer for the case m=16 when the input bit code is equal to 8 is shown in Fig.2.

The number of sections DMS corresponds to the input bit words, one section commutes one of his discharge in accordance with the address code supplied from the channel counter. The first half of the address corresponds to the first group CLS Ii, i=1,m, the second the second group CLS 2i, i=1,m.

A possible implementation of one section of the demultiplexer shown in Fig. 3.

On the information input W1 chips IJ receives one bit of the input word Si. Four low-order addresses are fed to the control inputs X3, X4, X5, X6 of these chips, and high-order address input Wo "choice crystal", and one of the circuits through the inverter. As a result, one half of the addresses has one chip, providing switching between CLS 1i, i= 1,m of the first group, the other the second chip, providing switching between CLS 2i, i=1,m of the second group.

The address counter 6 (Fig.1).

A possible implementation of the address counter shown in Fig.4.

The address code for CLS 1i, CLS 2i first and second groups are formed using a conventional counter So that doing so is CLASS="ptx2">

SC performed on the chip IE, as shown in Fig.7.

When calculating cross correlation functions between the input and reference signals must consistently provide the various offsets of these signals relative to each other. This is achieved by the offset addresses for CLS 3i, CLS 4i of the third and fourth groups in the reading mode information. In write mode for all CLS use the same address output SC that is provided by switch COM-controlled signal 4m/3n from the synchronizer. COM is made on the chip IP, as shown in Fig.6.

Offset address is removed from the output of the adder, the inputs of which are served source address and the offset obtained by using a frequency divider 1:N and the second counter SC.

Thus, after receiving one of the reference correlation function for an N point signal, the offset is incremented and is calculated following the reference correlation function.

Synchronizer 5 (Fig.1).

Based synchronizer (Fig.5) is the master oscillator operating in the oscillatory mode, which generates a sequence of clock pulses directly supplied to CLS 1,si through the inverter.

In addition, clock pulses are fed to the inputs of the frequency dividers, the output of which is signal 4m/3n, managing mode CLS 1(3). To control the mode of operation CLS 2(4) the signal is removed from the inverter. This ensures the following: while CLS 1(3) performs the accumulation of the signal, i.e., operates in the recording mode, the processed signal output from CLS 2(4), which operates in the reading mode.

Improve performance in m times in comparison with the prototype is achieved by parallel execution of the operations of multiplication counts the received and reference signals. In addition, the use of additional digital delay lines 71,7mand 81,8mallows simultaneous processing and accumulation of data, which ultimately increases the performance of the digital correlator. Known devices use the accumulation of works of samples received and reference signals sequentially in time, which limits the performance of the digital correlator. In these devices there is no possibility to perform simultaneous processing and accumulation of signal in the digital delay lines. The introduction of additional groups of digital lines sprosty samples of the input signal. Therefore, the proposed device allows to reduce the analysis time required for evaluation of the correlation function.

On the date of filing the company made a sample of the claimed device, currently in an integrated setting and testing.

The use of the proposed technical solution in the processing system of complex radar signals are planned in 1994 in order 9071. 2

A digital correlator that contains the integrator, the synchronizer and the address counter, an input connected to the first output of the synchronizer, characterized in that it introduced the first, second, third and fourth groups of digital delay lines, the first and second groups of switches, the first and second demultiplexes, the multiplier products, the adder, the first and second frequency dividers and channel counter, and informational inputs of the first and second demuxers are respectively the input job information and reference signals of the correlator outputs of the first demultiplexer connected to information inputs of the digital delay lines of the first and third groups, outputs, which are connected respectively to the information inputs of the switchboard shall support the second and fourth groups, the outputs are connected respectively to the information inputs of the switches of the second group, the outputs of the switches of the first and second groups are connected to first and second inputs of the respective multiplier products whose outputs are connected to inputs of the adder, the output of which is connected to the input of the integrator, the output of which is the output of the correlator, the first output of the synchronizer through the first frequency divider is connected to the input channel counter and through a second frequency divider to control inputs of the switches of the first and second groups, the outputs of the address counter connected to the address inputs of the digital delay lines for all groups, the control inputs of which are connected with the second output of the synchronizer, the output of the channel counter is connected to the control inputs of the first and second demultiplexes.

 

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