The device for the study of amplitude-frequency characteristics of a quadrupole

 

(57) Abstract:

Usage: the invention relates to radio engineering. The inventive device has 1 a voltage controlled oscillator (1), 1 meter frequency (2), 1 adder (3), 3 digital-to-analog converters (4, 5, 6), 5 registers(7, 8, 9, 15, 28), 1 the address decoder (10), 1 study quadrupole (12), the amplitude detector (13), 1 analog-to-digital Converter (14), 1 signal scan indicator and signal (15), 1 indicator (16), 2 buffer stage (17, 18), 1 driver labels (19), 1 synchronizer (20), 2 RAM data display (21, 31), 3 multiplexer (22, 30, 32), 3 meter (23, 24, 26), 1 RAM (25), 1 unit pair (27), 1 block read (29), 1 counter trigger (33).1 Il.

The invention relates to electrical engineering and can be used for observations and measurements of the amplitude-frequency characteristics (AFC) of the radio with digital readout of measurement results and playback frequency response on the display screen of the monitor type with the raster method of forming the image.

Known devices for the study of amplitude-frequency characteristics X1-53 and X1-48 (technical description and operating instructions 1.400.263 and 2.048.061 respectively), katoozian frequency channels, i.e. limited functionality.

The closest in technical essence to the claimed is selected as the prototype instrument for the study of amplitude-frequency characteristics X1-55 (technical description and operating instructions 1.400.293) (Fig. 3-8) and containing a voltage controlled oscillator (VCO), the input set of the frequency band which is connected to the output of the first register, the first input which is the input-output device and connected to the first input of the measuring frequency, the first inputs of the second, third and fourth registers and the input of the address decoder, the first to fourth outputs of which are connected respectively to the second inputs of the first to fourth registers, the outputs of the second and third registers respectively connected to the input of the first digital to analogue Converter (DAC) and the first input of the second DAC, a second input connected to the output of the third DAC, and the output from the second input of the adder, the first input and the output of which is connected respectively with the output of the first DAC and control input of the oscillator, voltage-controlled, the output of which is connected to the second input of the measuring frequency, the second input of the amplitude detector and one is funaho detector, the output of which is connected to the first input of the analog-to-digital Converter (ADC), the second input is connected to the first output of the synchronizer, the second output of which is connected to the first input of the first random access memory (RAM) data display, the second input is connected to the output of the first multiplexer, the first and second inputs which are connected respectively to the first output of the first counter and the second counter, a first input connected to the third output of the synchronizer and the first input of the first counter, the second input is connected to the fourth output of the synchronizer, fifth output of which is connected to the input of the shaper labels, input-output of the first buffer stage, the first input-output of which is connected to the first input-output of the second buffer stage connected to the first input of the first register, and the sixth output of the synchronizer is connected to the first input signal of the sweep of the indicator signal, the output of which is connected to the input of the indicator.

The disadvantage of the prototype is that it offers limited functionality, namely:

a) you cannot play on the screen of the indicator amplitude t to organize the study of the frequency response with a speed commensurate with the speed of the raster scan display, what is necessary to exclude the effect of "rubber screwdriver when adjusting the investigational device, i.e., reducing the response time of the display on the external perturbation of the investigational device;

C) does not provide a wide range of generated frequencies with high resolution;

g) does not allow the investigation and adjustment of two electronically controlled in an automated mode.

Resolution the number of generated frequencies in the range.

Frequency range maximum frequency band overlapped GONG when changing the control voltage from Uminto Umax.

Frequency sub-band of an arbitrary frequency band within the range.

The purpose of the invention to enhance the functionality.

This objective is achieved in that the device for the study of amplitude-frequency characteristics of two-port network containing a voltage controlled oscillator, the input set of the frequency band which is connected to the output of the first register, the first input which is the input-output device and connected to the first input of the measuring frequency, the first input veroyatnostei to the second inputs of the first to fourth registers, the outputs of the second and third registers respectively connected to the input of the first digital to analogue Converter (DAC) and the first input of the second DAC, a second input connected to the output of the third DAC, and the output from the second input of the adder, the first input and the output of which is connected respectively with the output of the first DAC and control input of the oscillator, voltage-controlled, the output of which is connected to the second input of the measuring frequency, the second input of the amplitude detector and the first input connection of the investigated two-port network whose output is the first output of the amplitude detector, the output of which is connected to the first input of the analog-to-digital Converter (ADC), the second input is connected to the first output of the synchronizer, the second output of which is connected to the first input of the first random access memory (RAM) data display, the second input is connected to the output of the first multiplexer, the first and second inputs which are connected respectively to the first output of the first counter and the second counter, a first input connected to the third output of the synchronizer and the first input of the first counter, the second input is connected to Chetvertaya to the clock input and the second input is the output of the first buffer stage, the first input-output of which is connected to the first input-output of the second buffer stage connected to the first input of the first register, and the sixth output of the synchronizer is connected to the first input signal of the sweep of the indicator signal, the output of which is connected to the input of the indicator, introduced random access memory device, the third counter, block read, block pair, the second multiplexer, and the audit trigger, the second RAM data display, the third multiplexer and the fifth register, and the second input of the third counter connected to the sixth output of the decoder address, the fifth output of which is connected to the second input of RAM, the first input is combined with the first input of the third counter, and the output and the third input of RAM respectively connected to the input of the third d / a Converter and the output of the third counter, the third input of which is connected to the output of the fourth register, the input-output block read its output, first, second and third inputs respectively connected to the second input-output of the second buffer stage, the second input of the second counter, the seventh output of the synchronizer, the output of driver labels and the output of the second multiplexer, the first, the second and third inputs of which are connected within the od of which is connected to the third input of the first multiplexer and the third input of the first RAM data display, the fourth input is connected to the fourth input of the second RAM data display and output of the fifth register, the first input of which is connected to the ADC output and the second input is connected to the ninth output of the synchronizer, the eighth output of which is connected to the fourth input of the third counter and the second output of the synchronizer is connected to the first input of the second RAM data display, the third and the second input of which is connected respectively to the output of the third multiplexer and to the first output of the counting trigger, the input of which is connected to the second output of the first counter, the first output of which is connected to the first input of the third multiplexer, the second and third inputs of which are connected respectively with the output of the second counter and the first output of the counting trigger, and the output interface block is the second input to connect investigated quadrupole, the first input interface block is combined with the second input signal of the sweep of the indicator signal, the first input of the RAM and the first input of the first register, the second and third inputs of the interface block connected respectively to the seventh output of the address decoder and the output of the third counter.

The drawing shows BL is to study the amplitude-frequency characteristics of two-port network comprises a generator 1 voltage controlled (VCO), the 2 meter frequency, the adder 3, the first 4, second 5 and third 6 DAC, the first 7, second 8 and third 9 registers, the decoder 10 addresses (DSA), the fourth register 11, the analyzed quadrupole 12, the amplitude detector 13, the ADC 14, block 15 signal scan indicator and signal indicator 16, the first 17 and second 18 buffer cascades, shaper 19 tags synchronizer 20, the first RAM 21 data display, the first multiplexer 22, the first 23 and second 24 counters, RAM 25, the third counter 26, block 27 mates, the fifth register 28, block 29 is read, the second multiplexer 30, the second RAM 31 data display, the third multiplexer 32, the counting trigger 33.

The output of the VCO 1 is connected to the second input of the 2 meter frequency. At the first input of the VCO 1 control voltage comes from the output of the adder 3, the first and the second input of which receives the voltage from the outputs of the first 4 and second 5 DAC. On the second (multiplying) the input of the second DAC 5 receives the voltage output from the third DAC 6. The output of the first register 7 is connected to the second input of the VCO 1. To input the first 4 and second 5 DAC receives information from the output of the second 8 and third 9 registers. The first to fourth outputs of DSA 10 is connected to a second (gate) inputs of the first to fourth registers 7, 8, 9, 11, maricela 2 frequency. The first input of the investigated two-port network 12 connected to the output of the VCO 1 and the second input of the 2 meter frequency. The output of the investigated two-port network 12 connected to the first input of the amplitude detector 13, the second input is connected to the output of the VCO 1. The output of the amplitude detector 13 is connected to the first input of the ADC 14. The input unit 15 of the signal scan indicator and signal connected to the input-output device, and the output connected to the input of the indicator 16. First the inputs and outputs of the first 17 and second 18 of buffer stages connected to the input-output device. The second input is the output of the first buffer cascade 17 is connected to the input-output driver 19 of the labels and the input of the synchronizer 20. The second input of the first RAM 21 data display is connected to the output of the first multiplexer 22, the first and second inputs which are connected respectively to the output of the first 23 and second 24 counter. The first and sixth outputs of the synchronizer 20 is connected respectively with the second ADC input 14, the first input of the first RAM 21 data display, the first input of the first 23 and second 24 counter, a second input of the first counter 23, the input of the shaper 19 labels and the input processing unit 15 of the signal scan indicator and signal. The output of the RAM 25 connection(gate) input of RAM 25 is connected to the fifth output DSA 10, and the third (address) input of RAM 25 is connected to the output of the third counter 26. The first entry (PE) of the third counter 26 is connected to the input-output device, the second (mode) input to output of the fourth register 11, the third input (strobe records) third counter 26 is connected to the sixth output DSA 10, the fourth (counting) input of the third counter 26 is connected to the eighth output of the synchronizer. The seventh output DSA 10 is connected to the second input unit 27 mates. The output of the third counter 26 is connected with the third input unit 27 pair, the first input connected to the input-output device, and the output connected to the second input of the investigated two-port network 12. The first input (data) of the fifth register 28 is connected to the output of the ADC 14, and the second (gate) input is connected to the ninth output of the synchronizer 20. The output of the fifth register 28 is connected to the fourth inputs of the first 21 and 31 of the second RAM data display, the first inputs of which are connected. The input-output unit 29 reads the information connected to a second input the output of the second buffer cascade 18. The second input unit 29 read is connected to the output of the shaper 19 labels, and the first input of the seventh output of the synchronizer 20. The output unit 29 read is connected to the WTO is connected respectively to the output of the first 21 and 31 of the second RAM data display. The second input of the second RAM 31 data display is connected to the third input of the second multiplexer 30 and the third input of the multiplexer 32, the output of which is connected to the third input of the second RAM 31 data display. The first and second inputs of the multiplexer 32 is connected respectively to the first output of the first counter 23 and the output of the second counter 24. The counting input of the trigger 33 is connected to the second output of the first counter 23. The first output of the counting trigger 33 is connected to the third input of the multiplexer 32, and the second output of the counting trigger 33 is connected to the third input of the multiplexer 22 and the third input of the RAM 21 data display.

GUN is designed to generate sinusoidal oscillations. Controlled by the voltage from the output of the adder 3. Can be performed by any well-known scheme (see technical description of the instrument X1-55 1.400.293).

The 2 meter frequency is designed to measure the frequency of the VCO 1. May be made under the scheme (see technical description of the instrument X1-55 1.400.293).

The adder 3 is designed for summing the analog signals from the outputs of the first-third DAC 4-6 and provide a control voltage for the VCO 1 (device X1-55 1.400.293).

The first DAC 4 is designed for steemy CPA.

The second DAC 5 is designed for installation stresses, the respective end frequency sub-band scanning. Can be performed on the basis of chip CPU.

The third DAC 6 is designed for adjustment of the voltages corresponding to the frequencies within the sub-band scanning. Can be performed on the basis of chip CPU.

The first register 7 register of sub-bands is used to set the information of the switching sub-bands. Can be performed on the basis of chip KTM.

The second 8 and third 9 registers are used for installation of digital information corresponding to the start and end frequency sub-band. Can be performed on the basis of chip KTM.

DSA 10 distributes the impulse to write to the selected address. Can be performed on the basis of chip CIJ.

The fourth register 11 register of the modes of operation of the first counter 26 (direct account, download, reverse scored). Can be performed on the basis of chip KTM.

The study quadrupole 12 analyzed quadrupole, for example, the selector of the TV channels.

The amplitude detector 13 is designed to highlight information about the amplitude-frequency harano United broadband mixer, band-pass filter, an intermediate frequency amplifier and synchronous detector. In the simplified variant represents a detector head.

ADC 14 is designed to convert analog input to digital. Can be performed on the basis of chip CPU.

Unit 15 of the signal scan indicator and the video is designed to generate signals scan indicator and signal. Can be performed on the basis of chip CVG.

The indicator 16 is intended for visualization of research results. Can be made on the basis of a television monitor.

Buffer cascades 17, 18 are designed to ensure coordination with external bus input / output. Can be performed by various well-known logical control circuits, providing the necessary algorithm to the bus.

Shaper 19 tags is designed to create the necessary supporting information on the screen, such as a grid of valid values of the controlled parameter. Can be made on the basis of chip RAM CMR and appropriate management schemes.

The synchronizer 20 is designed for time synchronization of the work in the data display are designed for recording, read and store initiated information. Can be made on the basis chip CRU.

The first 22 and 32 third multiplexers are designed to alternately supply the address inputs of the first 21 and the second RAM 31 or the first counter 23, or from the second counter 24. Can be made on the basis of chips CCP.

The first 23 and second 24 counters counters addresses. Can be made on the basis of chip CIE.

RAM 25 random access memory intended for storing information corresponding to the change of voltage at the output of the third DAC 6, which ultimately results in the VCO 1 to change the frequency within the prescribed frequency range. Can be made on the basis of chips CRU.

The third counter 26, the counter address of the first RAM 25. Can be performed on the basis of chip CIE.

Block 27 interfacing analyzed multipole 12 control voltage required for its operation research. Can be made on the basis of chips CRU and CPA.

The fifth register 28 is designed to store information received from the ADC 14 and intended for standardization in blkue 29 the Norcia information from the RAM 21, 31 data display on the indicator 16 through the block 15 signal scan indicator and signal. Can be performed on the basis of chip CUT.

The second multiplexer 31 is used to alternately transmit information from the RAM 21, 31 data indication to the controller 30 of the transmission of information. Can be performed on the basis of chip CCP.

Counting the trigger 33 is designed to provide sequential operation of the multiplexers 22, 32 and the RAM 21, 31 data display. Chip K155TM2.

The device for the study of amplitude-frequency characteristics of two works in the following way.

In install mode:

In the first register 7 provides information that is intended for switching of sub-bands, the second register 8 is set information corresponding to the initial voltage of the oscillation frequency of the VCO 1, the third register 9 is set information corresponding to the voltage of the final generation frequency of the VCO 1. The voltage corresponding to the different frequency generation in each of the sections is performed using a third DAC 6. The sequence of voltage changes in it is determined by the information recorded in Otvoditsya in the recording mode information, then in the third counter 26 is written to parallel the required address of the RAM 25, on which information is recorded in the RAM 25 to the input data. This is repeated for each address of the RAM 25.

In the operating mode:

The third counter 26 through the fourth register 11 is transferred to the counting mode and the counting signals that come from the synchronizer 20 is a change of address RAM 25, respectively changing information at the input of the third DAC 6, which is read from the RAM 25 for each address. Changing the voltage at the output of the third DAC 6, which results ultimately in the VCO 1 to install different frequencies within a specified frequency range. To switch to another frequency range, it is necessary to interrupt the operating mode and reboot the initial conditions. To ensure operation of the VCO 1 in the mode that allows you to organize the study of the response of several different areas of the frequency range, synchronously with the scan TV display, without loss of resolution must synchronously, in accordance with the algorithm, modify the data in the first 7 and second 8 and third 9 registers, as in install mode and desktop mode.

The outputs of the block 27 with the Noah functions studied quadrupole 12, synchronously with the operation algorithm of the device. The output signal of the investigated two-port network 12 is converted into a proportional DC signal amplitude detector 13, and the digital code of the ADC 14. The signal from the synchronizer 20 of the first 23 and second 24 counters on the first input set to the initial zero state. The pulse from the synchronizer 20 is recording information from the ADC 14 in the fifth register 28. Counting the trigger 33 is allowed to write data from the fifth register 28 by the signal from the synchronizer 20 in the first RAM 21 data indicating at address zero. The first multiplexer 22 transmits information from the first output of the first counter 23, which is the address of the first RAM 21 data display. The signal from the synchronizer 20 at the counting input of the first counter 23 is changing the address for the data from the ADC 14. Again, write these data in the fifth register 28 and overwrite them in the first RAM 21 data display. This cycle is repeated. The number of cycles is determined by the bit width of the first counter 23. After a certain number of cycles of the first counter 23 at the second output pulse to the counting trigger 33, which changes its state. Now the first RAM 21 data display working mode is svertki indicator and signal. Addresses for the first RAM 21 data display in this case are set via the first multiplexer 22 of the second counter 24, to the second input of which receives pulses from unit 29 read.

Thus, when the first RAM 21 data display works on the recording of the input information, the second RAM 31 data display works in the mode of reading data in block 15 of the signal scan indicator and signal and Vice versa.

Data from the shaper 19 tags through the block 29 reading is transmitted in block 15 of the signal scan indicator and signal together with information from the first 21 or 31 of the second RAM data display.

Thus, the proposed device for the study of amplitude-frequency characteristics of two-port network has enhanced functionality that allows you to create a number of frequency sub-bands within the required frequency range scanning with high resolution in each frequency sub-band allows you to organize the formation of a signal at a speed commensurate with the speed of the sweep of the indicator is made on the basis of a television monitor. While it is possible to organize nerde of RAM data display and in parallel to read information from the other RAM data display, that also extends the functionality of the device, namely: it provides an indication of rapidly changing processes without interruption write/read and allows you to explore the processes, commensurate with the speed of the raster scan display.

Experimental studies of the proposed device for the study of amplitude-frequency characteristics (as VCO 1 was used VCO device X1-55) showed that it has in comparison with the prototype enhanced functionality, namely:

a) allows you to play on the screen of the indicator of the amplitude-frequency characteristics of several controlled interrelated frequency channels;

(b) the ability to organize the study of the frequency response with a speed comparable to the speed of the scan raster of the indicator that you want to exclude the effect of "rubber screwdriver when adjusting the investigational device;

C) provides a wide range of generated frequencies with high resolution;

g) allows for examination and adjustment of the quadrupole with electronic control in automatic mode.

All this helps improve performance and tocisco for the study of amplitude-frequency characteristics of two-port network, containing a voltage controlled oscillator, the input set of the frequency band which is connected to the output of the first register, the first input which is the input-output device and connected to the first input of the measuring frequency, the first inputs of the second to fourth registers and the input of the address decoder, the first to fourth outputs of which are connected respectively to the second inputs of the first to fourth registers, the outputs of the second and third registers respectively connected to the input of the first digital to analogue Converter (DAC) and the first input of the second DAC, a second input connected to the output of the third DAC, and the output from the second input of the adder, first the input and output of which are connected respectively with the output of the first DAC and control input of the oscillator voltage-controlled, the output of which is connected to the second input of the measuring frequency, the second input of the amplitude detector and the first input connection of the investigated two-port network, the output of which is the first input of the amplitude detector, the output of which is connected to the first input of the analog-to-digital Converter (ADC), the second input is connected to the first output of the synchronizer, the second output of which podkluchu connected to the output of the first multiplexer, the first and second inputs which are connected respectively to the first output of the first counter and the second counter, a first input connected to the third output of the synchronizer and the first input of the first counter, the second input is connected to the fourth output of the synchronizer, fifth output of which is connected to the input of the shaper labels, input-output of which is connected to the clock input and the second input is the output of the first buffer stage, the first input-output of which is connected to the first input-output of the second buffer stage connected to the first input of the first register, and the sixth output of the synchronizer is connected to the first input signal of the sweep of the indicator signal, the output of which is connected to the input of the indicator, characterized in that it introduced random access memory device, the third counter, block read, block pair, the second multiplexer, and the audit trigger, the second RAM data display, the third multiplexer and the fifth register, and the second input of the third counter connected to the sixth output of the decoder address, the fifth output of which is connected to the second input OW, the first input of which is combined with the first input of the third counter, and the output of and rogo register, input-output block read its output, the first to the third inputs respectively connected to the second input-output of the second buffer stage, the second input of the second counter, the seventh output of the synchronizer, the output of driver labels and the output of the second multiplexer, the first to the third input of which is connected respectively to the outputs of the first and second RAM data display and to the first output of the counting trigger, the second output of which is connected to the third input of the first RAM data display, the fourth input is connected to the fourth input of the second RAM data display and output of the fifth register, the first input of which is connected to the output of the ADC, and the second entrance to the ninth output of the synchronizer, the eighth output of which is connected to the fourth input of the third counter and the second output to the first input of the second RAM data display, the third and the second input of which is connected respectively to the output of the third multiplexer and to the first output of the counting trigger, the input of which is connected to the second output of the first counter, the first output of which is connected to the first input of the third multiplexer, the second and third inputs of which are connected respectively with the output of the second counter and the first outputs of the counting trigger, the input interface block is combined with the second input signal scan indicator and video first input of the RAM and the first input of the first register, the second and third inputs of the interface block connected respectively to the seventh output of the address decoder and the output of the third counter.

 

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