Universal generator arbitrary waveform

 

(57) Abstract:

Usage: in the generation of complex waveforms in simulation systems designed for the study of radio systems. The inventive generator comprises a generator of clock pulses, two counters, two decoder, eight registers, an element, OR trigger, three multiplexer, two schemes of comparison, three memory block, five adders, three multiplier, the unit's permanent memory, the code Converter-voltage, analog filter. Generator output signal is formed of an arbitrary shape with a variable law of modulation. The device enables the generation of arbitrary waveform, for example, with adjustable time delay. 3 Il.

The invention relates to computer technology and may find application in the generation of complex waveforms, and modeling systems for the study of radio systems.

In Fig.1 presents a functional diagram of the device of Fig.2 timing diagram of control signals of the device of Fig.3 timing diagrams pulsing signals of the device.

The device comprises a generator of clock pulses 1, counter hell the Lok memory 8, the second memory unit 9, the third memory block 10, a frequency register 11, the first multiplexer 12, the first adder 13, the second adder 14, the third adder 15, a fourth adder 16, the register width of the spectrum 17, the first register 18, the second multiplier 19, the unit's permanent memory 20, the first multiplier 21, the register number of harmonics 22, the first comparison circuit 23, the third multiplexer 24, the fifth adder 25, the third multiplier 26, the code Converter-voltage 27, an analog filter 28, the register time delay 29, the counter period 30, the second register 31, the case of amplitude 32, the register of the synchronization period 33, the second comparison circuit 34.

The information inputs of the frequency register 11, the spectrum width register 17 register of the number of harmonics 22, register time delay 29, register amplitude 32, register synchronization period 33 are input parameters, signal frequency, spectrum width, the number of harmonics of the spectrum, the time delay, amplitude and synchronization period, respectively. The information inputs of the second and third memory blocks 9, 10 are used as inputs of the task of the phases and amplitudes of the harmonics of the device. The input element OR 5 is the input synchronization signal delay device. The second output of the comparison circuit 34 C is A.

The output of clock 1 is connected to the counting input of the address counter 2. The first output of the address counter 2 is connected to the input of the decoder 3 departments. The second output of the address counter 2 is connected to the input of the decoder state 4. The third output of the address counter 2 is connected to the second input of the first differential amplifier 23 and the address inputs of the first, second and third memory blocks 8, 9, 10. The fourth output of the address counter 2 is connected to the counting input of counter 30. The first output of the decoder controls 3 is connected to the clock inputs of registers frequency 11, width, range 17, the number of harmonics 22, the amplitude of 32, the synchronization period 33, the third multiplier 26. The second output of the decoder controls 3 is connected to the control input of the first multiplexer 12. The third output of the decoder controls 3 is connected to the control input of the third multiplexer 24, the first information input of which is connected to the zero bus. The first input of the OR element 5 is connected to the second input of the trigger 6, the output of which is connected to the control input of the second multiplexer 7, the first information input of which is connected to the zero bus. Second input of the OR element 5 is connected to the first output of the comparison circuit 23 and the first input of the trigger is pout information input of the first multiplexer 12, the output of which is connected to the first input of the first adder 13, the output of which is connected to the first input of the second adder 14, the second input of the second multiplier 19 and the input of the first register 18, the output of which is connected to the second information input of the first multiplexer 12. The output spectrum width register 17 is connected to the second input of the first adder 13. The output of the register the number of harmonics 22 connected to the first input of the first differential amplifier 23. Output register delay 29 is connected to the first input of the second multiplier 19. The second input of the second adder 14 is connected to the output of the second multiplexer 7, the second information input of which is connected to the output of the first memory unit 8, the information input of which is connected to the output of the second adder 14 and the second input of the third adder 15, the first input of which is connected to the output of the second multiplier 19.

The output of the third adder 15 is connected to the first input of the fourth adder 16, the second input is connected to the output of the second memory block 9. The output of the fourth adder 16 is connected to the input of the unit's permanent memory 20, the output of which is connected to the first input of the first multiplier 21, the second input is connected to the output of the third memory block is th input of the third multiplier 26 and the input of the second register 31, the output of which is connected to the second information input of the third multiplexer 24, the output of which is connected to the second input of the fifth adder 25. The output of register amplitude 32 connected to the first input of the third multiplier 26, the output of which is connected to the input of the code Converter-voltage 27, the output of which is connected to the input of the analog filter 28. The output of counter 30 is connected to the first input of the second differential amplifier 34, the second input of which is connected to the output register of the synchronization period 33. The second output of the comparison circuit 34 is connected to boleosoma input of counter 30. The first output of the decoder state 4 is connected to the clock inputs of the fourth adder 16 and a second register 31. The second output of decoder States 4 is connected to the clock input of the first adder 13. The third output of the decoder state is connected to the clock inputs of the register 18, the second adder 14, the second and first tubes 19, 21. The fourth output of the decoder state is connected to the clock inputs of the first memory block 8, the third and the fifth adder 15, 25.

All blocks of the device are standard electronic units.

The device operates as follows.

The device implements the model is

While the signal amplitude;

i ordinal number of the harmonic component of the signal;

n is the number of harmonics;

ai, ithe normalized amplitude and phase of the i-th harmonics determined by the law of modulation of the generated signal.;

+i frequency i-th harmonic;

the frequency determines the center frequency of the signal;

- frequency shift, which determines the width of the spectrum and the high frequency signal;

is the time delay of the signal.

The parameters of the signal (1) is stored in the following blocks of the device. Frequency in the frequency register 11, a frequency shift in the spectrum width register 17, the number of harmonics n in the register the number of harmonics 22, the time delay of the signal in the register time delay 29, amplitude And is stored in the register amplitude 32.

The blocks of the device (see Fig.1) running of governors (see Fig.2) and pulsing (see Fig.3) of the pulses generated by the decoders departments 3 and state 4. When this clock 1 produces a uniform sequence of pulses, which is supplied to the counting input of the address counter 2. The address counter 2 sequentially changes its state. The signals from the two least significant bits of the address counter 2 serves on desirat the t pulses a, b, c, d (see Fig.3) with a period equal to the duration of formation of the full phase i-th harmonic. Sequence are supplied to clock inputs of the respective blocks. The set of all bit signals of the address counter 2 is supplied to the decoder 3 departments, three outputs which signals are formed (see Fig.2) U1(phase pulse (a), U2(phase pulse), U3(phase pulse (d). The duration of the signals U1U2U3equal pulsing, but have a repetition period of Taboutthat is equal to the processing time for a single value of a discrete signal S[kTo] (k 1,2, ordinal values of the signal).

The delay of the signal by the time interval is in the device relative to the external clock signal WITHIapplied to the input of the OR element 5 in the form of a short pulse with a period T equal to the repetition period of the signal S. the Device and produces its own internal synchronization signalotaken from the second of the comparison circuit 34, against which the measured delay In the internal synchronization mode signalomust be submitted as an input WITHIon the item OR 5.

The initial installation of the device the standing of the address counter 2. Resetting the address counter 2 is also every k-th step, after computing the current count of a discrete signal S[kTo] When this signal from the first output of the comparison circuit 23 is fed through the element OR 5 on Abdoulaye the input of the address counter 2.

The formation of the k-th value of the signal S in the current moment of time t kTooccurs as follows. After the reset of the address counter 2 signal from the first output of the comparison circuit 23, to indicate the beginning of a new cycle k for the formation of the signal S, the decoder controls 3 produces a control signal U1(see Fig. 2). This signal is the recording of new information (signal parameters) that are fed into the device from the outside in registers 11, 17, 22, 28, 31, 32. Then starts the calculation of the full phase i ( +i )(kTo- )iharmonic components i 1,2,n signal (1), starting with 1. The number of harmonics determines the state of the address counter 2, passed on his third release.

The first adder 13 in the i-th cycle (i 1) pulsing sequence of pulses a, b, c, d computes the value (+i )Toin step b by summing the output value ( +(i-1) )Toregister 18, is fed through the first multiplexer 12 to the first input of the first adder 13 with veline value (+i )Tois written to the buffer storage register 18. So is the cyclic frequency calculation of the i-th harmonic. The forming cycle of the first harmonic (i 1) is special. During its flow control signal U2removed from the second output of the decoder controls 3, the first multiplexer 12 connects to the input of the first adder 13 is not the case 18, and the frequency register 11 and tick b calculated value ( + )To.

Value ( +i )Toin the i-th loop from the output of the first adder 13 is supplied to the first input of the second adder 14. To the second input of the second adder 14 is fed through the second multiplexer 7 contents (+i )(k-1)Tothe i-th cell of the first memory block 8, which asked the address counter 2. The quantum is the summation of the numerical values at the inputs of the second adder 17, and calculates the variable phase (+i )kToi-th harmonic at the k-th step. The limitation of this phase, the range of allowable values [0,2 ] is due to capacity restrictions (grids) of the second adder 14. Tick d calculated phase (+i )kTois written into the cell i of the first memory block 8 for temporary storage and use in the next step k signal S[kTo]

Step k + 1 is SJ trigger 6, connecting the output of the multiplexer 7 to the zero bus. Then, a second adder 14 to the value (+i )Totaken from the output of the first adder 13, adds 0 and produces the sum ( +i )Tocorresponding to k 1 the beginning of period T on the formation of new values of the signal S. the Trigger 6 will be reset and disable the second multiplexer 7 from the neutral bus after the address counter 2 will pass through all States from i 1 to i n at step k-1. The state of i n+1 of the address counter 2 is registered by the first comparison circuit 23, which continuously compares the state of the address counter 2 with the value n+1 is transferred from the register the number of harmonics 22. When i n+1 of the first comparison circuit 23 produces an output signal which resets the trigger 6, which connects the output of the second multiplexer 7 to the output of the first memory block 8. This means the transition to the second step k 2 formation of a discrete signal S[kTo]

The variable phase of the i-th harmonic on k-th step ( +i )kToformed in the third adder 15 in step d with a constant phase ( +i ) Education constant phase produced by the second multiplier 19, which multiplies in accordance with the output value (+i )Tothe first adder 13 with the magnitude proportional passing/SUB>- ), which is transmitted to the first input of the fourth adder 16. To the second input of the fourth adder 16 receives the phaseifrom the i-th cell of the second memory block 9 (record valuesithe second memory unit 9 is carried out under control of external signals). The fourth adder 16 in tact and performs a sum of the input numbers, and thus calculates the total phasei( +i )(kTo- ) +ii-th harmonic.

Full phaseiharmonic i, which can vary in the range [0,2 ] is fed to the address input of the permanent memory unit 20. In the cell block 20 recorded trigonometric function value cos for different argument values in the range [0,2 ] From the output of the unit's permanent memory 20 is removed discrete harmonic signal cosiand transmitted to the first input of the first multiplier 21. To the second input of the multiplier 21 is served normalized amplitude aii-th harmonic (record values of aiin the third block memory 10 is performed under the action of external signals). The rhythm is the multiplication of the values and forms the value of aicosisupplied to the first input of the fifth adder 25.

The fifth adder 25 performs a sum of harmonic components, virabhadrasana on the first input of the adder 25, up to the value of ajcosjtransmitted to the second input of the adder 25 through the multiplexer 24 to the second register 31. The sum value is stored in the second register 31 in tact. After n cycles in the adder 25 is formed by the sum of ajcosjwith the precision of amplitude in digital form corresponding to the signal model (1). In a loop i 1 the value of the amount accumulated in the second register 31 in the previous step k-1 the formation of a discrete signal S[kTo] is reset to zero by connecting to one clock cycle of the second input of the adder 25 to the zero bus third multiplexer 24 to the signal U3(see Fig.2), taken from the third output of the decoder controls 3.

The value of ajcosjis supplied to the second input of the third multiplier 26, at the first input of which is fed the value of the amplitude And output register amplitude 32. The third multiplier performs multiplication of the input values under the action of the control signal U1. The output of the third multiplier is formed of a digital discrete signal S[kTo] Aajcosj. The digital signal is transformed into an analog voltage using the code Converter-voltage 27 and is applied to the analog filter 28. Analog is and. The output voltage of the analog filter 28 is an output signal S(t) device, an adequate model (1).

When the device is in the internal synchronization mode period of the generated signal T is determined numerical value written in the register of the synchronization period 33. The second comparison circuit 34 continuously compares the current state of the counter 30, is proportional to kTowith the contents of the T register of the synchronization period 33. When the counter reaches the period of 30 values of T, the second comparison circuit 34 produces an output signal Abdoulaye counter period 30. This signal is used as the output clock WITHoregarding changing the time delay generated signal S(t).

The use of the proposed device allows you to extend the scope of its application due to the generation of arbitrary waveform with adjustable time delay. The device is fully implemented on digital items and generate a signal with the given parameters with high accuracy. Managed parameters generated in real-time signal is the mean frequency, spectral width, the number of spectral costvolume the laws of the signal. You can easily spectral certification voltage signal.

The proposed device can be widely used as a generator of complex waveforms.

Universal generator arbitrary waveform containing the frequency register, the register width of the spectrum, the register number of harmonics, the clock, the address counter, the trigger, the first comparison circuit, three multiplexer, three memory block, the first and second adders, three multiplier, the count period, and the input parameters, frequency and width of the spectrum of the generator are informational inputs of the frequency register and the register width of the spectrum, respectively, the output of the frequency register is connected to the first information input of the first multiplexer, the output of which is connected to the first information input of the first adder, the output of the first memory block is connected to the first information input of the second multiplexer, characterized in that it introduced the case of the time delay, the register of the synchronization period, the second comparison circuit, the register of the amplitude, the element OR the decoder controls the first and second registers, the decoder States, third, fourth and fifth adders, block Pastora, moreover, the generator output clock pulses connected to the counting input of the address counter, the first output of which is connected to the input of the decoder controls the first output of which is connected to the state clock inputs of the registers of the frequency spectrum width, number of harmonics, amplitude, time delay of the synchronization period and the third multiplier, the second output of the address counter connected to the input of decoder States, the output of the first register is connected to the second information input of the first multiplexer, a control input which is connected to the second output of the decoder controls the output of the register width of the spectrum is connected to the second information input of the first adder, the output of which is connected to the information input of the first register and the first information input of the second adder and the second multiplier, the second information input of which is wired to the output register delay time, the output of the second multiplier connected to the first information input of the third adder, a second information input of which is connected to the information input of the first memory block and the output of the second adder, the second information input of which is connected to the output of the second multiplexer, the second informazioa the first input of the comparison circuit, the control input of the second multiplexer is connected to the trigger output, a reset input which is connected to the first input of the OR element and the first output of the comparison circuit, the second input of which is connected to the output of the register the number of harmonics, the information input of which is the reference input time delay signal generator, the reference input of the synchronization period of which is connected to the information input register of the synchronization period, the output of which is connected to the first input of the second differential amplifier, the second input of which is connected to the output of the meter period, the counting input of which is connected to the fourth output of the address counter, the second output of the comparison circuit connected to the input of a reset period and an output characteristic of the synchronization signal delay generator, the input job phases and amplitudes of the harmonics generator is connected to information inputs of the second and third memory blocks, respectively, the outputs of which are connected to the first information input of the fourth adder and the first multiplier, respectively, the output of the third adder connected to the second information input of the fourth adder, the output of which is connected to the information input unit's permanent memory, you is it a multiplexer connected to the bus logic zero generator, the third output of the address counter connected to the address inputs of the first, second and third memory blocks, the synchronization input signal delay generator connected to the information input of the trigger and the second input member OR the output of which is connected to the reset input of the address counter, the output of the first multiplier connected to the first information input of the fifth adder, the second information input of which is connected to the output of the third multiplexer, a control input which is connected to the third output of the decoder departments, the output of the second register connected to the second information input of the third multiplexer, the output of the fifth adder connected to the first information input of the third multiplier, the second information input of which is connected to the output register of the amplitude of the input amplitude signal generator connected to the information input register of the amplitude, the output of the third multiplier connected to the input of the code Converter - voltage, the output of which is connected to the input of the analog filter, the synchronization input of the third multiplier connected to the first output of the decoder controls the first output of the decoder States are connected to the state clock inputs of the fourth adder and the second register is connected to synchronou first adder, the third output of the decoder States are connected to the state clock inputs of the second adder and the second multiplier, the fourth output of the decoder States are connected to the control input of the recording-reading of the first memory block and synchronou fifth adder.

 

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